OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests/] [ddr31.S] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
/*****************************************************************
2
//                                                              //
3
//  Amber 2 Core DDR3 Memory Access                             //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Word accesses to random addresses in DDR3 memory            //
10
//  The test creates a list of addresses in an area of          //
11
//  boot_mem. It then writes to all addresses with data value   //
12
//  equal to address. Finally it reads back all locations       //
13
//  checking that the read value is correct.                    //
14
//                                                              //
15
//  Author(s):                                                  //
16
//      - Conor Santifort, csantifort.amber@gmail.com           //
17
//                                                              //
18
//////////////////////////////////////////////////////////////////
19
//                                                              //
20
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
21
//                                                              //
22
// This source file may be used and distributed without         //
23
// restriction provided that this copyright statement is not    //
24
// removed from the file and that any derivative work contains  //
25
// the original copyright notice and the associated disclaimer. //
26
//                                                              //
27
// This source file is free software; you can redistribute it   //
28
// and/or modify it under the terms of the GNU Lesser General   //
29
// Public License as published by the Free Software Foundation; //
30
// either version 2.1 of the License, or (at your option) any   //
31
// later version.                                               //
32
//                                                              //
33
// This source is distributed in the hope that it will be       //
34
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
35
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
36
// PURPOSE.  See the GNU Lesser General Public License for more //
37
// details.                                                     //
38
//                                                              //
39
// You should have received a copy of the GNU Lesser General    //
40
// Public License along with this source; if not, download it   //
41
// from http://www.opencores.org/lgpl.shtml                     //
42
//                                                              //
43
*****************************************************************/
44
 
45
#include "amber_registers.h"
46
#define ARRAY_WORDS 0x40
47
 
48
        .section .text
49
        .globl  main
50
main:
51
 
52
        @ --------------------------------------------
53
        @ Quick Pre-Test
54
        ldr     r0, DDRBase
55
        add     r4, r0, #12
56
        mov     r1, #0xff
57
        mov     r3, #0x55
58
 
59
        str     r1, [r0]
60
        str     r3, [r4]
61
        ldr     r2, [r0]
62
        ldr     r5, [r4]
63
 
64
        cmp     r1, r2
65
        movne   r10, #10
66
        bne     testfail
67
 
68
        cmp     r3, r5
69
        movne   r10, #15
70
        bne     testfail
71
 
72
        @ --------------------------------------------
73
        @ Create an array of random accresses
74
        @ Write data = address to each address
75
        @ Read back and verify data is correct
76
 
77
        @ setup
78
        ldr     r0,  AdrRanNum
79
        ldr     r9,  PointerBase
80
        ldr     r10, DDRBase
81
        mov     r11, #ARRAY_WORDS
82
 
83
1:      ldmia   r0,{r1-r8}
84
        add     r1, r10, r1, lsl #2
85
        add     r2, r1,  r2, lsl #2
86
        add     r3, r2,  r3, lsl #2
87
        add     r4, r3,  r4, lsl #2
88
        add     r5, r4,  r5, lsl #2
89
        add     r6, r5,  r6, lsl #2
90
        add     r7, r6,  r7, lsl #2
91
        add     r8, r7,  r8, lsl #2
92
 
93
        stmia   r9,{r1-r8}
94
 
95
        add     r9, r9, #32
96
        mov     r10, r8
97
 
98
        subs    r11, r11, #1
99
        bne     1b
100
        @ --------------------------------------------
101
 
102
        @ Write array to ddr memory
103
        ldr     r9,  PointerBase
104
        mov     r11, #ARRAY_WORDS
105
 
106
2:      ldmia   r9,  {r1-r8}
107
        str     r1, [r1]
108
        str     r2, [r2]
109
        str     r3, [r3]
110
        str     r4, [r4]
111
        str     r5, [r5]
112
        str     r6, [r6]
113
        str     r7, [r7]
114
        str     r8, [r8]
115
 
116
        add     r9, r9, #32
117
        subs    r11, r11, #1
118
        bne     2b
119
 
120
 
121
        @ --------------------------------------------
122
 
123
        @ Read array back from ddr and verify it
124
        ldr     r9,  PointerBase
125
        mov     r11, #ARRAY_WORDS
126
3:      ldmia   r9,  {r1-r8}
127
 
128
        @ r1
129
        ldr     r12, [r1]
130
        cmp     r12, r1
131
        movne   r10, #10
132
        bne     testfail
133
 
134
        @ r2
135
        ldr     r12, [r2]
136
        cmp     r12, r2
137
        movne   r10, #10
138
        bne     testfail
139
 
140
        @ r3
141
        ldr     r12, [r3]
142
        cmp     r12, r3
143
        movne   r10, #10
144
        bne     testfail
145
 
146
        @ r4
147
        ldr     r12, [r4]
148
        cmp     r12, r4
149
        movne   r10, #10
150
        bne     testfail
151
 
152
 
153
        @ r5
154
        ldr     r12, [r5]
155
        cmp     r12, r5
156
        movne   r10, #10
157
        bne     testfail
158
 
159
        @ r6
160
        ldr     r12, [r6]
161
        cmp     r12, r6
162
        movne   r10, #10
163
        bne     testfail
164
 
165
        @ r7
166
        ldr     r12, [r7]
167
        cmp     r12, r7
168
        movne   r10, #10
169
        bne     testfail
170
 
171
        @ r8
172
        ldr     r12, [r8]
173
        cmp     r12, r8
174
        movne   r10, #10
175
        bne     testfail
176
 
177
        add     r9, r9, #32
178
        subs    r11, r11, #1
179
        bne     3b
180
 
181
 
182
        b       testpass
183
 
184
 
185
testfail:
186
        ldr     r11, AdrTestStatus
187
        str     r10, [r11]
188
        b       testfail
189
 
190
testpass:
191
        ldr     r11, AdrTestStatus
192
        mov     r10, #17
193
        str     r10, [r11]
194
        b       testpass
195
 
196
 
197
/* Write 17 to this address to generate a Test Passed message */
198
AdrTestStatus:  .word ADR_AMBER_TEST_STATUS
199
AdrRanNum:      .word ADR_AMBER_TEST_RANDOM_NUM
200
PointerBase:    .word 0x1000
201
DDRBase:        .word 0x20000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.