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[/] [amber/] [trunk/] [hw/] [tests/] [ethmac_reg.S] - Blame information for rev 2

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 System Ethernet MAC Test                            //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests wishbone access to registers in the Ethernet MAC      //
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//  module.                                                     //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ Test reading of a register in the ethmac module
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        ldr     r0, AdrEthMacModer
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        ldr     r1, [r0]
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        ldr     r2, EthMacModerDefault
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        cmp     r1, r2
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        movne   r10, #10
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        bne     testfail
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        @ Turn on Duplex Mode, bit 10, and write back new value
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        orr     r1, r1, #0x400
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        str     r1, [r0]
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        @ Read back again to check the value
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        ldr     r3, [r0]
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        orr     r2, r2, #0x400
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        cmp     r3, r2
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        movne   r10, #20
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        bne     testfail
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        @ Set clock divider to 10 -> 3.3MHz MDC
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        ldr     r4, AdrEthMacMIIModer
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        mov     r5, #10
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        str     r5, [r4]
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        @ Set MII address - device [4:0], register [12:8]
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        ldr     r4, AdrEthMacMIIAddress
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        mov     r5,       #0x07
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        orr     r5, r5, #0x1600
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        str     r5, [r4]
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        @ receive (read PHY register) Command
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        ldr     r4, AdrEthMacMIICommand
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        mov     r5, #0x2
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        str     r5, [r4]
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        @ wait for busy, bit 1, to go low
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        @ Use r6 as a timeout
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        ldr     r4, AdrEthMacMIIStatus
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        mov     r6, #0
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wait_busy:
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        add     r6, r6, #1
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        cmp     r6, #0x400
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        @ Timeout error
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        moveq   r10, #30
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        beq     testfail
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        ldr     r5, [r4]
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        ands    r5, r5, #2
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        beq     readback
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        b       wait_busy
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readback:
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        ldr     r4, AdrEthMacMIIRxData
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        ldr     r5, [r4]
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        ldr     r6, ExpectedMIIReadBack
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        cmp     r5, r6
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        movne   r10, #100
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        bne     testfail
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:          .word  ADR_AMBER_TEST_STATUS
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AdrEthMacModer:         .word  ADR_ETHMAC_MODER
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AdrEthMacMIIModer:      .word  ADR_ETHMAC_MIIMODER
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AdrEthMacMIICommand:    .word  ADR_ETHMAC_MIICOMMAND
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AdrEthMacMIIAddress:    .word  ADR_ETHMAC_MIIADDRESS
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AdrEthMacMIITxData:     .word  ADR_ETHMAC_MIITXDATA
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AdrEthMacMIIRxData:     .word  ADR_ETHMAC_MIIRXDATA
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AdrEthMacMIIStatus:     .word  ADR_ETHMAC_MIISTATUS
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EthMacModerDefault:     .word  0x0000a000
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ExpectedMIIReadBack:    .word  0x0000ffff
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/* ========================================================================= */
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/* ========================================================================= */
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