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[/] [amber/] [trunk/] [hw/] [tests/] [ethmac_tx.S] - Blame information for rev 35

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 System Ethernet MAC Test                            //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests ethernet MAC frame transmit and receive functions     //
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//  and Ethmac DMA access to hiboot mem. Ethmac is put in       //
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//  loopback mode and a packet is transmitted and received.     //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        ldr     r0, AdrEthMacMemBase
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/* Write the Transmit Packet Buffer Descriptor */
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        ldr     r1, TxBufferW0
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        str     r1, [r0]
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        ldr     r1, TxBufferW1
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        add     r1, r1, #2      @ shift start by 2 bytes
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        str     r1, [r0, #4]
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/* Write the Receive Packet Buffer Descriptor */
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        ldr     r1, RxBufferW0
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        str     r1, [r0, #0x200]
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        ldr     r1, RxBufferW1
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        str     r1, [r0, #0x204]
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/* Copy a Frame into the transmit buffer */
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        ldr     r0, TxBufferW1
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        ldr     r1, =TxFrame
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        ldr     r2, =EndTxFrame
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        @ copy 8 words at a time
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1:      ldmia   r1!, {r3-r10}
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        stmia   r0!, {r3-r10}
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        cmp     r1, r2
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        blt     1b
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/*  Set Mode Register */
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        ldr     r0, AdrEthMacModer
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        ldr     r1, EthMacModerValue
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        str     r1, [r0]
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/* Start transmit */
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        ldr     r0, AdrEthMacMemBase
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        ldr     r1, TxBufferW0
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        orr     r1, r1, #0x8000
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        str     r1, [r0]
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89 35 csantifort
/* Check register values */
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        ldr     r0, AdrEthMacModer
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        ldr     r1, EthMacModerValue
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        ldr     r2, [r0]
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        cmp     r1, r2
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        movne   r10, #200
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        bne     testfail
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        ldr     r0, AdrEthMacMemBase
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        ldr     r1, TxBufferW0
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        orr     r1, r1, #0x8000
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        ldr     r2, [r0]
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        cmp     r1, r2
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        movne   r10, #220
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        bne     testfail
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106 2 csantifort
/* Wait until receive complete - Wait for Empty bit to go low */
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2:      ldr     r1, [r0, #0x200]
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        ands    r1, r1, #0x8000
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        bne     2b
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/* Wait a bit */
112 35 csantifort
        mov     r0, #80
113 2 csantifort
3:      subs    r0, r0, #1
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        bne     3b
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/* Check receive buffer */
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        ldr     r0, RxBufferW1
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        add     r3, r0, #2
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        ldr     r1, =TxFrame
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        add     r1, r1, #4
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        ldr     r2, =EndTxFrame
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        @ end of frame is crc which is different so dont check it
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        sub     r2, r2, #4
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        @ there is a 2-byte shift from tx to rx buffer
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        @ so load in the data from the rx buffer in 2 byte chunks
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        @ and re-arrange to match the tx buffer
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 4:     ldr     r4, [r0, #4]!
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        mov     r6, r4, lsl #16
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        ldr     r5, [r3], #4
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        ldr     r12, LoMask
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        and     r5, r5, r12
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        orr     r7, r5, r6
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        ldr     r8, [r1], #4
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        cmp     r7, r8
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        movne   r10, #100
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        bne     testfail
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        cmp     r1, r2
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        blt     4b
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:          .word  ADR_AMBER_TEST_STATUS
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AdrEthMacModer:         .word  ADR_ETHMAC_MODER
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AdrEthMacMIIModer:      .word  ADR_ETHMAC_MIIMODER
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AdrEthMacMIICommand:    .word  ADR_ETHMAC_MIICOMMAND
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AdrEthMacMIIAddress:    .word  ADR_ETHMAC_MIIADDRESS
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AdrEthMacMIITxData:     .word  ADR_ETHMAC_MIITXDATA
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AdrEthMacMIIRxData:     .word  ADR_ETHMAC_MIIRXDATA
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AdrEthMacMIIStatus:     .word  ADR_ETHMAC_MIISTATUS
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AdrEthMacMemBase:       .word  ADR_ETHMAC_BDBASE
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EthMacModerDefault:     .word  0x0000a000
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ExpectedMIIReadBack:    .word  0x0000ffff
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LoMask:                 .word  0x0000ffff
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/* [31:16] = length in bytes, Bit[15] = ready, Bit [13] = wrap bit */
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TxBufferW0:             .word  0x00a02800
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/* [31:16] = length in bytes, Bit[15] = empty, Bit [13] = wrap bit */
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RxBufferW0:             .word  0x0000a800
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182 35 csantifort
/* Buffer Pointer in Main Memory */
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TxBufferW1:             .word  0x00011000
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RxBufferW1:             .word  0x00011200
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/*
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 Ethmac Mode Register
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 [15] = Add pads to short frames
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 [13] = CRCEN
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 [7]  = loopback
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 [5]  = 1 for promiscuous, 0 rx only frames that match mac address
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 [1]  = txen
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 [0]  = rxen
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*/
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EthMacModerValue:       .word  0xa0a3
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TxFrame:
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.word  0x0e000000
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.word  0xa0583e0c  @ rx  1200: 3e0c 0e00
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.word  0x554e5300  @ rx  1204: 5300 a058
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.word  0x0008304c
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.word  0x90000045
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.word  0x00400000
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.word  0xd5b61140
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.word  0x0501a8c0
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.word  0x3201a8c0
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.word  0x01080203
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.word  0xb6c47c00
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.word  0xf67d4fc7
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.word  0x00000000
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.word  0x02000000
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.word  0xa3860100
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.word  0x03000000
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.word  0x06000000
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.word  0x01000000
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.word  0x18000000
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.word  0x025b8f02
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.word  0x02000000
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.word  0x00003170
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.word  0x00000000
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.word  0x00000000
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.word  0x00000000
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.word  0x00000000
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.word  0x00000000
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.word  0x24000000
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.word  0x01070001
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.word  0x00143ed5
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.word  0x00000000
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.word  0x2c043c7f
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.word  0x6c41657c
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.word  0x8cc37e87
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.word  0x2340a928
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.word  0x0026048e
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.word  0xec587a0e
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.word  0x00000000
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.word  0x00080000
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.word  0x00080000
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.word  0x00000000
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EndTxFrame:
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.word  0
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.word  0
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.word  0
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.word  0
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.word  0
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.word  0
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.word  0
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/* ========================================================================= */
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/* ========================================================================= */
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