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[/] [amber/] [trunk/] [hw/] [tests/] [flow1.S] - Blame information for rev 35

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1 15 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests instruction and data flow.                            //
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//  Specifically tests that a stm writing to cached memory      //
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//  also writes all data through to main memory.                //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        @ ---------------------
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        @ Enable the cache
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        @ ---------------------
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        mvn     r0,  #0
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        mcr     15, 0, r0, cr3, cr0, 0   @ cacheable area
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        mov     r0,  #1
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        mcr     15, 0, r0, cr2, cr0, 0   @ cache enable
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        mov     r13, #0x1000
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        orr     r13, r13, #0x08
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        ldr     r0, =Data1
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        ldm     r0,  {r1-r5}
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        stm     r13, {r1-r5}
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        @ load the data values back to put them into the data cache
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        ldm     r13, {r6-r10}
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        ldr     r0, =Data2
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        ldm     r0,  {r1-r5}
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        @ second stm will be to cached memory
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        stm     r13, {r1-r5}
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        @ load it back from the cache to check that
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        @ it was written to the cache correctly
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        ldm     r13, {r6-r10}
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        cmp     r1, r6
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        cmpeq   r2, r7
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        cmpeq   r3, r8
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        cmpeq   r4, r9
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        cmpeq   r5, r10
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        movne   r10, #100
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        bne     testfail
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        @ Clear the cache and read back the data from main memory
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        @ Write any value to cp15 reg1 to flush the cache
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        mcr     15, 0, r0, cr1, cr0, 0
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        ldm     r13, {r6-r10}
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        cmp     r1, r6
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        cmpeq   r2, r7
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        cmpeq   r3, r8
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        cmpeq   r4, r9
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        cmpeq   r5, r10
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        movne   r10, #200
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        bne     testfail
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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Data1:          .word  0x3
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                .word  0x4
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                .word  0x5
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                .word  0x6
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                .word  0x7
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Data2:          .word  0x13
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                .word  0x14
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                .word  0x15
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                .word  0x16
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                .word  0x17
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/* ========================================================================= */
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/* ========================================================================= */
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