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[/] [amber/] [trunk/] [hw/] [tests/] [stm1.S] - Blame information for rev 2

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests stm                                                   //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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@ ------------------------------------------
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@ 1. stmia   r14!, {r0-r13}
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@ ------------------------------------------
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        mov     r0,  #0
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        mov     r1,  #1
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        mov     r2,  #2
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        mov     r3,  #3
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        mov     r4,  #4
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        mov     r5,  #5
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        mov     r6,  #6
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        mov     r7,  #7
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        mov     r8,  #8
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        mov     r9,  #9
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        mov     r10, #10
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        mov     r11, #11
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        mov     r12, #12
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        mov     r13, #13
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        ldr     r14, StoreBase
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        stmia   r14!, {r0-r13}
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        @ Check that r14 was updated correctly
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        ldr     r0, StoreBase
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        add     r0, r0, #56  @ 14 x 4
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        cmp     r14, r0
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        movne   r10, #20
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        bne     testfail
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        @ Check that all values were saved to memory correctly
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        mov     r2, #0
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        ldr     r0, StoreBase
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loop1:  ldr     r1, [r0], #4
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        cmp     r1, r2
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        movne   r10, #30
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        bne     testfail
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        cmp     r2, #13
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        beq     start2
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        add     r2, r2, #1
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        b       loop1
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@ ------------------------------------------
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@ 2. stmib   r14!, {r0-r13}
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@ ------------------------------------------
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start2:
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        mov     r0,  #0
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        mov     r1,  #1
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        mov     r2,  #2
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        mov     r3,  #3
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        mov     r4,  #4
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        mov     r5,  #5
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        mov     r6,  #6
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        mov     r7,  #7
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        mov     r8,  #8
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        mov     r9,  #9
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        mov     r10, #10
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        mov     r11, #11
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        mov     r12, #12
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        mov     r13, #13
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        ldr     r14, StoreBase
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        stmib   r14!, {r0-r13}
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        @ Check that r14 was updated correctly
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        ldr     r0, StoreBase
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        add     r0, r0, #56  @ 14 x 4
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        cmp     r14, r0
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        movne   r10, #40
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        bne     testfail
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        @ Check that all values were saved to memory correctly
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        mov     r2, #0
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        ldr     r0, StoreBase
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        add     r0, r0, #4
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loop2:  ldr     r1, [r0], #4
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        cmp     r1, r2
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        movne   r10, #50
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        bne     testfail
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        cmp     r2, #13
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        beq     start3
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        add     r2, r2, #1
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        b       loop2
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@ ------------------------------------------
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@ 3. stmib   r14!, {r14}
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@ Test that the starting value of r14 is stored
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@ Test that storing a single register works correctly
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@ ------------------------------------------
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start3:
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        ldr     r14, StoreBase
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        stmib   r14!, {r14}
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        @ check that r14 got updated with a new value
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        ldr     r0, StoreBase
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        add     r1, r0, #4
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        cmp     r14, r1
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        movne   r10, #60
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        bne     testfail
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        @ check that the old value in r14 was stored
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        ldr     r2, [r1]
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        cmp     r2, r0
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        movne   r10, #70
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        bne     testfail
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@ ------------------------------------------
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@ 4. stmda   r0, {r14, pc}
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@ Test that r0 is not updated
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@ Test that the correct pc value is stored
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@ Test that Descending works
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@ ------------------------------------------
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start4:
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        mov     r14, #97
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        ldr     r0, StoreBase
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        mov     r2, pc  @ NB this must be immediately before
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                        @ the stm instruction to capture the
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                        @ correct pc value for checking below
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        stmda   r0, {lr, pc}
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        @ check that r0 did not get updated
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        ldr     r1, StoreBase
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        cmp     r0, r1
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        movne   r10, #70
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        bne     testfail
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        @ check that the correct pc value was stored
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        @ The value of the pc is 12 bytes after the address of the stm instruction
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        add     r2, r2, #8
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        ldr     r3, [r1]
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        cmp     r2, r3
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        movne   r10, #80
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        bne     testfail
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        @ check that r14 was stored in the correct place
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        ldr     r1, StoreBase
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        sub     r1, r1, #4
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        ldr     r4, [r1]
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        cmp     r4, #97
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        movne   r10, #90
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        bne     testfail
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@ ------------------------------------------
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@ 5. stmdb   r9!, {r0, r9, r10}
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@ Test non-continuous range of registers
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@ Test that r9 is updated correctly
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@ ------------------------------------------
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        mov     r0,  #17
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        ldr     r9,  StoreBase
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        mov     r10, #18
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        stmdb   r9!, {r0, r9, r10}
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        ldr     r3,  StoreBase
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        sub     r3,  r3, #12
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        ldr     r4,  [r3], #4
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        cmp     r4,  #17
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        movne   r10, #100
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        bne     testfail
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        @ r9 is the second register on the list, so the updated
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        @ value gets stored in StoreBase - 8
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        ldr     r4,  [r3]       @ r3 points to StoreBase - 8
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        ldr     r3,  StoreBase
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        sub     r3,  r3, #12
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        cmp     r3,  r4
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        movne   r10, #110
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        bne     testfail
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        ldr     r3,  StoreBase
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        sub     r3,  r3, #4
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        ldr     r4,  [r3]
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        cmp     r4,  #18
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        movne   r10, #120
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        bne     testfail
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@ ------------------------------------------
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@ ------------------------------------------
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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AdrData1:       .word  Data1
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AdrData2:       .word  Data2
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StoreBase:      .word  0x800
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Data1:          .word  0x12345678
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Data2:          .word  0xffccbbaa
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Data3:          .word  0x12345600
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/* ========================================================================= */
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/* ========================================================================= */
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