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[/] [amber/] [trunk/] [hw/] [tests/] [strb.S] - Blame information for rev 2

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Instruction Test                               //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests str and strb with different indexing modes.           //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        /* Store single Byte */
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        ldr     r0,  StoreBase
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        add     r0,  r0, #4
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        mov     r4,  #0
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        str     r4,  [r0]
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        ldr     r1,  Data1
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        strb    r1, [r0]
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        and     r3, r1, #0xff
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        ldr     r2, [r0]
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        cmp     r3, r2
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        movne   r10, #10   @ error number
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        bne     testfail
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        /* Store Byte at address 1, 2 and 3 */
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        ldr     r0,  StoreBase
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        add     r0,  r0, #8
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        mov     r4,  #0
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        @ start by writing a word of 0 to the memory location
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        str     r4, [r0], #1
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        ldr     r1,  Data1
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        @ then store byte 0 in r1 to 3 positions
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        @ in the memory location
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        strb    r1, [r0], #1
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        strb    r1, [r0], #1
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        strb    r1, [r0], #1
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        @ load back the memory location and check its contents
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        ldr     r0,  StoreBase
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        ldr     r2,  [r0, #8]
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        ldr     r3,  Data3
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        cmp     r2, r3
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        movne   r10, #20   @ error number
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        bne     testfail
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        /* Reverse order of bytes */
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        @ read in Data1 and store it out to
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        @ StoreBase + 12, reversing the order
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        @ of the bytes
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        ldr     r2,  StoreBase
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        add     r2, r2, #12
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        ldr     r1,  Data1
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        @ store byte 3
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        mov     r1, r1, ror #24
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        strb    r1, [r2], #1
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        @ store byte 2
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        mov     r1, r1, ror #24
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        strb    r1, [r2], #1
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        @ store byte 1
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        mov     r1, r1, ror #24
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        strb    r1, [r2], #1
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        @ store byte 0
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        mov     r1, r1, ror #24
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        strb    r1, [r2], #1
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        ldr     r2,  StoreBase
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        add     r2, r2, #12
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        ldr     r3, [r2]
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        ldr     r4, Data4
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        cmp     r3, r4
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        movne   r10, #30
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        bne     testfail
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        /* Store word */
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        ldr     r0,  StoreBase
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        ldr     r1,  Data1
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        str     r1, [r0]
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        ldr     r2, [r0]
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        cmp     r1, r2
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        movne   r10, #50   @ error number
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        bne     testfail
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@ ------------------------------------------
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@ ------------------------------------------
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        b       testpass
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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AdrData1:       .word  Data1
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AdrData2:       .word  Data2
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StoreBase:      .word  0x800
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Data1:          .word  0x12345678
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Data2:          .word  0xffccbbaa
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Data3:          .word  0x78787800
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Data4:          .word  0x78563412
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/* ========================================================================= */
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/* ========================================================================= */
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