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[/] [amber/] [trunk/] [hw/] [tests/] [swi.S] - Blame information for rev 2

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1 2 csantifort
/*****************************************************************
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//                                                              //
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//  Amber 2 Core Interrupt Test                                 //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Tests the software interrupt - swi.                         //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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*****************************************************************/
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#include "amber_registers.h"
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        .section .text
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        .globl  main
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main:
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        /* 0x00 Reset Interrupt vector address */
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        b       start
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        /* 0x04 Undefined Instruction Interrupt vector address */
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        b       testfail
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        /* 0x08 SWI Interrupt vector address */
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        b       service_swi
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        /* 0x0c Prefetch abort Interrupt vector address */
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        b       testfail
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        /* 0x10 Data abort Interrupt vector address */
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        b       testfail
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        b       testfail
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        /* 0x18 IRQ vector address */
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        b       testfail
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        /* 0x1c FIRQ vector address */
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        b       testfail
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start:
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        /* Switch to User Mode */
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        /* and unset interrupt mask bits */
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        mov     r0,   #0x00000000
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        teqp    pc, r0
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        @ Check that we're in user mode now
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        mov     r2, pc
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        ands    r2, r2, #3
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        movne   r10, #10
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        bne     testfail
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        @ ---------------------------------
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        @ Test a SWI that does execute
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        @ ---------------------------------
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        swieq   #0xff8877
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pos1:   b       testpass
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        b       testfail
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        b       testfail
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continue:
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        mov     r1, #3
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        mov     r2, #2
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        cmp     r1, r2
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        moveq   r3, #17
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        @ ---------------------------------
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        @ Test a SWI that does not execute
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        @ ---------------------------------
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        swieq   #0xff1122
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        moveq   r10, #20
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        beq     testfail
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        bne     testpass
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@ ---------------------------------
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@ Test Conditional Execution of SWI
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@ ---------------------------------
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service_swi:
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        @ Check that the address immediately
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        @ after the SWI instruction is saved
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        @ in the supervisor mode lr
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        ldr     r0, Adrpos1
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        ldr     r13, PCMask
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        and     r14, r14, r13
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        cmp     r0, r14
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        movne   r10, #20
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        bne     testfail
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        @ Check that we're back in supervisor mode now
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        mov     r2, pc
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        @ filter out all bits other than mode bits
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        and     r2, r2, #0x3
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        cmp     r2, #0x00000003
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        movne   r10, #30
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        bne     testfail
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@ ------------------------------------------
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@ Retun after interrupt
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@ ------------------------------------------
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        b       continue
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testfail:
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        ldr     r11, AdrTestStatus
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        str     r10, [r11]
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        b       testfail
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testpass:
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        ldr     r11, AdrTestStatus
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        mov     r10, #17
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        str     r10, [r11]
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        b       testpass
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@ put this data section here so its reachable
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@ by the 8-bit immediate offset in LDRH
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Data1:          .word  0x12345678
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Data2:          .word  0xffccbbaa
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Data3:          .word  0xffccbbaa
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Data4:          .word  0x12345600
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Data5:          .word  0x0000ffff
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Data6:          .word  0xffff0000
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Data7:          .word  0x5678ffff
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Data8:          .word  0xffffffff
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PCMask:         .word  0x03fffffc
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/* Write 17 to this address to generate a Test Passed message */
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AdrTestStatus:  .word  ADR_AMBER_TEST_STATUS
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AdrData1:       .word  Data1
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AdrData2:       .word  Data2
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AdrData3:       .word  Data3
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AdrData4:       .word  Data4
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AdrData5:       .word  Data5
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AdrData6:       .word  Data6
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AdrData7:       .word  Data7
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AdrData8:       .word  Data8
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Adrpos1:        .word  pos1
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/* ========================================================================= */
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/* ========================================================================= */
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