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Missing files. These files are not provided as part of the

amber package for copyright reasons. They are only needed

to do simulations with real FPGA comonent models.

The following files are generated by Xilinx coregen

for the DDR3 Interface in the Spartan-6 FPGA used in the SP605

development board.

xs6_ddr3/iodrp_controller.v

xs6_ddr3/iodrp_mcb_controller.v

xs6_ddr3/mcb_ddr3.v

xs6_ddr3/mcb_raw_wrapper.v

xs6_ddr3/mcb_soft_calibration_top.v

xs6_ddr3/mcb_soft_calibration.v

xs6_ddr3/memc3_infrastructure.v

xs6_ddr3/memc3_wrapper.v

The following files are generated by Xilinx coregen

for the DDR3 Interface in the Virtex-6 FPGA.

xv6_ddr3/arb_mux.v

xv6_ddr3/arb_row_col.v

xv6_ddr3/arb_select.v

xv6_ddr3/bank_cntrl.v

xv6_ddr3/bank_common.v

xv6_ddr3/bank_compare.v

xv6_ddr3/bank_mach.v

xv6_ddr3/bank_queue.v

xv6_ddr3/bank_state.v

xv6_ddr3/circ_buffer.v

xv6_ddr3/clk_ibuf.v

xv6_ddr3/col_mach.v

xv6_ddr3/ddr2_ddr3_chipscope.v

xv6_ddr3/ecc_buf.v

xv6_ddr3/ecc_dec_fix.v

xv6_ddr3/ecc_gen.v

xv6_ddr3/ecc_merge_enc.v

xv6_ddr3/infrastructure.v

xv6_ddr3/iodelay_ctrl.v

xv6_ddr3/mc.v

xv6_ddr3/memc_ui_top.v

xv6_ddr3/mem_intfc.v

xv6_ddr3/phy_ck_iob.v

xv6_ddr3/phy_clock_io.v

xv6_ddr3/phy_control_io.v

xv6_ddr3/phy_data_io.v

xv6_ddr3/phy_dly_ctrl.v

xv6_ddr3/phy_dm_iob.v

xv6_ddr3/phy_dq_iob.v

xv6_ddr3/phy_dqs_iob.v

xv6_ddr3/phy_init.v

xv6_ddr3/phy_ocb_mon_top.v

xv6_ddr3/phy_ocb_mon.v

xv6_ddr3/phy_pd_top.v

xv6_ddr3/phy_pd.v

xv6_ddr3/phy_rdclk_gen.v

xv6_ddr3/phy_rdctrl_sync.v

xv6_ddr3/phy_rddata_sync.v

xv6_ddr3/phy_rdlvl.v

xv6_ddr3/phy_read.v

xv6_ddr3/phy_top.v

xv6_ddr3/phy_write.v

xv6_ddr3/phy_wrlvl.v

xv6_ddr3/rank_cntrl.v

xv6_ddr3/rank_common.v

xv6_ddr3/rank_mach.v

xv6_ddr3/rd_bitslip.v

xv6_ddr3/round_robin_arb.v

xv6_ddr3/ui_cmd.v

xv6_ddr3/ui_rd_data.v

xv6_ddr3/ui_top.v

xv6_ddr3/ui_wr_data.v

xv6_ddr3/xv6_ddr3.v

The following files provide a highly accurate model of a real

DDR3 memory device. They are supplied by Xilinx along with

a DDR3 memory interface generated by coregen.

tb/ddr3_model_c3.v

tb/ddr3_model_parameters_c3.vh