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[/] [amber/] [trunk/] [hw/] [vlog/] [README.txt] - Blame information for rev 2

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1 2 csantifort
Missing files. These files are not provided as part of the
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amber package for copyright reasons. They are only needed
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to do simulations with real FPGA comonent models.
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The following files are generated by Xilinx coregen
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for the DDR3 Interface in the Spartan-6 FPGA used in the SP605
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development board.
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xs6_ddr3/iodrp_controller.v
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xs6_ddr3/iodrp_mcb_controller.v
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xs6_ddr3/mcb_ddr3.v
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xs6_ddr3/mcb_raw_wrapper.v
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xs6_ddr3/mcb_soft_calibration_top.v
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xs6_ddr3/mcb_soft_calibration.v
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xs6_ddr3/memc3_infrastructure.v
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xs6_ddr3/memc3_wrapper.v
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The following files are generated by Xilinx coregen
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for the DDR3 Interface in the Virtex-6 FPGA.
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xv6_ddr3/arb_mux.v
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xv6_ddr3/arb_row_col.v
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xv6_ddr3/arb_select.v
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xv6_ddr3/bank_cntrl.v
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xv6_ddr3/bank_common.v
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xv6_ddr3/bank_compare.v
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xv6_ddr3/bank_mach.v
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xv6_ddr3/bank_queue.v
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xv6_ddr3/bank_state.v
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xv6_ddr3/circ_buffer.v
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xv6_ddr3/clk_ibuf.v
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xv6_ddr3/col_mach.v
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xv6_ddr3/ddr2_ddr3_chipscope.v
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xv6_ddr3/ecc_buf.v
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xv6_ddr3/ecc_dec_fix.v
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xv6_ddr3/ecc_gen.v
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xv6_ddr3/ecc_merge_enc.v
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xv6_ddr3/infrastructure.v
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xv6_ddr3/iodelay_ctrl.v
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xv6_ddr3/mc.v
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xv6_ddr3/memc_ui_top.v
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xv6_ddr3/mem_intfc.v
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xv6_ddr3/phy_ck_iob.v
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xv6_ddr3/phy_clock_io.v
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xv6_ddr3/phy_control_io.v
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xv6_ddr3/phy_data_io.v
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xv6_ddr3/phy_dly_ctrl.v
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xv6_ddr3/phy_dm_iob.v
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xv6_ddr3/phy_dq_iob.v
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xv6_ddr3/phy_dqs_iob.v
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xv6_ddr3/phy_init.v
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xv6_ddr3/phy_ocb_mon_top.v
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xv6_ddr3/phy_ocb_mon.v
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xv6_ddr3/phy_pd_top.v
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xv6_ddr3/phy_pd.v
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xv6_ddr3/phy_rdclk_gen.v
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xv6_ddr3/phy_rdctrl_sync.v
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xv6_ddr3/phy_rddata_sync.v
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xv6_ddr3/phy_rdlvl.v
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xv6_ddr3/phy_read.v
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xv6_ddr3/phy_top.v
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xv6_ddr3/phy_write.v
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xv6_ddr3/phy_wrlvl.v
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xv6_ddr3/rank_cntrl.v
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xv6_ddr3/rank_common.v
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xv6_ddr3/rank_mach.v
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xv6_ddr3/rd_bitslip.v
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xv6_ddr3/round_robin_arb.v
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xv6_ddr3/ui_cmd.v
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xv6_ddr3/ui_rd_data.v
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xv6_ddr3/ui_top.v
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xv6_ddr3/ui_wr_data.v
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xv6_ddr3/xv6_ddr3.v
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The following files provide a highly accurate model of a real
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DDR3 memory device. They are supplied by Xilinx along with
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a DDR3 memory interface generated by coregen.
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tb/ddr3_model_c3.v
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tb/ddr3_model_parameters_c3.vh
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