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//////////////////////////////////////////////////////////////////
//                                                              //
//  Co-processor module for Amber 2 Core                        //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Co_processor 15 registers and control signals               //                                                           //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module a23_coprocessor
(
input                       i_clk,
input                       i_fetch_stall,    // stall all stages of the cpu at the same time
input       [2:0]           i_copro_opcode1,
input       [2:0]           i_copro_opcode2,
input       [3:0]           i_copro_crn,      // Register Number 
input       [3:0]           i_copro_crm,
input       [3:0]           i_copro_num,
input       [1:0]           i_copro_operation,
input       [31:0]          i_copro_write_data,
 
input                       i_fault,          // high to latch the fault address and status
input       [7:0]           i_fault_status,
input       [31:0]          i_fault_address,  // the address that caused the fault
 
output reg  [31:0]          o_copro_read_data,
output                      o_cache_enable,
output                      o_cache_flush,
output      [31:0]          o_cacheable_area
);
 
// Bit 0 - Cache on(1)/off
// Bit 1 - Shared (1) or seperate User/Supervisor address space
// Bit 2 - address monitor mode(1)
reg [2:0]  cache_control = 3'b000;
 
// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable
// Bit 1 - next 2MB region etc.
reg [31:0] cacheable_area = 32'h0;
 
// Marks memory regions as read only so writes are ignored by the cache
// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable
// Bit 1 - next 2MB region etc.
reg [31:0] updateable_area = 32'h0;
 
// Accesses to a region with a flag set in this register cause the
// cache to flush
// Bit 0 - 2MB memory from 0 to 0x01fffff
// Bit 1 - next 2MB region etc.
reg [31:0] disruptive_area = 32'h0;
 
 
reg [7:0]  fault_status  = 'd0;
reg [31:0] fault_address = 'd0;  // the address that caused the fault
 
wire       copro15_reg1_write;
 
 
// ---------------------------
// Outputs
// ---------------------------
assign o_cache_enable   = cache_control[0];
assign o_cache_flush    = copro15_reg1_write;
assign o_cacheable_area = cacheable_area;
 
// ---------------------------
// Capture an access fault address and status
// ---------------------------
always @ ( posedge i_clk )
    if ( !i_fetch_stall )
        begin
        if ( i_fault )
            begin
 
            `ifdef A23_COPRO15_DEBUG
            $display ("Fault status  set to 0x%08x", i_fault_status);
            $display ("Fault address set to 0x%08x", i_fault_address);
            `endif
            fault_status    <= i_fault_status;
            fault_address   <= i_fault_address;
            end
        end
 
 
// ---------------------------
// Register Writes
// ---------------------------
always @ ( posedge i_clk )
    if ( !i_fetch_stall )
        begin
        if ( i_copro_operation == 2'd2 )
            case ( i_copro_crn )
                4'd2: cache_control   <= i_copro_write_data[2:0];
                4'd3: cacheable_area  <= i_copro_write_data[31:0];
                4'd4: updateable_area <= i_copro_write_data[31:0];
                4'd5: disruptive_area <= i_copro_write_data[31:0];
            endcase
        end
 
// Flush the cache
assign copro15_reg1_write = !i_fetch_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;
 
 
// ---------------------------
// Register Reads   
// ---------------------------
always @ ( posedge i_clk )
    if ( !i_fetch_stall )
        case ( i_copro_crn )
            // ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision
            4'd0:    o_copro_read_data <= 32'h4156_0300;
            4'd2:    o_copro_read_data <= {29'd0, cache_control};
            4'd3:    o_copro_read_data <= cacheable_area;
            4'd4:    o_copro_read_data <= updateable_area;
            4'd5:    o_copro_read_data <= disruptive_area;
            4'd6:    o_copro_read_data <= {24'd0, fault_status };
            4'd7:    o_copro_read_data <= fault_address;
            default: o_copro_read_data <= 32'd0;
        endcase
 
 
 
// ========================================================
// Debug code - not synthesizable
// ========================================================
 
`ifdef A23_COPRO15_DEBUG
//synopsys translate_off
reg [1:0]  copro_operation_d1;
reg [3:0]  copro_crn_d1;
 
always @( posedge i_clk )
    if ( !i_fetch_stall )
        begin
        copro_operation_d1  <= i_copro_operation;
        copro_crn_d1        <= i_copro_crn;
        end
 
always @( posedge i_clk )
    if ( !i_fetch_stall )
        begin
        if ( i_copro_operation == 2'd2 )  // mcr
            case ( i_copro_crn )
                4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #2, Cache Control", i_copro_write_data); end
                4'd 3: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #3, Cacheable area", i_copro_write_data); end
                4'd 4: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #4, Updateable area", i_copro_write_data); end
                4'd 5: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to   Co-Pro 15 #5, Disruptive area", i_copro_write_data); end
            endcase
 
        if ( copro_operation_d1 == 2'd1 ) // mrc
            case ( copro_crn_d1 )
                4'd 0: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #0, ID Register", o_copro_read_data); end
                4'd 2: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #2, Cache control", o_copro_read_data); end
                4'd 3: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #3, Cacheable area", o_copro_read_data); end
                4'd 4: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #4, Updateable area", o_copro_read_data); end
                4'd 5: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #4, Disruptive area", o_copro_read_data); end
                4'd 6: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #6, Fault Status Register", o_copro_read_data); end
                4'd 7: begin `TB_DEBUG_MESSAGE $display ("Read  0x%08h from Co-Pro 15 #7, Fault Address Register", o_copro_read_data); end
            endcase
    end
//synopsys translate_on
`endif
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Co-processor module for Amber 2 Core //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Co_processor 15 registers and control signals // //`
10			`// Author(s): //`
11			`// - Conor Santifort, csantifort.amber@gmail.com //`
12			`// //`
13			`//////////////////////////////////////////////////////////////////`
14			`// //`
15			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
16			`// //`
17			`// This source file may be used and distributed without //`
18			`// restriction provided that this copyright statement is not //`
19			`// removed from the file and that any derivative work contains //`
20			`// the original copyright notice and the associated disclaimer. //`
21			`// //`
22			`// This source file is free software; you can redistribute it //`
23			`// and/or modify it under the terms of the GNU Lesser General //`
24			`// Public License as published by the Free Software Foundation; //`
25			`// either version 2.1 of the License, or (at your option) any //`
26			`// later version. //`
27			`// //`
28			`// This source is distributed in the hope that it will be //`
29			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
30			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
31			`// PURPOSE. See the GNU Lesser General Public License for more //`
32			`// details. //`
33			`// //`
34			`// You should have received a copy of the GNU Lesser General //`
35			`// Public License along with this source; if not, download it //`
36			`// from http://www.opencores.org/lgpl.shtml //`
37			`// //`
38			`//////////////////////////////////////////////////////////////////`
39
40
41	15	csantifort	`module a23_coprocessor`
42	2	csantifort	`(`
43			`input i_clk,`
44			`input i_fetch_stall, // stall all stages of the cpu at the same time`
45			`input [2:0] i_copro_opcode1,`
46			`input [2:0] i_copro_opcode2,`
47			`input [3:0] i_copro_crn, // Register Number`
48			`input [3:0] i_copro_crm,`
49			`input [3:0] i_copro_num,`
50			`input [1:0] i_copro_operation,`
51			`input [31:0] i_copro_write_data,`
52
53			`input i_fault, // high to latch the fault address and status`
54			`input [7:0] i_fault_status,`
55			`input [31:0] i_fault_address, // the address that caused the fault`
56
57			`output reg [31:0] o_copro_read_data,`
58			`output o_cache_enable,`
59			`output o_cache_flush,`
60			`output [31:0] o_cacheable_area`
61			`);`
62
63			`// Bit 0 - Cache on(1)/off`
64			`// Bit 1 - Shared (1) or seperate User/Supervisor address space`
65			`// Bit 2 - address monitor mode(1)`
66			`reg [2:0] cache_control = 3'b000;`
67
68			`// Bit 0 - 2MB memory from 0 to 0x01fffff cacheable(1)/not cachable`
69			`// Bit 1 - next 2MB region etc.`
70			`reg [31:0] cacheable_area = 32'h0;`
71
72			`// Marks memory regions as read only so writes are ignored by the cache`
73			`// Bit 0 - 2MB memory from 0 to 0x01fffff updateable(1)/not updateable`
74			`// Bit 1 - next 2MB region etc.`
75			`reg [31:0] updateable_area = 32'h0;`
76
77			`// Accesses to a region with a flag set in this register cause the`
78			`// cache to flush`
79			`// Bit 0 - 2MB memory from 0 to 0x01fffff`
80			`// Bit 1 - next 2MB region etc.`
81			`reg [31:0] disruptive_area = 32'h0;`
82
83
84			`reg [7:0] fault_status = 'd0;`
85			`reg [31:0] fault_address = 'd0; // the address that caused the fault`
86
87			`wire copro15_reg1_write;`
88
89
90			`// ---------------------------`
91			`// Outputs`
92			`// ---------------------------`
93			`assign o_cache_enable = cache_control[0];`
94			`assign o_cache_flush = copro15_reg1_write;`
95			`assign o_cacheable_area = cacheable_area;`
96
97			`// ---------------------------`
98			`// Capture an access fault address and status`
99			`// ---------------------------`
100			`always @ ( posedge i_clk )`
101			`if ( !i_fetch_stall )`
102			`begin`
103			`if ( i_fault )`
104			`begin`
105
106	15	csantifort	`ifdef A23_COPRO15_DEBUG
107	2	csantifort	`$display ("Fault status set to 0x%08x", i_fault_status);`
108			`$display ("Fault address set to 0x%08x", i_fault_address);`
109			`endif
110			`fault_status <= i_fault_status;`
111			`fault_address <= i_fault_address;`
112			`end`
113			`end`
114
115
116			`// ---------------------------`
117			`// Register Writes`
118			`// ---------------------------`
119			`always @ ( posedge i_clk )`
120			`if ( !i_fetch_stall )`
121			`begin`
122			`if ( i_copro_operation == 2'd2 )`
123			`case ( i_copro_crn )`
124			`4'd2: cache_control <= i_copro_write_data[2:0];`
125			`4'd3: cacheable_area <= i_copro_write_data[31:0];`
126			`4'd4: updateable_area <= i_copro_write_data[31:0];`
127			`4'd5: disruptive_area <= i_copro_write_data[31:0];`
128			`endcase`
129			`end`
130
131			`// Flush the cache`
132			`assign copro15_reg1_write = !i_fetch_stall && i_copro_operation == 2'd2 && i_copro_crn == 4'd1;`
133
134
135			`// ---------------------------`
136			`// Register Reads`
137			`// ---------------------------`
138			`always @ ( posedge i_clk )`
139			`if ( !i_fetch_stall )`
140			`case ( i_copro_crn )`
141			`// ID Register - [31:24] Company id, [23:16] Manuf id, [15:8] Part type, [7:0] revision`
142	15	csantifort	`4'd0: o_copro_read_data <= 32'h4156_0300;`
143	2	csantifort	`4'd2: o_copro_read_data <= {29'd0, cache_control};`
144			`4'd3: o_copro_read_data <= cacheable_area;`
145			`4'd4: o_copro_read_data <= updateable_area;`
146			`4'd5: o_copro_read_data <= disruptive_area;`
147			`4'd6: o_copro_read_data <= {24'd0, fault_status };`
148			`4'd7: o_copro_read_data <= fault_address;`
149			`default: o_copro_read_data <= 32'd0;`
150			`endcase`
151
152
153
154			`// ========================================================`
155			`// Debug code - not synthesizable`
156			`// ========================================================`
157
158	15	csantifort	`ifdef A23_COPRO15_DEBUG
159	2	csantifort	`//synopsys translate_off`
160			`reg [1:0] copro_operation_d1;`
161			`reg [3:0] copro_crn_d1;`
162
163			`always @( posedge i_clk )`
164			`if ( !i_fetch_stall )`
165			`begin`
166			`copro_operation_d1 <= i_copro_operation;`
167			`copro_crn_d1 <= i_copro_crn;`
168			`end`
169
170			`always @( posedge i_clk )`
171			`if ( !i_fetch_stall )`
172			`begin`
173			`if ( i_copro_operation == 2'd2 ) // mcr`
174			`case ( i_copro_crn )`
175			4'd 1: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #1, Flush Cache", i_copro_write_data); end
176			4'd 2: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #2, Cache Control", i_copro_write_data); end
177			4'd 3: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #3, Cacheable area", i_copro_write_data); end
178			4'd 4: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #4, Updateable area", i_copro_write_data); end
179			4'd 5: begin `TB_DEBUG_MESSAGE $display ("Write 0x%08h to Co-Pro 15 #5, Disruptive area", i_copro_write_data); end
180			`endcase`
181
182			`if ( copro_operation_d1 == 2'd1 ) // mrc`
183			`case ( copro_crn_d1 )`
184			4'd 0: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #0, ID Register", o_copro_read_data); end
185			4'd 2: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #2, Cache control", o_copro_read_data); end
186			4'd 3: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #3, Cacheable area", o_copro_read_data); end
187			4'd 4: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #4, Updateable area", o_copro_read_data); end
188			4'd 5: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #4, Disruptive area", o_copro_read_data); end
189			4'd 6: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #6, Fault Status Register", o_copro_read_data); end
190			4'd 7: begin `TB_DEBUG_MESSAGE $display ("Read 0x%08h from Co-Pro 15 #7, Fault Address Register", o_copro_read_data); end
191			`endcase`
192			`end`
193			`//synopsys translate_on`
194			`endif
195
196			`endmodule`
197

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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_coprocessor.v] - Blame information for rev 15