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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Amber 2 Core top-Level module //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// Instantiates the core consisting of fetch, instruction //
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// decode, execute, and co-processor. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2010 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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15 |
csantifort |
module a23_core
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2 |
csantifort |
(
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input i_clk,
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input i_irq, // Interrupt request, active high
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input i_firq, // Fast Interrupt request, active high
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input i_system_rdy, // Amber is stalled when this is low
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// Wishbone Master I/F
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output [31:0] o_wb_adr,
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output [3:0] o_wb_sel,
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output o_wb_we,
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input [31:0] i_wb_dat,
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output [31:0] o_wb_dat,
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output o_wb_cyc,
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output o_wb_stb,
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input i_wb_ack,
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input i_wb_err
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);
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wire [31:0] execute_address;
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wire execute_address_valid;
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wire [31:0] execute_address_nxt; // un-registered version of execute_address to the cache rams
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wire [31:0] write_data;
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wire write_enable;
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wire [31:0] read_data;
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wire priviledged;
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wire exclusive_exec;
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wire data_access_exec;
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wire [3:0] byte_enable;
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wire data_access; // high for data petch, low for instruction fetch
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wire exclusive; // swap access
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wire cache_enable; // Enabel the cache
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wire cache_flush; // Flush the cache
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wire [31:0] cacheable_area;
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wire fetch_stall; // when this is asserted all registers in all 3 pipeline
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// stages are held
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// at their current values
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wire [1:0] status_bits_mode;
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wire status_bits_irq_mask;
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wire status_bits_firq_mask;
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wire status_bits_flags_wen;
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wire status_bits_mode_wen;
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wire status_bits_irq_mask_wen;
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wire status_bits_firq_mask_wen;
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wire [31:0] execute_status_bits;
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wire [31:0] imm32;
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wire [4:0] imm_shift_amount;
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wire shift_imm_zero;
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wire [3:0] condition;
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wire [31:0] read_data_s2;
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wire [4:0] read_data_alignment;
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wire [3:0] rm_sel;
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wire [3:0] rds_sel;
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wire [3:0] rn_sel;
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71 |
csantifort |
wire [3:0] rm_sel_nxt;
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wire [3:0] rds_sel_nxt;
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wire [3:0] rn_sel_nxt;
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2 |
csantifort |
wire [1:0] barrel_shift_amount_sel;
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wire [1:0] barrel_shift_data_sel;
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83 |
csantifort |
wire [1:0] barrel_shift_function;
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wire use_carry_in;
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2 |
csantifort |
wire [8:0] alu_function;
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wire [1:0] multiply_function;
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wire [2:0] interrupt_vector_sel;
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wire [3:0] address_sel;
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wire [1:0] pc_sel;
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wire [1:0] byte_enable_sel;
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wire [2:0] status_bits_sel;
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wire [2:0] reg_write_sel;
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wire user_mode_regs_load;
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wire user_mode_regs_store_nxt;
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wire firq_not_user_mode;
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wire write_data_wen;
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wire copro_write_data_wen;
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wire base_address_wen;
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wire pc_wen;
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wire [14:0] reg_bank_wen;
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csantifort |
wire [3:0] reg_bank_wsel;
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2 |
csantifort |
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wire [2:0] copro_opcode1;
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wire [2:0] copro_opcode2;
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wire [3:0] copro_crn;
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wire [3:0] copro_crm;
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wire [3:0] copro_num;
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wire [1:0] copro_operation;
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wire [31:0] copro_read_data;
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wire [31:0] copro_write_data;
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wire multiply_done;
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wire decode_fault;
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wire iabt_trigger;
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wire dabt_trigger;
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wire [7:0] decode_fault_status;
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wire [7:0] iabt_fault_status;
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wire [7:0] dabt_fault_status;
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wire [31:0] decode_fault_address;
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wire [31:0] iabt_fault_address;
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wire [31:0] dabt_fault_address;
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wire adex;
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// data abort has priority
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assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
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assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
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assign decode_fault = dabt_trigger | iabt_trigger;
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15 |
csantifort |
a23_fetch u_fetch (
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2 |
csantifort |
.i_clk ( i_clk ),
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.i_address ( {execute_address[31:2], 2'd0} ),
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.i_address_valid ( execute_address_valid ),
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.i_address_nxt ( execute_address_nxt ),
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.i_write_data ( write_data ),
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.i_write_enable ( write_enable ),
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.o_read_data ( read_data ),
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.i_priviledged ( priviledged ),
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.i_byte_enable ( byte_enable ),
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.i_data_access ( data_access ),
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.i_exclusive ( exclusive ),
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.i_cache_enable ( cache_enable ),
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.i_cache_flush ( cache_flush ),
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.i_cacheable_area ( cacheable_area ),
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.i_system_rdy ( i_system_rdy ),
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.o_fetch_stall ( fetch_stall ),
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.o_wb_adr ( o_wb_adr ),
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.o_wb_sel ( o_wb_sel ),
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.o_wb_we ( o_wb_we ),
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.i_wb_dat ( i_wb_dat ),
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.o_wb_dat ( o_wb_dat ),
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.o_wb_cyc ( o_wb_cyc ),
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.o_wb_stb ( o_wb_stb ),
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.i_wb_ack ( i_wb_ack ),
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.i_wb_err ( i_wb_err )
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);
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15 |
csantifort |
a23_decode u_decode (
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2 |
csantifort |
.i_clk ( i_clk ),
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// Instruction fetch or data read signals
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.i_read_data ( read_data ),
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.i_execute_address ( execute_address ),
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.i_adex ( adex ),
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.i_iabt ( 1'd0 ),
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.i_dabt ( 1'd0 ),
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.i_abt_status ( 8'd0 ),
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.o_read_data ( read_data_s2 ),
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.o_read_data_alignment ( read_data_alignment ),
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.i_irq ( i_irq ),
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.i_firq ( i_firq ),
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.i_fetch_stall ( fetch_stall ),
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.i_execute_status_bits ( execute_status_bits ),
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.i_multiply_done ( multiply_done ),
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71 |
csantifort |
.o_status_bits_mode ( status_bits_mode ),
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2 |
csantifort |
.o_status_bits_irq_mask ( status_bits_irq_mask ),
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.o_status_bits_firq_mask ( status_bits_firq_mask ),
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.o_imm32 ( imm32 ),
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.o_imm_shift_amount ( imm_shift_amount ),
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.o_shift_imm_zero ( shift_imm_zero ),
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.o_condition ( condition ),
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.o_exclusive_exec ( exclusive_exec ),
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.o_data_access_exec ( data_access_exec ),
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.o_rm_sel ( rm_sel ),
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.o_rds_sel ( rds_sel ),
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.o_rn_sel ( rn_sel ),
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71 |
csantifort |
.o_rm_sel_nxt ( rm_sel_nxt ),
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.o_rds_sel_nxt ( rds_sel_nxt ),
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.o_rn_sel_nxt ( rn_sel_nxt ),
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2 |
csantifort |
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
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.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
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.o_barrel_shift_function ( barrel_shift_function ),
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83 |
csantifort |
.o_use_carry_in ( use_carry_in ),
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2 |
csantifort |
.o_alu_function ( alu_function ),
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.o_multiply_function ( multiply_function ),
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.o_interrupt_vector_sel ( interrupt_vector_sel ),
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.o_address_sel ( address_sel ),
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.o_pc_sel ( pc_sel ),
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.o_byte_enable_sel ( byte_enable_sel ),
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.o_status_bits_sel ( status_bits_sel ),
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.o_reg_write_sel ( reg_write_sel ),
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.o_user_mode_regs_load ( user_mode_regs_load ),
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.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.o_firq_not_user_mode ( firq_not_user_mode ),
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.o_write_data_wen ( write_data_wen ),
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.o_base_address_wen ( base_address_wen ),
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.o_pc_wen ( pc_wen ),
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.o_reg_bank_wen ( reg_bank_wen ),
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71 |
csantifort |
.o_reg_bank_wsel ( reg_bank_wsel ),
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2 |
csantifort |
.o_status_bits_flags_wen ( status_bits_flags_wen ),
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.o_status_bits_mode_wen ( status_bits_mode_wen ),
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.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
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.o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
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.o_copro_opcode1 ( copro_opcode1 ),
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.o_copro_opcode2 ( copro_opcode2 ),
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.o_copro_crn ( copro_crn ),
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.o_copro_crm ( copro_crm ),
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.o_copro_num ( copro_num ),
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.o_copro_operation ( copro_operation ),
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.o_copro_write_data_wen ( copro_write_data_wen ),
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.o_iabt_trigger ( iabt_trigger ),
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.o_iabt_address ( iabt_fault_address ),
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.o_iabt_status ( iabt_fault_status ),
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.o_dabt_trigger ( dabt_trigger ),
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.o_dabt_address ( dabt_fault_address ),
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.o_dabt_status ( dabt_fault_status )
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);
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15 |
csantifort |
a23_execute u_execute (
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| 270 |
2 |
csantifort |
.i_clk ( i_clk ),
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.i_read_data ( read_data_s2 ),
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.i_read_data_alignment ( read_data_alignment ),
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.i_copro_read_data ( copro_read_data ),
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.o_write_data ( write_data ),
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.o_copro_write_data ( copro_write_data ),
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.o_address ( execute_address ),
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.o_address_valid ( execute_address_valid ),
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.o_address_nxt ( execute_address_nxt ),
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.o_adex ( adex ),
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| 283 |
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.o_byte_enable ( byte_enable ),
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.o_data_access ( data_access ),
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.o_write_enable ( write_enable ),
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| 286 |
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.o_exclusive ( exclusive ),
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.o_priviledged ( priviledged ),
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.o_status_bits ( execute_status_bits ),
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.o_multiply_done ( multiply_done ),
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.i_fetch_stall ( fetch_stall ),
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.i_status_bits_mode ( status_bits_mode ),
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.i_status_bits_irq_mask ( status_bits_irq_mask ),
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| 294 |
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.i_status_bits_firq_mask ( status_bits_firq_mask ),
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| 295 |
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.i_imm32 ( imm32 ),
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| 296 |
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.i_imm_shift_amount ( imm_shift_amount ),
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| 297 |
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.i_shift_imm_zero ( shift_imm_zero ),
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| 298 |
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.i_condition ( condition ),
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| 299 |
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.i_exclusive_exec ( exclusive_exec ),
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.i_data_access_exec ( data_access_exec ),
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.i_rm_sel ( rm_sel ),
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.i_rds_sel ( rds_sel ),
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.i_rn_sel ( rn_sel ),
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71 |
csantifort |
.i_rm_sel_nxt ( rm_sel_nxt ),
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.i_rds_sel_nxt ( rds_sel_nxt ),
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| 306 |
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.i_rn_sel_nxt ( rn_sel_nxt ),
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| 307 |
2 |
csantifort |
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
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| 308 |
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.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
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| 309 |
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.i_barrel_shift_function ( barrel_shift_function ),
|
| 310 |
83 |
csantifort |
.i_use_carry_in ( use_carry_in ),
|
| 311 |
2 |
csantifort |
.i_alu_function ( alu_function ),
|
| 312 |
|
|
.i_multiply_function ( multiply_function ),
|
| 313 |
|
|
.i_interrupt_vector_sel ( interrupt_vector_sel ),
|
| 314 |
|
|
.i_address_sel ( address_sel ),
|
| 315 |
|
|
.i_pc_sel ( pc_sel ),
|
| 316 |
|
|
.i_byte_enable_sel ( byte_enable_sel ),
|
| 317 |
|
|
.i_status_bits_sel ( status_bits_sel ),
|
| 318 |
|
|
.i_reg_write_sel ( reg_write_sel ),
|
| 319 |
|
|
.i_user_mode_regs_load ( user_mode_regs_load ),
|
| 320 |
|
|
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
|
| 321 |
|
|
.i_firq_not_user_mode ( firq_not_user_mode ),
|
| 322 |
|
|
.i_write_data_wen ( write_data_wen ),
|
| 323 |
|
|
.i_base_address_wen ( base_address_wen ),
|
| 324 |
|
|
.i_pc_wen ( pc_wen ),
|
| 325 |
|
|
.i_reg_bank_wen ( reg_bank_wen ),
|
| 326 |
71 |
csantifort |
.i_reg_bank_wsel ( reg_bank_wsel ),
|
| 327 |
2 |
csantifort |
.i_status_bits_flags_wen ( status_bits_flags_wen ),
|
| 328 |
|
|
.i_status_bits_mode_wen ( status_bits_mode_wen ),
|
| 329 |
|
|
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
|
| 330 |
|
|
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
|
| 331 |
|
|
.i_copro_write_data_wen ( copro_write_data_wen )
|
| 332 |
|
|
);
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
15 |
csantifort |
a23_coprocessor u_coprocessor (
|
| 336 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 337 |
|
|
|
| 338 |
|
|
.i_fetch_stall ( fetch_stall ),
|
| 339 |
|
|
.i_copro_opcode1 ( copro_opcode1 ),
|
| 340 |
|
|
.i_copro_opcode2 ( copro_opcode2 ),
|
| 341 |
|
|
.i_copro_crn ( copro_crn ),
|
| 342 |
|
|
.i_copro_crm ( copro_crm ),
|
| 343 |
|
|
.i_copro_num ( copro_num ),
|
| 344 |
|
|
.i_copro_operation ( copro_operation ),
|
| 345 |
|
|
.i_copro_write_data ( copro_write_data ),
|
| 346 |
|
|
|
| 347 |
|
|
.i_fault ( decode_fault ),
|
| 348 |
|
|
.i_fault_status ( decode_fault_status ),
|
| 349 |
|
|
.i_fault_address ( decode_fault_address ),
|
| 350 |
|
|
|
| 351 |
|
|
.o_copro_read_data ( copro_read_data ),
|
| 352 |
|
|
.o_cache_enable ( cache_enable ),
|
| 353 |
|
|
.o_cache_flush ( cache_flush ),
|
| 354 |
|
|
.o_cacheable_area ( cacheable_area )
|
| 355 |
|
|
);
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
endmodule
|
| 359 |
|
|
|
