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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] [a23_execute.v] - Blame information for rev 15

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Execute stage of Amber 2 Core                               //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Executes instructions. Instantiates the register file, ALU  //
10
//  multiplication unit and barrel shifter. This stage is       //
11
//  relitively simple. All the complex stuff is done in the     //
12
//  decode stage.                                               //
13
//                                                              //
14
//  Author(s):                                                  //
15
//      - Conor Santifort, csantifort.amber@gmail.com           //
16
//                                                              //
17
//////////////////////////////////////////////////////////////////
18
//                                                              //
19
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
20
//                                                              //
21
// This source file may be used and distributed without         //
22
// restriction provided that this copyright statement is not    //
23
// removed from the file and that any derivative work contains  //
24
// the original copyright notice and the associated disclaimer. //
25
//                                                              //
26
// This source file is free software; you can redistribute it   //
27
// and/or modify it under the terms of the GNU Lesser General   //
28
// Public License as published by the Free Software Foundation; //
29
// either version 2.1 of the License, or (at your option) any   //
30
// later version.                                               //
31
//                                                              //
32
// This source is distributed in the hope that it will be       //
33
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
34
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
35
// PURPOSE.  See the GNU Lesser General Public License for more //
36
// details.                                                     //
37
//                                                              //
38
// You should have received a copy of the GNU Lesser General    //
39
// Public License along with this source; if not, download it   //
40
// from http://www.opencores.org/lgpl.shtml                     //
41
//                                                              //
42
//////////////////////////////////////////////////////////////////
43
 
44
 
45 15 csantifort
module a23_execute (
46 2 csantifort
 
47
input                       i_clk,
48
input       [31:0]          i_read_data,
49
input       [4:0]           i_read_data_alignment,  // 2 LSBs of address in [4:3], appended 
50
                                                    // with 3 zeros
51
input       [31:0]          i_copro_read_data,      // From Co-Processor, to either Register 
52
                                                    // or Memory
53
input                       i_data_access_exec,     // from Instruction Decode stage
54
                                                    // high means the memory access is a read 
55
                                                    // read or write, low for instruction
56
 
57
output reg  [31:0]          o_copro_write_data = 'd0,
58
output reg  [31:0]          o_write_data = 'd0,
59
output reg  [31:0]          o_address = 32'hdead_dead,
60
output reg                  o_adex = 'd0,           // Address Exception
61
output reg                  o_address_valid = 'd0,  // Prevents the reset address value being a 
62
                                                    // wishbone access
63
output      [31:0]          o_address_nxt,          // un-registered version of address to the 
64
                                                    // cache rams address ports
65
output reg                  o_priviledged = 'd0,    // Priviledged access
66
output reg                  o_exclusive = 'd0,      // swap access
67
output reg                  o_write_enable = 'd0,
68
output reg  [3:0]           o_byte_enable = 'd0,
69
output reg                  o_data_access = 'd0,    // To Fetch stage. high = data fetch, 
70
                                                    // low = instruction fetch
71
output      [31:0]          o_status_bits,          // Full PC will all status bits, but PC part zero'ed out
72
output                      o_multiply_done,
73
 
74
 
75
// --------------------------------------------------
76
// Control signals from Instruction Decode stage
77
// --------------------------------------------------
78
input                       i_fetch_stall,          // stall all stages of the cpu at the same time
79
input      [1:0]            i_status_bits_mode,
80
input                       i_status_bits_irq_mask,
81
input                       i_status_bits_firq_mask,
82
input      [31:0]           i_imm32,
83
input      [4:0]            i_imm_shift_amount,
84
input                       i_shift_imm_zero,
85
input      [3:0]            i_condition,
86
input                       i_exclusive_exec,       // swap access
87
 
88
input      [3:0]            i_rm_sel,
89
input      [3:0]            i_rds_sel,
90
input      [3:0]            i_rn_sel,
91
input      [1:0]            i_barrel_shift_amount_sel,
92
input      [1:0]            i_barrel_shift_data_sel,
93
input      [1:0]            i_barrel_shift_function,
94
input      [8:0]            i_alu_function,
95
input      [1:0]            i_multiply_function,
96
input      [2:0]            i_interrupt_vector_sel,
97
input      [3:0]            i_address_sel,
98
input      [1:0]            i_pc_sel,
99
input      [1:0]            i_byte_enable_sel,
100
input      [2:0]            i_status_bits_sel,
101
input      [2:0]            i_reg_write_sel,
102
input                       i_user_mode_regs_load,
103
input                       i_user_mode_regs_store_nxt,
104
input                       i_firq_not_user_mode,
105
 
106
input                       i_write_data_wen,
107
input                       i_base_address_wen,     // save LDM base address register, 
108
                                                    // in case of data abort
109
input                       i_pc_wen,
110
input      [14:0]           i_reg_bank_wen,
111
input                       i_status_bits_flags_wen,
112
input                       i_status_bits_mode_wen,
113
input                       i_status_bits_irq_mask_wen,
114
input                       i_status_bits_firq_mask_wen,
115
input                       i_copro_write_data_wen
116
 
117
);
118
 
119 15 csantifort
`include "a23_localparams.v"
120
`include "a23_functions.v"
121 2 csantifort
 
122
// ========================================================
123
// Internal signals
124
// ========================================================
125
wire [31:0]         write_data_nxt;
126
wire [3:0]          byte_enable_nxt;
127
wire [31:0]         pc_plus4;
128
wire [31:0]         pc_minus4;
129
wire [31:0]         address_plus4;
130
wire [31:0]         alu_plus4;
131
wire [31:0]         rn_plus4;
132
wire [31:0]         alu_out;
133
wire [3:0]          alu_flags;
134
wire [31:0]         rm;
135
wire [31:0]         rs;
136
wire [31:0]         rd;
137
wire [31:0]         rn;
138
wire [31:0]         pc;
139
wire [31:0]         pc_nxt;
140
wire                write_enable_nxt;
141
wire [31:0]         interrupt_vector;
142
wire [7:0]          shift_amount;
143
wire [31:0]         barrel_shift_in;
144
wire [31:0]         barrel_shift_out;
145
wire                barrel_shift_carry;
146
 
147
wire [3:0]          status_bits_flags_nxt;
148
reg  [3:0]          status_bits_flags = 'd0;
149
wire [1:0]          status_bits_mode_nxt;
150
reg  [1:0]          status_bits_mode = SVC;
151
                    // one-hot encoded rs select
152
wire [3:0]          status_bits_mode_rds_oh_nxt;
153
reg  [3:0]          status_bits_mode_rds_oh = 1'd1 << OH_SVC;
154
wire                status_bits_mode_rds_oh_update;
155
wire                status_bits_irq_mask_nxt;
156
reg                 status_bits_irq_mask = 1'd1;
157
wire                status_bits_firq_mask_nxt;
158
reg                 status_bits_firq_mask = 1'd1;
159
 
160
wire                execute;           // high when condition execution is true
161
wire [31:0]         reg_write_nxt;
162
wire                pc_wen;
163
wire [14:0]         reg_bank_wen;
164
wire [31:0]         multiply_out;
165
wire [1:0]          multiply_flags;
166
reg  [31:0]         base_address = 'd0;    // Saves base address during LDM instruction in 
167
                                           // case of data abort
168
 
169
wire                priviledged_nxt;
170
wire                priviledged_update;
171
wire                address_update;
172
wire                base_address_update;
173
wire                write_data_update;
174
wire                copro_write_data_update;
175
wire                byte_enable_update;
176
wire                data_access_update;
177
wire                write_enable_update;
178
wire                exclusive_update;
179
wire                status_bits_flags_update;
180
wire                status_bits_mode_update;
181
wire                status_bits_irq_mask_update;
182
wire                status_bits_firq_mask_update;
183
 
184
wire [31:0]         alu_out_pc_filtered;
185
wire                adex_nxt;
186
 
187
// ========================================================
188
// Status Bits in PC register
189
// ========================================================
190
assign o_status_bits = {   status_bits_flags,           // 31:28
191
                           status_bits_irq_mask,        // 7
192
                           status_bits_firq_mask,       // 6
193
                           24'd0,
194
                           status_bits_mode };          // 1:0 = mode
195
 
196
 
197
// ========================================================
198
// Status Bits Select
199
// ========================================================
200
assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
201
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :
202
                                   i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28]            :
203
                                   // 4 = update flags after a multiply operation
204
                                                        { multiply_flags, status_bits_flags[1:0] } ;
205
 
206
assign status_bits_mode_nxt      = i_status_bits_sel == 3'd0 ? i_status_bits_mode       :
207
                                   i_status_bits_sel == 3'd1 ? alu_out            [1:0] :
208
                                                               i_copro_read_data  [1:0] ;
209
 
210
 
211
// Used for the Rds output of register_bank - this special version of
212
// status_bits_mode speeds up the critical path from status_bits_mode through the
213
// register_bank, barrel_shifter and alu. It moves a mux needed for the
214
// i_user_mode_regs_store_nxt signal back into the previous stage -
215
// so its really part of the decode stage even though the logic is right here
216
// In addition the signal is one-hot encoded to further speed up the logic
217
 
218
assign status_bits_mode_rds_oh_nxt    = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR                            :
219
                                        status_bits_mode_update    ? oh_status_bits_mode(status_bits_mode_nxt) :
220
                                                                     oh_status_bits_mode(status_bits_mode)     ;
221
 
222
 
223
assign status_bits_irq_mask_nxt  = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask      :
224
                                   i_status_bits_sel == 3'd1 ? alu_out                [27] :
225
                                                               i_copro_read_data      [27] ;
226
 
227
assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask     :
228
                                   i_status_bits_sel == 3'd1 ? alu_out                [26] :
229
                                                               i_copro_read_data      [26] ;
230
 
231
 
232
 
233
// ========================================================
234
// Adders
235
// ========================================================
236
assign pc_plus4      = pc        + 32'd4;
237
assign pc_minus4     = pc        - 32'd4;
238
assign address_plus4 = o_address + 32'd4;
239
assign alu_plus4     = alu_out   + 32'd4;
240
assign rn_plus4      = rn        + 32'd4;
241
 
242
// ========================================================
243
// Barrel Shift Amount Select
244
// ========================================================
245
// An immediate shift value of 0 is translated into 32
246
assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
247
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                       :
248
                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
249
                                                          {3'd0, i_read_data_alignment } ;
250
 
251
// ========================================================
252
// Barrel Shift Data Select
253
// ========================================================
254
assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
255
                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
256
                                                           rm            ;
257
 
258
// ========================================================
259
// Interrupt vector Select
260
// ========================================================
261
 
262
assign interrupt_vector = // Reset vector
263
                          (i_interrupt_vector_sel == 3'd0) ? 32'h00000000 :
264
                          // Data abort interrupt vector                 
265
                          (i_interrupt_vector_sel == 3'd1) ? 32'h00000010 :
266
                          // Fast interrupt vector  
267
                          (i_interrupt_vector_sel == 3'd2) ? 32'h0000001c :
268
                          // Regular interrupt vector
269
                          (i_interrupt_vector_sel == 3'd3) ? 32'h00000018 :
270
                          // Prefetch abort interrupt vector
271
                          (i_interrupt_vector_sel == 3'd5) ? 32'h0000000c :
272
                          // Undefined instruction interrupt vector
273
                          (i_interrupt_vector_sel == 3'd6) ? 32'h00000004 :
274
                          // Software (SWI) interrupt vector
275
                          (i_interrupt_vector_sel == 3'd7) ? 32'h00000008 :
276
                          // Default is the address exception interrupt
277
                                                             32'h00000014 ;
278
 
279
 
280
// ========================================================
281
// Address Select
282
// ========================================================
283
 
284
// If rd is the pc, then seperate the address bits from the status bits for
285
// generating the next address to fetch
286
assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;
287
 
288
// if current instruction does not execute because it does not meet the condition
289
// then address advances to next instruction
290
assign o_address_nxt = (!execute)              ? pc_plus4              :
291
                       (i_address_sel == 4'd0) ? pc_plus4              :
292
                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
293
                       (i_address_sel == 4'd2) ? interrupt_vector      :
294
                       (i_address_sel == 4'd3) ? pc                    :
295
                       (i_address_sel == 4'd4) ? rn                    :
296
                       (i_address_sel == 4'd5) ? address_plus4         :  // MTRANS address incrementer
297
                       (i_address_sel == 4'd6) ? alu_plus4             :  // MTRANS decrement after
298
                                                 rn_plus4              ;  // MTRANS increment before
299
 
300
// Data accesses use 32-bit address space, but instruction
301
// accesses are restricted to 26 bit space
302
assign adex_nxt      = |o_address_nxt[31:26] && !i_data_access_exec;
303
 
304
// ========================================================
305
// Program Counter Select
306
// ========================================================
307
// If current instruction does not execute because it does not meet the condition
308
// then PC advances to next instruction
309
assign pc_nxt = (!execute)       ? pc_plus4              :
310
                i_pc_sel == 2'd0 ? pc_plus4              :
311
                i_pc_sel == 2'd1 ? alu_out               :
312
                                   interrupt_vector      ;
313
 
314
 
315
// ========================================================
316
// Register Write Select
317
// ========================================================
318
wire [31:0] save_int_pc;
319
wire [31:0] save_int_pc_m4;
320
 
321
assign save_int_pc    = { status_bits_flags,
322
                          status_bits_irq_mask,
323
                          status_bits_firq_mask,
324
                          pc[25:2],
325
                          status_bits_mode      };
326
 
327
 
328
assign save_int_pc_m4 = { status_bits_flags,
329
                          status_bits_irq_mask,
330
                          status_bits_firq_mask,
331
                          pc_minus4[25:2],
332
                          status_bits_mode      };
333
 
334
 
335
assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :
336
                       // save pc to lr on an interrupt                    
337
                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
338
                       // to update Rd at the end of Multiplication
339
                       i_reg_write_sel == 3'd2 ? multiply_out          :
340
                       i_reg_write_sel == 3'd3 ? o_status_bits         :
341
                       i_reg_write_sel == 3'd5 ? i_copro_read_data     :  // mrc
342
                       i_reg_write_sel == 3'd6 ? base_address          :
343
                                                 save_int_pc           ;
344
 
345
 
346
// ========================================================
347
// Byte Enable Select
348
// ========================================================
349
assign byte_enable_nxt = i_byte_enable_sel == 2'd0  ? 4'b1111 :  // word write
350
                         i_byte_enable_sel == 2'd2  ?            // halfword write
351
                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 :
352
                                                      4'b1100  ) :
353
 
354
                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :  // byte write
355
                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
356
                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
357
                                                      4'b1000 ;
358
 
359
 
360
// ========================================================
361
// Write Data Select
362
// ========================================================
363
assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
364
                                                    {4{rd[ 7:0]}} ;
365
 
366
 
367
// ========================================================
368
// Conditional Execution
369
// ========================================================
370
assign execute = conditional_execute ( i_condition, status_bits_flags );
371
 
372
// allow the PC to increment to the next instruction when current
373
// instruction does not execute
374
assign pc_wen       = i_pc_wen || !execute;
375
 
376
// only update register bank if current instruction executes
377
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
378
 
379
 
380
// ========================================================
381
// Priviledged output flag
382
// ========================================================
383
// Need to look at status_bits_mode_nxt so switch to priviledged mode
384
// at the same time as assert interrupt vector address
385
assign priviledged_nxt  = ( i_status_bits_mode_wen ? status_bits_mode_nxt : status_bits_mode ) != USR ;
386
 
387
 
388
// ========================================================
389
// Write Enable
390
// ========================================================
391
// This must be de-asserted when execute is fault
392
assign write_enable_nxt = execute && i_write_data_wen;
393
 
394
 
395
// ========================================================
396
// Register Update
397
// ========================================================
398
 
399
assign priviledged_update              = !i_fetch_stall;
400
assign data_access_update              = !i_fetch_stall && execute;
401
assign write_enable_update             = !i_fetch_stall;
402
assign write_data_update               = !i_fetch_stall && execute && i_write_data_wen;
403
assign exclusive_update                = !i_fetch_stall && execute;
404
assign address_update                  = !i_fetch_stall;
405
assign byte_enable_update              = !i_fetch_stall && execute && i_write_data_wen;
406
assign copro_write_data_update         = !i_fetch_stall && execute && i_copro_write_data_wen;
407
 
408
assign base_address_update             = !i_fetch_stall && execute && i_base_address_wen;
409
assign status_bits_flags_update        = !i_fetch_stall && execute && i_status_bits_flags_wen;
410
assign status_bits_mode_update         = !i_fetch_stall && execute && i_status_bits_mode_wen;
411
assign status_bits_mode_rds_oh_update  = !i_fetch_stall;
412
assign status_bits_irq_mask_update     = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
413
assign status_bits_firq_mask_update    = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
414
 
415
 
416
always @( posedge i_clk )
417
    begin
418
    o_priviledged           <= priviledged_update             ? priviledged_nxt              : o_priviledged;
419
    o_exclusive             <= exclusive_update               ? i_exclusive_exec             : o_exclusive;
420
    o_data_access           <= data_access_update             ? i_data_access_exec           : o_data_access;
421
    o_write_enable          <= write_enable_update            ? write_enable_nxt             : o_write_enable;
422
    o_write_data            <= write_data_update              ? write_data_nxt               : o_write_data;
423
    o_address               <= address_update                 ? o_address_nxt                : o_address;
424
    o_adex                  <= address_update                 ? adex_nxt                     : o_adex;
425
    o_address_valid         <= address_update                 ? 1'd1                         : o_address_valid;
426
    o_byte_enable           <= byte_enable_update             ? byte_enable_nxt              : o_byte_enable;
427
    o_copro_write_data      <= copro_write_data_update        ? write_data_nxt               : o_copro_write_data;
428
 
429
    base_address            <= base_address_update            ? rn                           : base_address;
430
 
431
    status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
432
    status_bits_mode        <= status_bits_mode_update        ? status_bits_mode_nxt         : status_bits_mode;
433
    status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt  : status_bits_mode_rds_oh;
434
    status_bits_irq_mask    <= status_bits_irq_mask_update    ? status_bits_irq_mask_nxt     : status_bits_irq_mask;
435
    status_bits_firq_mask   <= status_bits_firq_mask_update   ? status_bits_firq_mask_nxt    : status_bits_firq_mask;
436
    end
437
 
438
 
439
// ========================================================
440
// Instantiate Barrel Shift
441
// ========================================================
442 15 csantifort
a23_barrel_shift u_barrel_shift  (
443 2 csantifort
    .i_in             ( barrel_shift_in           ),
444
    .i_carry_in       ( status_bits_flags[1]      ),
445
    .i_shift_amount   ( shift_amount              ),
446
    .i_shift_imm_zero ( i_shift_imm_zero          ),
447
    .i_function       ( i_barrel_shift_function   ),
448
 
449
    .o_out            ( barrel_shift_out          ),
450
    .o_carry_out      ( barrel_shift_carry        )
451
);
452
 
453
 
454
// ========================================================
455
// Instantiate ALU
456
// ========================================================
457 15 csantifort
a23_alu u_alu (
458 2 csantifort
    .i_a_in                 ( rn                    ),
459
    .i_b_in                 ( barrel_shift_out      ),
460
    .i_barrel_shift_carry   ( barrel_shift_carry    ),
461
    .i_status_bits_carry    ( status_bits_flags[1]  ),
462
    .i_function             ( i_alu_function        ),
463
 
464
    .o_out                  ( alu_out               ),
465
    .o_flags                ( alu_flags             )
466
);
467
 
468
 
469
// ========================================================
470
// Instantiate Booth 64-bit Multiplier-Accumulator
471
// ========================================================
472 15 csantifort
a23_multiply u_multiply (
473 2 csantifort
    .i_clk          ( i_clk                 ),
474
    .i_fetch_stall  ( i_fetch_stall         ),
475
    .i_a_in         ( rs                    ),
476
    .i_b_in         ( rm                    ),
477
    .i_function     ( i_multiply_function   ),
478
    .i_execute      ( execute               ),
479
    .o_out          ( multiply_out          ),
480
    .o_flags        ( multiply_flags        ),  // [1] = N, [0] = Z
481
    .o_done         ( o_multiply_done       )
482
);
483
 
484
 
485
// ========================================================
486
// Instantiate Register Bank
487
// ========================================================
488 15 csantifort
a23_register_bank u_register_bank(
489 2 csantifort
    .i_clk                   ( i_clk                     ),
490
    .i_fetch_stall           ( i_fetch_stall             ),
491
    .i_rm_sel                ( i_rm_sel                  ),
492
    .i_rds_sel               ( i_rds_sel                 ),
493
    .i_rn_sel                ( i_rn_sel                  ),
494
    .i_pc_wen                ( pc_wen                    ),
495
    .i_reg_bank_wen          ( reg_bank_wen              ),
496
    .i_pc                    ( pc_nxt[25:2]              ),
497
    .i_reg                   ( reg_write_nxt             ),
498
    .i_mode_idec             ( i_status_bits_mode        ),
499
    .i_mode_exec             ( status_bits_mode          ),
500
 
501
    .i_status_bits_flags     ( status_bits_flags         ),
502
    .i_status_bits_irq_mask  ( status_bits_irq_mask      ),
503
    .i_status_bits_firq_mask ( status_bits_firq_mask     ),
504
 
505
    // pre-encoded in decode stage to speed up long path
506
    .i_firq_not_user_mode    ( i_firq_not_user_mode      ),
507
 
508
    // use one-hot version for speed, combine with i_user_mode_regs_store
509
    .i_mode_rds_exec         ( status_bits_mode_rds_oh   ),
510
 
511
    .i_user_mode_regs_load   ( i_user_mode_regs_load     ),
512
    .o_rm                    ( rm                        ),
513
    .o_rs                    ( rs                        ),
514
    .o_rd                    ( rd                        ),
515
    .o_rn                    ( rn                        ),
516
    .o_pc                    ( pc                        )
517
);
518
 
519
 
520
// ========================================================
521
// Debug - non-synthesizable code
522
// ========================================================
523
//synopsys translate_off
524
 
525
wire    [(2*8)-1:0]    xCONDITION;
526
wire    [(4*8)-1:0]    xMODE;
527
 
528
assign  xCONDITION           = i_condition == EQ ? "EQ"  :
529
                               i_condition == NE ? "NE"  :
530
                               i_condition == CS ? "CS"  :
531
                               i_condition == CC ? "CC"  :
532
                               i_condition == MI ? "MI"  :
533
                               i_condition == PL ? "PL"  :
534
                               i_condition == VS ? "VS"  :
535
                               i_condition == VC ? "VC"  :
536
                               i_condition == HI ? "HI"  :
537
                               i_condition == LS ? "LS"  :
538
                               i_condition == GE ? "GE"  :
539
                               i_condition == LT ? "LT"  :
540
                               i_condition == GT ? "GT"  :
541
                               i_condition == LE ? "LE"  :
542
                               i_condition == AL ? "AL"  :
543
                                                   "NV " ;
544
 
545
assign  xMODE  =  status_bits_mode == SVC  ? "SVC"  :
546
                  status_bits_mode == IRQ  ? "IRQ"  :
547
                  status_bits_mode == FIRQ ? "FIRQ" :
548
                  status_bits_mode == USR  ? "USR"  :
549
                                             "XXX"  ;
550
 
551
 
552
//synopsys translate_on
553
 
554
endmodule
555
 
556
 

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