| 1 |
2 |
csantifort |
//////////////////////////////////////////////////////////////////
|
| 2 |
|
|
// //
|
| 3 |
|
|
// Fetch - Instantiates the fetch stage sub-modules of //
|
| 4 |
|
|
// the Amber 2 Core //
|
| 5 |
|
|
// //
|
| 6 |
|
|
// This file is part of the Amber project //
|
| 7 |
|
|
// http://www.opencores.org/project,amber //
|
| 8 |
|
|
// //
|
| 9 |
|
|
// Description //
|
| 10 |
|
|
// Instantiates the Cache and Wishbone I/F //
|
| 11 |
|
|
// Also contains a little bit of logic to decode memory //
|
| 12 |
|
|
// accesses to decide if they are cached or not //
|
| 13 |
|
|
// //
|
| 14 |
|
|
// Author(s): //
|
| 15 |
|
|
// - Conor Santifort, csantifort.amber@gmail.com //
|
| 16 |
|
|
// //
|
| 17 |
|
|
//////////////////////////////////////////////////////////////////
|
| 18 |
|
|
// //
|
| 19 |
|
|
// Copyright (C) 2010 Authors and OPENCORES.ORG //
|
| 20 |
|
|
// //
|
| 21 |
|
|
// This source file may be used and distributed without //
|
| 22 |
|
|
// restriction provided that this copyright statement is not //
|
| 23 |
|
|
// removed from the file and that any derivative work contains //
|
| 24 |
|
|
// the original copyright notice and the associated disclaimer. //
|
| 25 |
|
|
// //
|
| 26 |
|
|
// This source file is free software; you can redistribute it //
|
| 27 |
|
|
// and/or modify it under the terms of the GNU Lesser General //
|
| 28 |
|
|
// Public License as published by the Free Software Foundation; //
|
| 29 |
|
|
// either version 2.1 of the License, or (at your option) any //
|
| 30 |
|
|
// later version. //
|
| 31 |
|
|
// //
|
| 32 |
|
|
// This source is distributed in the hope that it will be //
|
| 33 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied //
|
| 34 |
|
|
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
|
| 35 |
|
|
// PURPOSE. See the GNU Lesser General Public License for more //
|
| 36 |
|
|
// details. //
|
| 37 |
|
|
// //
|
| 38 |
|
|
// You should have received a copy of the GNU Lesser General //
|
| 39 |
|
|
// Public License along with this source; if not, download it //
|
| 40 |
|
|
// from http://www.opencores.org/lgpl.shtml //
|
| 41 |
|
|
// //
|
| 42 |
|
|
//////////////////////////////////////////////////////////////////
|
| 43 |
|
|
|
| 44 |
|
|
|
| 45 |
15 |
csantifort |
module a23_fetch
|
| 46 |
2 |
csantifort |
(
|
| 47 |
|
|
input i_clk,
|
| 48 |
|
|
|
| 49 |
|
|
input [31:0] i_address,
|
| 50 |
|
|
input i_address_valid,
|
| 51 |
|
|
input [31:0] i_address_nxt, // un-registered version of address to the cache rams
|
| 52 |
|
|
input [31:0] i_write_data,
|
| 53 |
|
|
input i_write_enable,
|
| 54 |
|
|
output [31:0] o_read_data,
|
| 55 |
|
|
input i_priviledged,
|
| 56 |
|
|
input i_exclusive, // high for read part of swap access
|
| 57 |
|
|
input [3:0] i_byte_enable,
|
| 58 |
|
|
input i_data_access, // high for data petch, low for instruction fetch
|
| 59 |
|
|
input i_cache_enable, // cache enable
|
| 60 |
|
|
input i_cache_flush, // cache flush
|
| 61 |
|
|
input [31:0] i_cacheable_area, // each bit corresponds to 2MB address space
|
| 62 |
|
|
input i_system_rdy,
|
| 63 |
|
|
output o_fetch_stall, // when this is asserted all registers
|
| 64 |
|
|
// in all 3 pipeline stages are held
|
| 65 |
|
|
// at their current values
|
| 66 |
|
|
|
| 67 |
|
|
// Wishbone Master I/F
|
| 68 |
|
|
output [31:0] o_wb_adr,
|
| 69 |
|
|
output [3:0] o_wb_sel,
|
| 70 |
|
|
output o_wb_we,
|
| 71 |
|
|
input [31:0] i_wb_dat,
|
| 72 |
|
|
output [31:0] o_wb_dat,
|
| 73 |
|
|
output o_wb_cyc,
|
| 74 |
|
|
output o_wb_stb,
|
| 75 |
|
|
input i_wb_ack,
|
| 76 |
|
|
input i_wb_err
|
| 77 |
|
|
|
| 78 |
|
|
);
|
| 79 |
|
|
|
| 80 |
82 |
csantifort |
`include "memory_configuration.vh"
|
| 81 |
2 |
csantifort |
|
| 82 |
|
|
wire cache_stall;
|
| 83 |
|
|
wire wb_stall;
|
| 84 |
|
|
wire [31:0] cache_read_data;
|
| 85 |
|
|
wire sel_cache;
|
| 86 |
|
|
wire sel_wb;
|
| 87 |
|
|
wire cache_wb_req;
|
| 88 |
|
|
wire address_cachable;
|
| 89 |
|
|
|
| 90 |
|
|
// ======================================
|
| 91 |
|
|
// Memory Decode
|
| 92 |
|
|
// ======================================
|
| 93 |
|
|
assign address_cachable = in_cachable_mem( i_address ) && i_cacheable_area[i_address[25:21]];
|
| 94 |
|
|
|
| 95 |
|
|
assign sel_cache = address_cachable && i_address_valid && i_cache_enable && !i_exclusive;
|
| 96 |
|
|
|
| 97 |
|
|
// Don't start wishbone transfers when the cache is stalling the core
|
| 98 |
|
|
// The cache stalls the core during its initialization sequence
|
| 99 |
|
|
assign sel_wb = !sel_cache && i_address_valid && !(cache_stall);
|
| 100 |
|
|
|
| 101 |
|
|
// Return read data either from the wishbone bus or the cache
|
| 102 |
|
|
assign o_read_data = sel_cache ? cache_read_data :
|
| 103 |
|
|
sel_wb ? i_wb_dat :
|
| 104 |
|
|
32'hffeeddcc ;
|
| 105 |
|
|
|
| 106 |
|
|
// Stall the instruction decode and execute stages of the core
|
| 107 |
|
|
// when the fetch stage needs more than 1 cycle to return the requested
|
| 108 |
|
|
// read data
|
| 109 |
|
|
assign o_fetch_stall = !i_system_rdy || wb_stall || cache_stall;
|
| 110 |
|
|
|
| 111 |
|
|
|
| 112 |
|
|
// ======================================
|
| 113 |
|
|
// L1 Cache (Unified Instruction and Data)
|
| 114 |
|
|
// ======================================
|
| 115 |
15 |
csantifort |
a23_cache u_cache (
|
| 116 |
2 |
csantifort |
.i_clk ( i_clk ),
|
| 117 |
|
|
|
| 118 |
|
|
.i_select ( sel_cache ),
|
| 119 |
|
|
.i_exclusive ( i_exclusive ),
|
| 120 |
|
|
.i_write_data ( i_write_data ),
|
| 121 |
|
|
.i_write_enable ( i_write_enable ),
|
| 122 |
|
|
.i_address ( i_address ),
|
| 123 |
|
|
.i_address_nxt ( i_address_nxt ),
|
| 124 |
|
|
.i_byte_enable ( i_byte_enable ),
|
| 125 |
|
|
.i_cache_enable ( i_cache_enable ),
|
| 126 |
|
|
.i_cache_flush ( i_cache_flush ),
|
| 127 |
|
|
.o_read_data ( cache_read_data ),
|
| 128 |
|
|
|
| 129 |
|
|
.o_stall ( cache_stall ),
|
| 130 |
|
|
.i_core_stall ( o_fetch_stall ),
|
| 131 |
|
|
.o_wb_req ( cache_wb_req ),
|
| 132 |
|
|
.i_wb_address ( o_wb_adr ),
|
| 133 |
|
|
.i_wb_read_data ( i_wb_dat ),
|
| 134 |
|
|
.i_wb_stall ( o_wb_stb & ~i_wb_ack )
|
| 135 |
|
|
);
|
| 136 |
|
|
|
| 137 |
|
|
|
| 138 |
|
|
|
| 139 |
|
|
// ======================================
|
| 140 |
|
|
// Wishbone Master I/F
|
| 141 |
|
|
// ======================================
|
| 142 |
15 |
csantifort |
a23_wishbone u_wishbone (
|
| 143 |
2 |
csantifort |
// CPU Side
|
| 144 |
|
|
.i_clk ( i_clk ),
|
| 145 |
|
|
|
| 146 |
|
|
// Core Accesses to Wishbone bus
|
| 147 |
|
|
.i_select ( sel_wb ),
|
| 148 |
|
|
.i_write_data ( i_write_data ),
|
| 149 |
|
|
.i_write_enable ( i_write_enable ),
|
| 150 |
|
|
.i_byte_enable ( i_byte_enable ),
|
| 151 |
|
|
.i_data_access ( i_data_access ),
|
| 152 |
|
|
.i_exclusive ( i_exclusive ),
|
| 153 |
|
|
.i_address ( i_address ),
|
| 154 |
|
|
.o_stall ( wb_stall ),
|
| 155 |
|
|
|
| 156 |
|
|
// Cache Accesses to Wishbone bus
|
| 157 |
|
|
// L1 Cache enable - used for hprot
|
| 158 |
|
|
.i_cache_req ( cache_wb_req ),
|
| 159 |
|
|
|
| 160 |
|
|
.o_wb_adr ( o_wb_adr ),
|
| 161 |
|
|
.o_wb_sel ( o_wb_sel ),
|
| 162 |
|
|
.o_wb_we ( o_wb_we ),
|
| 163 |
|
|
.i_wb_dat ( i_wb_dat ),
|
| 164 |
|
|
.o_wb_dat ( o_wb_dat ),
|
| 165 |
|
|
.o_wb_cyc ( o_wb_cyc ),
|
| 166 |
|
|
.o_wb_stb ( o_wb_stb ),
|
| 167 |
|
|
.i_wb_ack ( i_wb_ack ),
|
| 168 |
|
|
.i_wb_err ( i_wb_err )
|
| 169 |
|
|
);
|
| 170 |
|
|
|
| 171 |
|
|
|
| 172 |
|
|
endmodule
|
| 173 |
|
|
|
