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[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_decompile.v] - Blame information for rev 63

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1 16 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3 17 csantifort
//  Decompiler for Amber 25 Core                                //
4 16 csantifort
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Decompiler for debugging core - not synthesizable           //
10
//  Shows instruction in Execute Stage at last clock of         //
11
//  the instruction                                             //
12
//                                                              //
13
//  Author(s):                                                  //
14
//      - Conor Santifort, csantifort.amber@gmail.com           //
15
//                                                              //
16
//////////////////////////////////////////////////////////////////
17
//                                                              //
18
// Copyright (C) 2011 Authors and OPENCORES.ORG                 //
19
//                                                              //
20
// This source file may be used and distributed without         //
21
// restriction provided that this copyright statement is not    //
22
// removed from the file and that any derivative work contains  //
23
// the original copyright notice and the associated disclaimer. //
24
//                                                              //
25
// This source file is free software; you can redistribute it   //
26
// and/or modify it under the terms of the GNU Lesser General   //
27
// Public License as published by the Free Software Foundation; //
28
// either version 2.1 of the License, or (at your option) any   //
29
// later version.                                               //
30
//                                                              //
31
// This source is distributed in the hope that it will be       //
32
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
33
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
34
// PURPOSE.  See the GNU Lesser General Public License for more //
35
// details.                                                     //
36
//                                                              //
37
// You should have received a copy of the GNU Lesser General    //
38
// Public License along with this source; if not, download it   //
39
// from http://www.opencores.org/lgpl.shtml                     //
40
//                                                              //
41
//////////////////////////////////////////////////////////////////
42 63 csantifort
`include "global_defines.v"
43 16 csantifort
`include "a25_config_defines.v"
44
 
45
module a25_decompile
46
(
47
input                       i_clk,
48 35 csantifort
input                       i_core_stall,
49 16 csantifort
input       [31:0]          i_instruction,
50
input                       i_instruction_valid,
51
input                       i_instruction_undefined,
52
input                       i_instruction_execute,
53
input       [2:0]           i_interrupt,            // non-zero value means interrupt triggered
54
input                       i_interrupt_state,
55
input       [31:0]          i_instruction_address,
56
input       [2:0]           i_pc_sel,
57
input                       i_pc_wen
58
 
59
);
60
 
61
`include "a25_localparams.v"
62
 
63
`ifdef A25_DECOMPILE
64
 
65
integer i;
66
 
67
wire    [31:0]         imm32;
68
wire    [7:0]          imm8;
69
wire    [11:0]         offset12;
70
wire    [7:0]          offset8;
71
wire    [3:0]          reg_n, reg_d, reg_m, reg_s;
72
wire    [4:0]          shift_imm;
73
wire    [3:0]          opcode;
74
wire    [3:0]          condition;
75
wire    [3:0]          type;
76
wire                   opcode_compare;
77
wire                   opcode_move;
78
wire                   no_shift;
79
wire                   shift_op_imm;
80
wire    [1:0]          mtrans_type;
81
wire                   s_bit;
82
 
83
reg     [(5*8)-1:0]    xINSTRUCTION_EXECUTE;
84
reg     [(5*8)-1:0]    xINSTRUCTION_EXECUTE_R = "---   ";
85
wire    [(8*8)-1:0]    TYPE_NAME;
86
reg     [3:0]          fchars;
87
reg     [31:0]         execute_address = 'd0;
88
reg     [2:0]          interrupt_d1;
89
reg     [31:0]         execute_instruction = 'd0;
90
reg                    execute_now = 'd0;
91
reg                    execute_valid = 'd0;
92
reg                    execute_undefined = 'd0;
93
 
94
 
95
// ========================================================
96
// Delay instruction to Execute stage
97
// ========================================================
98
always @( posedge i_clk )
99 35 csantifort
    if ( !i_core_stall && i_instruction_valid )
100 16 csantifort
        begin
101
        execute_instruction <= i_instruction;
102
        execute_address     <= i_instruction_address;
103
        execute_undefined   <= i_instruction_undefined;
104
        execute_now         <= 1'd1;
105
        end
106
    else
107
        execute_now         <= 1'd0;
108
 
109
 
110
always @ ( posedge i_clk )
111 35 csantifort
    if ( !i_core_stall )
112 16 csantifort
        execute_valid <= i_instruction_valid;
113
 
114
// ========================================================
115
// Open File
116
// ========================================================
117
integer decompile_file;
118
 
119
initial
120
    #1 decompile_file = $fopen(`A25_DECOMPILE_FILE, "w");
121
 
122
 
123
// ========================================================
124
// Fields within the instruction
125
// ========================================================
126
assign opcode      = execute_instruction[24:21];
127
assign condition   = execute_instruction[31:28];
128
assign s_bit       = execute_instruction[20];
129
assign reg_n       = execute_instruction[19:16];
130
assign reg_d       = execute_instruction[15:12];
131
assign reg_m       = execute_instruction[3:0];
132
assign reg_s       = execute_instruction[11:8];
133
assign shift_imm   = execute_instruction[11:7];
134
assign offset12    = execute_instruction[11:0];
135
assign offset8     = {execute_instruction[11:8], execute_instruction[3:0]};
136
assign imm8        = execute_instruction[7:0];
137
 
138
assign no_shift    = execute_instruction[11:4] == 8'h0;
139
assign mtrans_type = execute_instruction[24:23];
140
 
141
 
142
assign opcode_compare =
143
            opcode == CMP ||
144
            opcode == CMN ||
145
            opcode == TEQ ||
146
            opcode == TST ;
147
 
148
assign opcode_move =
149
            opcode == MOV ||
150
            opcode == MVN ;
151
 
152
assign shift_op_imm = type == REGOP && execute_instruction[25] == 1'd1;
153
 
154
assign imm32 =  execute_instruction[11:8] == 4'h0 ? {            24'h0, imm8[7:0] } :
155
                execute_instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
156
                execute_instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
157
                execute_instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
158
                execute_instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0            } :
159
                execute_instruction[11:8] == 4'h5 ? { 2'h0,  imm8[7:0], 22'h0 }     :
160
                execute_instruction[11:8] == 4'h6 ? { 4'h0,  imm8[7:0], 20'h0 }     :
161
                execute_instruction[11:8] == 4'h7 ? { 6'h0,  imm8[7:0], 18'h0 }     :
162
                execute_instruction[11:8] == 4'h8 ? { 8'h0,  imm8[7:0], 16'h0 }     :
163
                execute_instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 }     :
164
                execute_instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 }     :
165
                execute_instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 }     :
166
                execute_instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0  }     :
167
                execute_instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0  }     :
168
                execute_instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0  }     :
169
                                                    { 22'h0, imm8[7:0], 2'h0  }     ;
170
 
171
 
172
// ========================================================
173
// Instruction decode
174
// ========================================================
175
// the order of these matters
176
assign type =
177
    {execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5'b00010, 2'b00, 8'b00001001 } ? SWAP     :  // Before REGOP
178
    {execute_instruction[27:22], execute_instruction[7:4]                              } == { 6'b000000, 4'b1001           } ? MULT     :  // Before REGOP
179
    {execute_instruction[27:26]                                                        } == { 2'b00                        } ? REGOP    :
180
    {execute_instruction[27:26]                                                        } == { 2'b01                        } ? TRANS    :
181
    {execute_instruction[27:25]                                                        } == { 3'b100                       } ? MTRANS   :
182
    {execute_instruction[27:25]                                                        } == { 3'b101                       } ? BRANCH   :
183
    {execute_instruction[27:25]                                                        } == { 3'b110                       } ? CODTRANS :
184
    {execute_instruction[27:24], execute_instruction[4]                                } == { 4'b1110, 1'b0                } ? COREGOP  :
185
    {execute_instruction[27:24], execute_instruction[4]                                } == { 4'b1110, 1'b1                } ? CORTRANS :
186
                                                                                                                               SWI      ;
187
 
188
 
189
//
190
// Convert some important signals to ASCII
191
// so their values can easily be displayed on a waveform viewer
192
//
193
assign TYPE_NAME    = type == REGOP    ? "REGOP   " :
194
                      type == MULT     ? "MULT    " :
195
                      type == SWAP     ? "SWAP    " :
196
                      type == TRANS    ? "TRANS   " :
197
                      type == MTRANS   ? "MTRANS  " :
198
                      type == BRANCH   ? "BRANCH  " :
199
                      type == CODTRANS ? "CODTRANS" :
200
                      type == COREGOP  ? "COREGOP " :
201
                      type == CORTRANS ? "CORTRANS" :
202
                      type == SWI      ? "SWI     " :
203
                                         "UNKNOWN " ;
204
 
205
 
206
always @*
207
    begin
208
 
209
    if ( !execute_now )
210
        begin
211
        xINSTRUCTION_EXECUTE =  xINSTRUCTION_EXECUTE_R;
212
        end // stalled
213
 
214
    else if ( type == REGOP    && opcode == ADC                                                          ) xINSTRUCTION_EXECUTE = "adc  ";
215
    else if ( type == REGOP    && opcode == ADD                                                          ) xINSTRUCTION_EXECUTE = "add  ";
216
    else if ( type == REGOP    && opcode == AND                                                          ) xINSTRUCTION_EXECUTE = "and  ";
217
    else if ( type == BRANCH   && execute_instruction[24] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "b    ";
218
    else if ( type == REGOP    && opcode == BIC                                                          ) xINSTRUCTION_EXECUTE = "bic  ";
219
    else if ( type == BRANCH   && execute_instruction[24] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "bl   ";
220
    else if ( type == COREGOP                                                                            ) xINSTRUCTION_EXECUTE = "cdp  ";
221
    else if ( type == REGOP    && opcode == CMN                                                          ) xINSTRUCTION_EXECUTE = "cmn  ";
222
    else if ( type == REGOP    && opcode == CMP                                                          ) xINSTRUCTION_EXECUTE = "cmp  ";
223
    else if ( type == REGOP    && opcode == EOR                                                          ) xINSTRUCTION_EXECUTE = "eor  ";
224
    else if ( type == CODTRANS && execute_instruction[20] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "ldc  ";
225
    else if ( type == MTRANS   && execute_instruction[20] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "ldm  ";
226
    else if ( type == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1'b0, 1'b1}   ) xINSTRUCTION_EXECUTE = "ldr  ";
227
    else if ( type == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1'b1, 1'b1}   ) xINSTRUCTION_EXECUTE = "ldrb ";
228
    else if ( type == CORTRANS && execute_instruction[20] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "mcr  ";
229
    else if ( type == MULT     && execute_instruction[21] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "mla  ";
230
    else if ( type == REGOP    && opcode == MOV                                                          ) xINSTRUCTION_EXECUTE = "mov  ";
231
    else if ( type == CORTRANS && execute_instruction[20] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "mrc  ";
232
    else if ( type == MULT     && execute_instruction[21] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "mul  ";
233
    else if ( type == REGOP    && opcode == MVN                                                          ) xINSTRUCTION_EXECUTE = "mvn  ";
234
    else if ( type == REGOP    && opcode == ORR                                                          ) xINSTRUCTION_EXECUTE = "orr  ";
235
    else if ( type == REGOP    && opcode == RSB                                                          ) xINSTRUCTION_EXECUTE = "rsb  ";
236
    else if ( type == REGOP    && opcode == RSC                                                          ) xINSTRUCTION_EXECUTE = "rsc  ";
237
    else if ( type == REGOP    && opcode == SBC                                                          ) xINSTRUCTION_EXECUTE = "sbc  ";
238
    else if ( type == CODTRANS && execute_instruction[20] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "stc  ";
239
    else if ( type == MTRANS   && execute_instruction[20] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "stm  ";
240
    else if ( type == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1'b0, 1'b0}   ) xINSTRUCTION_EXECUTE = "str  ";
241
    else if ( type == TRANS    && {execute_instruction[22],execute_instruction[20]}    == {1'b1, 1'b0}   ) xINSTRUCTION_EXECUTE = "strb ";
242
    else if ( type == REGOP    && opcode == SUB                                                          ) xINSTRUCTION_EXECUTE = "sub  ";
243
    else if ( type == SWI                                                                                ) xINSTRUCTION_EXECUTE = "swi  ";
244
    else if ( type == SWAP     && execute_instruction[22] == 1'b0                                        ) xINSTRUCTION_EXECUTE = "swp  ";
245
    else if ( type == SWAP     && execute_instruction[22] == 1'b1                                        ) xINSTRUCTION_EXECUTE = "swpb ";
246
    else if ( type == REGOP    && opcode == TEQ                                                          ) xINSTRUCTION_EXECUTE = "teq  ";
247
    else if ( type == REGOP    && opcode == TST                                                          ) xINSTRUCTION_EXECUTE = "tst  ";
248
    else                                                                                                   xINSTRUCTION_EXECUTE = "unkow";
249
    end
250
 
251
always @ ( posedge i_clk )
252
    xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
253
 
254 35 csantifort
// =================================================================================
255
// Memory Reads and Writes
256
// =================================================================================
257
 
258
reg [31:0] tmp_address;
259
 
260
 
261 16 csantifort
always @( posedge i_clk )
262 35 csantifort
    begin
263
    // Data Write    
264
    if ( get_1bit_signal(0) && !get_1bit_signal(3) )
265
        begin
266
 
267 58 csantifort
        $fwrite(decompile_file, "%09d              write   addr ", `U_TB.clk_count);
268 35 csantifort
        tmp_address = get_32bit_signal(2);
269
        fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
270
 
271
        $fwrite(decompile_file, ", data %08h, be %h",
272
                get_32bit_signal(3),    // u_cache.i_write_data
273
                get_4bit_signal (0));   // u_cache.i_byte_enable
274
 
275
        $fwrite(decompile_file, "\n");
276
        end
277
 
278
    // Data Read    
279
    if ( get_1bit_signal(4) && !get_1bit_signal(1) )
280
        begin
281 58 csantifort
        $fwrite(decompile_file, "%09d              read    addr ", `U_TB.clk_count);
282 35 csantifort
        tmp_address = get_32bit_signal(5);
283
        fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
284
 
285
        $fwrite(decompile_file, ", data %08h to ", get_32bit_signal(4));
286
        warmreg(get_4bit_signal(1));
287
 
288
        $fwrite(decompile_file, "\n");
289
        end
290
 
291
    // instruction
292 16 csantifort
    if ( execute_now )
293
        begin
294
 
295
            // Interrupts override instructions that are just starting
296
        if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
297
            begin
298 58 csantifort
            $fwrite(decompile_file,"%09d  ", `U_TB.clk_count);
299 16 csantifort
 
300
            // Right justify the address
301
            if      ( execute_address < 32'h10)        $fwrite(decompile_file,"       %01x:  ", {execute_address[ 3:1], 1'd0});
302
            else if ( execute_address < 32'h100)       $fwrite(decompile_file,"      %02x:  ",  {execute_address[ 7:1], 1'd0});
303
            else if ( execute_address < 32'h1000)      $fwrite(decompile_file,"     %03x:  ",   {execute_address[11:1], 1'd0});
304
            else if ( execute_address < 32'h10000)     $fwrite(decompile_file,"    %04x:  ",    {execute_address[15:1], 1'd0});
305
            else if ( execute_address < 32'h100000)    $fwrite(decompile_file,"   %05x:  ",     {execute_address[19:1], 1'd0});
306
            else if ( execute_address < 32'h1000000)   $fwrite(decompile_file,"  %06x:  ",      {execute_address[23:1], 1'd0});
307
            else if ( execute_address < 32'h10000000)  $fwrite(decompile_file," %07x:  ",       {execute_address[27:1], 1'd0});
308
            else                                       $fwrite(decompile_file,"%8x:  ",         {execute_address[31:1], 1'd0});
309
 
310
            // Mark that the instruction is not being executed 
311
            // condition field in execute stage allows instruction to execute ?
312
            if (!i_instruction_execute)
313
                begin
314
                $fwrite(decompile_file,"-");
315
                if ( type == SWI )
316 58 csantifort
                    $display ("Cycle %09d  SWI not taken *************", `U_TB.clk_count);
317 16 csantifort
                end
318
            else
319
                $fwrite(decompile_file," ");
320
 
321
            // ========================================
322
            // print the instruction name
323
            // ========================================
324
            case (numchars( xINSTRUCTION_EXECUTE ))
325
                4'd1: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:32] );
326
                4'd2: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:24] );
327
                4'd3: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:16] );
328
                4'd4: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 8] );
329
            default:  $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 0] );
330
            endcase
331
 
332
            fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
333
 
334
            // Print the Multiple transfer type
335
            if (type   == MTRANS )
336
                begin
337
                w_mtrans_type;
338
                fchars = fchars - 2;
339
                end
340
 
341
            // Print the s bit
342
           if ( ((type == REGOP && !opcode_compare) || type == MULT ) && s_bit == 1'b1 )
343
                begin
344
                $fwrite(decompile_file,"s");
345
                fchars = fchars - 1;
346
                end
347
 
348
            // Print the p bit
349
           if ( type == REGOP && opcode_compare && s_bit == 1'b1 && reg_d == 4'd15 )
350
                begin
351
                $fwrite(decompile_file,"p");
352
                fchars = fchars - 1;
353
                end
354
 
355
            // Print the condition code
356
            if ( condition != AL )
357
                begin
358
                wcond;
359
                fchars = fchars - 2;
360
                end
361
 
362
            // Align spaces after instruction    
363
            case ( fchars )
364
                4'd0: $fwrite(decompile_file,"");
365
                4'd1: $fwrite(decompile_file," ");
366
                4'd2: $fwrite(decompile_file,"  ");
367
                4'd3: $fwrite(decompile_file,"   ");
368
                4'd4: $fwrite(decompile_file,"    ");
369
                4'd5: $fwrite(decompile_file,"     ");
370
                4'd6: $fwrite(decompile_file,"      ");
371
                4'd7: $fwrite(decompile_file,"       ");
372
                4'd8: $fwrite(decompile_file,"        ");
373
            default:  $fwrite(decompile_file,"         ");
374
            endcase
375
 
376
            // ========================================
377
            // print the arguments for the instruction
378
            // ========================================
379
            case ( type )
380
                REGOP:     regop_args;
381
                TRANS:     trans_args;
382
                MTRANS:    mtrans_args;
383
                BRANCH:    branch_args;
384
                MULT:      mult_args;
385
                SWAP:      swap_args;
386
                CODTRANS:  codtrans_args;
387
                COREGOP:   begin
388
                           // `TB_ERROR_MESSAGE
389
                           $write("Coregop not implemented in decompiler yet\n");
390
                           end
391
                CORTRANS:  cortrans_args;
392
                SWI:       $fwrite(decompile_file,"#0x%06h", execute_instruction[23:0]);
393
                default: begin
394
                         `TB_ERROR_MESSAGE
395
                         $write("Unknown Instruction Type ERROR\n");
396
                         end
397
            endcase
398
 
399
            $fwrite( decompile_file,"\n" );
400
            end
401
 
402
        // Undefined Instruction Interrupts    
403
        if ( i_instruction_execute && execute_undefined )
404
            begin
405 58 csantifort
            $fwrite( decompile_file,"%09d              interrupt undefined instruction", `U_TB.clk_count );
406 16 csantifort
            $fwrite( decompile_file,", return addr " );
407
            $fwrite( decompile_file,"%08x\n",  pcf(get_reg_val(5'd21)-4'd4) );
408
            end
409
 
410
        // Software Interrupt  
411
        if ( i_instruction_execute && type == SWI )
412
            begin
413 58 csantifort
            $fwrite( decompile_file,"%09d              interrupt swi", `U_TB.clk_count );
414 16 csantifort
            $fwrite( decompile_file,", return addr " );
415
            $fwrite( decompile_file,"%08x\n",  pcf(get_reg_val(5'd21)-4'd4) );
416
            end
417
        end
418 35 csantifort
    end
419
 
420
 
421 16 csantifort
 
422
always @( posedge i_clk )
423 35 csantifort
    if ( !i_core_stall )
424 16 csantifort
        begin
425
        interrupt_d1 <= i_interrupt;
426
 
427
        // Asynchronous Interrupts    
428
        if ( interrupt_d1 != 3'd0 && i_interrupt_state )
429
            begin
430 58 csantifort
            $fwrite( decompile_file,"%09d              interrupt ", `U_TB.clk_count );
431 16 csantifort
            case ( interrupt_d1 )
432
                3'd1:    $fwrite( decompile_file,"data abort" );
433
                3'd2:    $fwrite( decompile_file,"firq" );
434
                3'd3:    $fwrite( decompile_file,"irq" );
435
                3'd4:    $fwrite( decompile_file,"address exception" );
436
                3'd5:    $fwrite( decompile_file,"instruction abort" );
437
                default: $fwrite( decompile_file,"unknown type" );
438
            endcase
439
            $fwrite( decompile_file,", return addr " );
440
 
441
            case ( interrupt_d1 )
442
                3'd1:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd16)));
443
                3'd2:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd17)));
444
                3'd3:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd18)));
445
                3'd4:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd19)));
446
                3'd5:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd19)));
447
                3'd7:    $fwrite(decompile_file,"%08h\n",  pcf(get_reg_val(5'd20)));
448
                default: ;
449
            endcase
450
            end
451
        end
452
 
453
 
454
// jump
455
// Dont print a jump message for interrupts
456
always @( posedge i_clk )
457
        if (
458
             i_pc_sel != 3'd0 &&
459
             i_pc_wen &&
460 35 csantifort
             !i_core_stall &&
461 16 csantifort
             i_instruction_execute &&
462
             i_interrupt == 3'd0 &&
463
             !execute_undefined &&
464
             type != SWI &&
465
             execute_address != get_32bit_signal(0)  // Don't print jump to same address
466
             )
467
            begin
468 58 csantifort
            $fwrite(decompile_file,"%09d              jump    from ", `U_TB.clk_count);
469 16 csantifort
            fwrite_hex_drop_zeros(decompile_file,  pcf(execute_address));
470
            $fwrite(decompile_file," to ");
471
            fwrite_hex_drop_zeros(decompile_file,  pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
472
            $fwrite(decompile_file,", r0 %08h, ",  get_reg_val ( 5'd0 ));
473
            $fwrite(decompile_file,"r1 %08h\n",    get_reg_val ( 5'd1 ));
474
            end
475
 
476
 
477
// =================================================================================
478
// Tasks
479
// =================================================================================
480
 
481
// Write Condition field
482
task wcond;
483
    begin
484
    case( condition)
485
        4'h0:    $fwrite(decompile_file,"eq");
486
        4'h1:    $fwrite(decompile_file,"ne");
487
        4'h2:    $fwrite(decompile_file,"cs");
488
        4'h3:    $fwrite(decompile_file,"cc");
489
        4'h4:    $fwrite(decompile_file,"mi");
490
        4'h5:    $fwrite(decompile_file,"pl");
491
        4'h6:    $fwrite(decompile_file,"vs");
492
        4'h7:    $fwrite(decompile_file,"vc");
493
        4'h8:    $fwrite(decompile_file,"hi");
494
        4'h9:    $fwrite(decompile_file,"ls");
495
        4'ha:    $fwrite(decompile_file,"ge");
496
        4'hb:    $fwrite(decompile_file,"lt");
497
        4'hc:    $fwrite(decompile_file,"gt");
498
        4'hd:    $fwrite(decompile_file,"le");
499
        4'he:    $fwrite(decompile_file,"  ");  // Always
500
        default: $fwrite(decompile_file,"nv");  // Never
501
    endcase
502
    end
503
endtask
504
 
505
// ldm and stm types
506
task w_mtrans_type;
507
    begin
508
    case( mtrans_type )
509
        4'h0:    $fwrite(decompile_file,"da");
510
        4'h1:    $fwrite(decompile_file,"ia");
511
        4'h2:    $fwrite(decompile_file,"db");
512
        4'h3:    $fwrite(decompile_file,"ib");
513
        default: $fwrite(decompile_file,"xx");
514
    endcase
515
    end
516
endtask
517
 
518
// e.g. mrc     15, 0, r9, cr0, cr0, {0}
519
task cortrans_args;
520
    begin
521
    // Co-Processor Number
522
    $fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
523
    // opcode1
524
    $fwrite(decompile_file,"%1d, ", execute_instruction[23:21]);
525
    // Rd [15:12]
526
    warmreg(reg_d);
527
    // CRn [19:16]
528
    $fwrite(decompile_file,", cr%1d", execute_instruction[19:16]);
529
    // CRm [3:0]
530
    $fwrite(decompile_file,", cr%1d", execute_instruction[3:0]);
531
    // Opcode2 [7:5]
532
    $fwrite(decompile_file,", {%1d}",   execute_instruction[7:5]);
533
    end
534
endtask
535
 
536
 
537
// ldc  15, 0, r9, cr0, cr0, {0}
538
task codtrans_args;
539
    begin
540
    // Co-Processor Number
541
    $fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
542
    // CRd [15:12]
543
    $fwrite(decompile_file,"cr%1d, ", execute_instruction[15:12]);
544
    // Rd [19:16]
545
    warmreg(reg_n);
546
    end
547
endtask
548
 
549
 
550
task branch_args;
551
reg [31:0] shift_amount;
552
    begin
553
    if (execute_instruction[23]) // negative
554
        shift_amount = {~execute_instruction[23:0] + 24'd1, 2'd0};
555
    else
556
        shift_amount = {execute_instruction[23:0], 2'd0};
557
 
558
    if (execute_instruction[23]) // negative
559
        fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) - shift_amount );
560
    else
561
        fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) + shift_amount );
562
    end
563
endtask
564
 
565
 
566
task mult_args;
567
    begin
568
    warmreg(reg_n);  // Rd is in the Rn position for MULT instructions
569
    $fwrite(decompile_file,", ");
570
    warmreg(reg_m);
571
    $fwrite(decompile_file,", ");
572
    warmreg(reg_s);
573
 
574
    if (execute_instruction[21]) // MLA
575
        begin
576
        $fwrite(decompile_file,", ");
577
        warmreg(reg_d);
578
        end
579
    end
580
endtask
581
 
582
 
583
task swap_args;
584
    begin
585
    warmreg(reg_d);
586
    $fwrite(decompile_file,", ");
587
    warmreg(reg_m);
588
    $fwrite(decompile_file,", [");
589
    warmreg(reg_n);
590
    $fwrite(decompile_file,"]");
591
    end
592
endtask
593
 
594
 
595
task regop_args;
596
    begin
597
    if (!opcode_compare)
598
        warmreg(reg_d);
599
 
600
    if (!opcode_move )
601
        begin
602
        if (!opcode_compare)
603
            begin
604
            $fwrite(decompile_file,", ");
605
            if (reg_d < 4'd10 || reg_d > 4'd12)
606
                $fwrite(decompile_file," ");
607
            end
608
        warmreg(reg_n);
609
        $fwrite(decompile_file,", ");
610
        if (reg_n < 4'd10 || reg_n > 4'd12)
611
            $fwrite(decompile_file," ");
612
        end
613
    else
614
        begin
615
        $fwrite(decompile_file,", ");
616
        if (reg_d < 4'd10 || reg_d > 4'd12)
617
            $fwrite(decompile_file," ");
618
        end
619
 
620
    if (shift_op_imm)
621
        begin
622
        if (|imm32[31:15])
623
            $fwrite(decompile_file,"#0x%08h", imm32);
624
        else
625
            $fwrite(decompile_file,"#%1d", imm32);
626
        end
627
    else // Rm
628
        begin
629
        warmreg(reg_m);
630
        if (execute_instruction[4])
631
            // Register Shifts
632
            wshiftreg;
633
        else
634
            // Immediate shifts
635
            wshift;
636
        end
637
    end
638
endtask
639
 
640
 
641
task trans_args;
642
    begin
643
    warmreg(reg_d);   // Destination register
644
 
645
    casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12'd0})
646
           6'b0100?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]" , offset12); end
647
           6'b0110?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]"  , offset12); end
648
           6'b0100?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
649
           6'b0110?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
650
           6'b0101?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]!", offset12); end
651
           6'b0111?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]!" , offset12); end
652
 
653
           6'b0000?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
654
           6'b0010?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
655
           6'b0001?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
656
           6'b0011?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
657
 
658
           6'b0000?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
659
           6'b0010?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
660
           6'b0001?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
661
           6'b0011?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
662
 
663
           6'b11001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -");  warmreg(reg_m); $fwrite(decompile_file,"]");  end
664
           6'b11101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", ");   warmreg(reg_m); $fwrite(decompile_file,"]");  end
665
           6'b11011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -");  warmreg(reg_m); $fwrite(decompile_file,"]!"); end
666
           6'b11111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", ");   warmreg(reg_m); $fwrite(decompile_file,"]!"); end
667
 
668
           6'b10001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m);  end
669
           6'b10101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], ");  warmreg(reg_m);  end
670
           6'b10011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m);  end
671
           6'b10111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], ");  warmreg(reg_m);  end
672
 
673
           6'b11000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -");  warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
674
           6'b11100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", ");   warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
675
           6'b11010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -");  warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
676
           6'b11110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", ");   warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
677
 
678
           6'b10000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
679
           6'b10100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], ");  warmreg(reg_m); wshift; end
680
           6'b10010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
681
           6'b10110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], ");  warmreg(reg_m); wshift; end
682
 
683
    endcase
684
    end
685
endtask
686
 
687
 
688
task mtrans_args;
689
    begin
690
    warmreg(reg_n);
691
    if (execute_instruction[21]) $fwrite(decompile_file,"!");
692
    $fwrite(decompile_file,", {");
693
    for (i=0;i<16;i=i+1)
694
        if (execute_instruction[i])
695
            begin
696
            warmreg(i);
697
            if (more_to_come(execute_instruction[15:0], i))
698
                $fwrite(decompile_file,", ");
699
            end
700
    $fwrite(decompile_file,"}");
701
    // SDM: store the user mode registers, when in priviledged mode     
702
    if (execute_instruction[22:20] == 3'b100)
703
        $fwrite(decompile_file,"^");
704
    end
705
endtask
706
 
707
 
708
task wshift;
709
    begin
710
    // Check that its a valid shift operation. LSL by #0 is the null operator                                    
711
    if (execute_instruction[6:5] != LSL || shift_imm != 5'd0)
712
        begin
713
        case(execute_instruction[6:5])
714
            2'd0: $fwrite(decompile_file,", lsl");
715
            2'd1: $fwrite(decompile_file,", lsr");
716
            2'd2: $fwrite(decompile_file,", asr");
717
            2'd3: if (shift_imm == 5'd0) $fwrite(decompile_file,", rrx"); else $fwrite(decompile_file,", ror");
718
        endcase
719
 
720
       if (execute_instruction[6:5] != 2'd3 || shift_imm != 5'd0)
721
           $fwrite(decompile_file," #%1d", shift_imm);
722
       end
723
    end
724
endtask
725
 
726
 
727
task wshiftreg;
728
    begin
729
    case(execute_instruction[6:5])
730
        2'd0: $fwrite(decompile_file,", lsl ");
731
        2'd1: $fwrite(decompile_file,", lsr ");
732
        2'd2: $fwrite(decompile_file,", asr ");
733
        2'd3: $fwrite(decompile_file,", ror ");
734
    endcase
735
 
736
    warmreg(reg_s);
737
    end
738
endtask
739
 
740
 
741
task warmreg;
742
input [3:0] regnum;
743
    begin
744
    if (regnum < 4'd12)
745
        $fwrite(decompile_file,"r%1d", regnum);
746
    else
747
    case (regnum)
748
        4'd12   : $fwrite(decompile_file,"ip");
749
        4'd13   : $fwrite(decompile_file,"sp");
750
        4'd14   : $fwrite(decompile_file,"lr");
751
        4'd15   : $fwrite(decompile_file,"pc");
752
    endcase
753
    end
754
endtask
755
 
756
 
757
task fwrite_hex_drop_zeros;
758
input [31:0] file;
759
input [31:0] num;
760
    begin
761
    if (num[31:28] != 4'd0)
762
        $fwrite(file, "%x", num);
763
    else if (num[27:24] != 4'd0)
764
        $fwrite(file, "%x", num[27:0]);
765
    else if (num[23:20] != 4'd0)
766
        $fwrite(file, "%x", num[23:0]);
767
    else if (num[19:16] != 4'd0)
768
        $fwrite(file, "%x", num[19:0]);
769
    else if (num[15:12] != 4'd0)
770
        $fwrite(file, "%x", num[15:0]);
771
    else if (num[11:8] != 4'd0)
772
        $fwrite(file, "%x", num[11:0]);
773
    else if (num[7:4] != 4'd0)
774
        $fwrite(file, "%x", num[7:0]);
775
    else
776
        $fwrite(file, "%x", num[3:0]);
777
 
778
    end
779
endtask
780
 
781
 
782
 
783
// =================================================================================
784
// Functions
785
// =================================================================================
786
 
787
// Get current value of register
788
function [31:0] get_reg_val;
789
input [4:0] regnum;
790
begin
791
    case (regnum)
792
        5'd0   : get_reg_val = `U_REGISTER_BANK.r0_out;
793
        5'd1   : get_reg_val = `U_REGISTER_BANK.r1_out;
794
        5'd2   : get_reg_val = `U_REGISTER_BANK.r2_out;
795
        5'd3   : get_reg_val = `U_REGISTER_BANK.r3_out;
796
        5'd4   : get_reg_val = `U_REGISTER_BANK.r4_out;
797
        5'd5   : get_reg_val = `U_REGISTER_BANK.r5_out;
798
        5'd6   : get_reg_val = `U_REGISTER_BANK.r6_out;
799
        5'd7   : get_reg_val = `U_REGISTER_BANK.r7_out;
800
        5'd8   : get_reg_val = `U_REGISTER_BANK.r8_out;
801
        5'd9   : get_reg_val = `U_REGISTER_BANK.r9_out;
802
        5'd10  : get_reg_val = `U_REGISTER_BANK.r10_out;
803
        5'd11  : get_reg_val = `U_REGISTER_BANK.r11_out;
804
        5'd12  : get_reg_val = `U_REGISTER_BANK.r12_out;
805
        5'd13  : get_reg_val = `U_REGISTER_BANK.r13_out;
806
        5'd14  : get_reg_val = `U_REGISTER_BANK.r14_out;
807
        5'd15  : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits 
808
 
809
        5'd16  : get_reg_val = `U_REGISTER_BANK.r14_svc;
810
        5'd17  : get_reg_val = `U_REGISTER_BANK.r14_firq;
811
        5'd18  : get_reg_val = `U_REGISTER_BANK.r14_irq;
812
        5'd19  : get_reg_val = `U_REGISTER_BANK.r14_svc;
813
        5'd20  : get_reg_val = `U_REGISTER_BANK.r14_svc;
814
        5'd21  : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits 
815
    endcase
816
end
817
endfunction
818
 
819
 
820
function [31:0] get_32bit_signal;
821
input [2:0] num;
822
begin
823
    case (num)
824
        3'd0: get_32bit_signal = `U_EXECUTE.pc_nxt;
825
        3'd1: get_32bit_signal = `U_EXECUTE.o_iaddress;
826
        3'd2: get_32bit_signal = `U_EXECUTE.o_daddress;
827
        3'd3: get_32bit_signal = `U_EXECUTE.o_write_data;
828
//         3'd4: get_32bit_signal = `U_EXECUTE.read_data_filtered;
829
        3'd4: get_32bit_signal = `U_EXECUTE.i_wb_read_data;
830
        3'd5: get_32bit_signal = `U_WB.daddress_r;
831
    endcase
832
end
833
endfunction
834
 
835
 
836
function get_1bit_signal;
837
input [2:0] num;
838
begin
839
    case (num)
840
        3'd0: get_1bit_signal = `U_EXECUTE.o_write_enable;
841
        3'd1: get_1bit_signal = `U_AMBER.mem_stall;
842
        3'd2: get_1bit_signal = `U_EXECUTE.o_daddress_valid;
843 35 csantifort
        3'd3: get_1bit_signal = `U_AMBER.core_stall;
844 16 csantifort
        3'd4: get_1bit_signal = `U_WB.mem_read_data_valid_r;
845
    endcase
846
end
847
endfunction
848
 
849
 
850
function [3:0] get_4bit_signal;
851
input [2:0] num;
852
begin
853
    case (num)
854
        3'd0: get_4bit_signal = `U_EXECUTE.o_byte_enable;
855
        3'd1: get_4bit_signal = `U_WB.mem_load_rd_r;
856
    endcase
857
end
858
endfunction
859
 
860
 
861
function [3:0] numchars;
862
input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
863
begin
864
     if (xINSTRUCTION_EXECUTE[31:0] == "    ")
865
    numchars = 4'd1;
866
else if (xINSTRUCTION_EXECUTE[23:0] == "   ")
867
    numchars = 4'd2;
868
else if (xINSTRUCTION_EXECUTE[15:0] == "  ")
869
    numchars = 4'd3;
870
else if (xINSTRUCTION_EXECUTE[7:0]  == " ")
871
    numchars = 4'd4;
872
else
873
    numchars = 4'd5;
874
end
875
endfunction
876
 
877
 
878
function more_to_come;
879
input [15:0] regs;
880
input [31:0] i;
881
begin
882
case (i)
883
    15 : more_to_come = 1'd0;
884
    14 : more_to_come =  regs[15]    ? 1'd1 : 1'd0;
885
    13 : more_to_come = |regs[15:14] ? 1'd1 : 1'd0;
886
    12 : more_to_come = |regs[15:13] ? 1'd1 : 1'd0;
887
    11 : more_to_come = |regs[15:12] ? 1'd1 : 1'd0;
888
    10 : more_to_come = |regs[15:11] ? 1'd1 : 1'd0;
889
     9 : more_to_come = |regs[15:10] ? 1'd1 : 1'd0;
890
     8 : more_to_come = |regs[15: 9] ? 1'd1 : 1'd0;
891
     7 : more_to_come = |regs[15: 8] ? 1'd1 : 1'd0;
892
     6 : more_to_come = |regs[15: 7] ? 1'd1 : 1'd0;
893
     5 : more_to_come = |regs[15: 6] ? 1'd1 : 1'd0;
894
     4 : more_to_come = |regs[15: 5] ? 1'd1 : 1'd0;
895
     3 : more_to_come = |regs[15: 4] ? 1'd1 : 1'd0;
896
     2 : more_to_come = |regs[15: 3] ? 1'd1 : 1'd0;
897
     1 : more_to_come = |regs[15: 2] ? 1'd1 : 1'd0;
898
 
899
endcase
900
end
901
endfunction
902
 
903
`endif
904
 
905
endmodule
906
 

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