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csantifort |
//////////////////////////////////////////////////////////////////
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// //
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// Wishbone master interface port buffer //
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// //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// //
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// Description //
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// This is a sub-module of the Amber wishbone master //
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// interface. The wishbone master interface connects a number //
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// of internal amber ports to the wishbone bus. The ports //
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// are; //
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// instruction cache read accesses //
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// data cache read and write accesses (cached) //
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// data cache read and write accesses (uncached) //
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// //
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// The buffer module buffers a single port. For write //
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// requests, this allows the processor core to continue //
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// executing withont having to wait for the wishbone write //
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// operation to complete. //
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// //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2011 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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module a25_wishbone_buf (
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input i_clk,
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// Core side
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input i_req,
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input i_write,
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input [127:0] i_wdata,
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input [15:0] i_be,
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input [31:0] i_addr,
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output [127:0] o_rdata,
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output o_ready,
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// Wishbone side
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output o_valid,
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input i_accepted,
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output o_write,
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output [127:0] o_wdata,
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output [15:0] o_be,
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output [31:0] o_addr,
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input [127:0] i_rdata,
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input i_rdata_valid
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);
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// ----------------------------------------------------
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// Signals
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// ----------------------------------------------------
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reg wbuf_used_r = 'd0;
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reg [127:0] wbuf_wdata_r;
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reg [31:0] wbuf_addr_r;
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reg [15:0] wbuf_be_r;
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reg wbuf_write_r = 'd0;
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wire in_wreq = i_req && i_write;
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reg busy_reading_r = 'd0;
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// ----------------------------------------------------
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// Access Buffer
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// ----------------------------------------------------
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always @(posedge i_clk)
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csantifort |
if (i_req && !wbuf_used_r)
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csantifort |
begin
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wbuf_used_r <= !i_accepted;
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wbuf_wdata_r <= i_wdata;
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wbuf_addr_r <= i_addr;
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wbuf_be_r <= i_write ? i_be : 16'hffff;
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wbuf_write_r <= i_write;
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end
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else if ( i_req && wbuf_used_r && o_valid && i_accepted)
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begin
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wbuf_used_r <= 1'd1;
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wbuf_wdata_r <= i_wdata;
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wbuf_addr_r <= i_addr;
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wbuf_be_r <= i_write ? i_be : 16'hffff;
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wbuf_write_r <= i_write;
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end
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else if (o_valid && i_accepted && wbuf_write_r)
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wbuf_used_r <= 1'd0;
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else if (i_rdata_valid && !wbuf_write_r)
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wbuf_used_r <= 1'd0;
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// ----------------------------------------------------
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// Output logic
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// ----------------------------------------------------
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assign o_wdata = wbuf_used_r ? wbuf_wdata_r : i_wdata;
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assign o_write = wbuf_used_r ? wbuf_write_r : i_write;
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assign o_addr = wbuf_used_r ? wbuf_addr_r : i_addr;
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assign o_be = wbuf_used_r ? wbuf_be_r : i_write ? i_be : 16'hffff;
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assign o_valid = (wbuf_used_r || i_req) && !busy_reading_r;
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assign o_rdata = i_rdata;
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assign o_ready = in_wreq ? (!wbuf_used_r || i_accepted) : i_rdata_valid;
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always@(posedge i_clk)
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if (o_valid && !o_write && i_accepted)
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busy_reading_r <= 1'd1;
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else if (i_rdata_valid)
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busy_reading_r <= 1'd0;
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endmodule
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