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//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/projects/ethmac/                   ////
7
////                                                              ////
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////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11
////  All additional information is available in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001, 2002 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.51  2005/02/21 11:13:17  igorm
45
// Defer indication fixed.
46
//
47
// Revision 1.50  2004/04/26 15:26:23  igorm
48
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
49
//   previous update of the core.
50
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
51
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
52
//   register. (thanks to Mathias and Torbjorn)
53
// - Multicast reception was fixed. Thanks to Ulrich Gries
54
//
55
// Revision 1.49  2003/11/12 18:24:59  tadejm
56
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
57
//
58
// Revision 1.48  2003/10/17 07:46:16  markom
59
// mbist signals updated according to newest convention
60
//
61
// Revision 1.47  2003/10/06 15:43:45  knguyen
62
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
63
//
64
// Revision 1.46  2003/01/30 13:30:22  tadejm
65
// Defer indication changed.
66
//
67
// Revision 1.45  2003/01/22 13:49:26  tadejm
68
// When control packets were received, they were ignored in some cases.
69
//
70
// Revision 1.44  2003/01/21 12:09:40  mohor
71
// When receiving normal data frame and RxFlow control was switched on, RXB
72
// interrupt was not set.
73
//
74
// Revision 1.43  2002/11/22 01:57:06  mohor
75
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
76
// synchronized.
77
//
78
// Revision 1.42  2002/11/21 00:09:19  mohor
79
// TPauseRq synchronized to tx_clk.
80
//
81
// Revision 1.41  2002/11/19 18:13:49  mohor
82
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
83
//
84
// Revision 1.40  2002/11/19 17:34:25  mohor
85
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
86
// that a frame was received because of the promiscous mode.
87
//
88
// Revision 1.39  2002/11/18 17:31:55  mohor
89
// wb_rst_i is used for MIIM reset.
90
//
91
// Revision 1.38  2002/11/14 18:37:20  mohor
92
// r_Rst signal does not reset any module any more and is removed from the design.
93
//
94
// Revision 1.37  2002/11/13 22:25:36  tadejm
95
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
96
//
97
// Revision 1.36  2002/10/18 17:04:20  tadejm
98
// Changed BIST scan signals.
99
//
100
// Revision 1.35  2002/10/11 13:36:58  mohor
101
// Typo error fixed. (When using Bist)
102
//
103
// Revision 1.34  2002/10/10 16:49:50  mohor
104
// Signals for WISHBONE B3 compliant interface added.
105
//
106
// Revision 1.33  2002/10/10 16:29:30  mohor
107
// BIST added.
108
//
109
// Revision 1.32  2002/09/20 17:12:58  mohor
110
// CsMiss added. When address between 0x800 and 0xfff is accessed within
111
// Ethernet Core, error acknowledge is generated.
112
//
113
// Revision 1.31  2002/09/12 14:50:17  mohor
114
// CarrierSenseLost bug fixed when operating in full duplex mode.
115
//
116
// Revision 1.30  2002/09/10 10:35:23  mohor
117
// Ethernet debug registers removed.
118
//
119
// Revision 1.29  2002/09/09 13:03:13  mohor
120
// Error acknowledge is generated when accessing BDs and RST bit in the
121
// MODER register (r_Rst) is set.
122
//
123
// Revision 1.28  2002/09/04 18:44:10  mohor
124
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
125
// connected.
126
//
127
// Revision 1.27  2002/07/25 18:15:37  mohor
128
// RxAbort changed. Packets received with MRxErr (from PHY) are also
129
// aborted.
130
//
131
// Revision 1.26  2002/07/17 18:51:50  mohor
132
// EXTERNAL_DMA removed. External DMA not supported.
133
//
134
// Revision 1.25  2002/05/03 10:15:50  mohor
135
// Outputs registered. Reset changed for eth_wishbone module.
136
//
137
// Revision 1.24  2002/04/22 14:15:42  mohor
138
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
139
// selected in eth_defines.v
140
//
141
// Revision 1.23  2002/03/25 13:33:53  mohor
142
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
143
// name was incorrect.
144
//
145
// Revision 1.22  2002/02/26 16:59:54  mohor
146
// Small fixes for external/internal DMA missmatches.
147
//
148
// Revision 1.21  2002/02/26 16:21:00  mohor
149
// Interrupts changed in the top file
150
//
151
// Revision 1.20  2002/02/18 10:40:17  mohor
152
// Small fixes.
153
//
154
// Revision 1.19  2002/02/16 14:03:44  mohor
155
// Registered trimmed. Unused registers removed.
156
//
157
// Revision 1.18  2002/02/16 13:06:33  mohor
158
// EXTERNAL_DMA used instead of WISHBONE_DMA.
159
//
160
// Revision 1.17  2002/02/16 07:15:27  mohor
161
// Testbench fixed, code simplified, unused signals removed.
162
//
163
// Revision 1.16  2002/02/15 13:49:39  mohor
164
// RxAbort is connected differently.
165
//
166
// Revision 1.15  2002/02/15 11:38:26  mohor
167
// Changes that were lost when updating from 1.11 to 1.14 fixed.
168
//
169
// Revision 1.14  2002/02/14 20:19:11  billditt
170
// Modified for Address Checking,
171
// addition of eth_addrcheck.v
172
//
173
// Revision 1.13  2002/02/12 17:03:03  mohor
174
// HASH0 and HASH1 registers added. Registers address width was
175
// changed to 8 bits.
176
//
177
// Revision 1.12  2002/02/11 09:18:22  mohor
178
// Tx status is written back to the BD.
179
//
180
// Revision 1.11  2002/02/08 16:21:54  mohor
181
// Rx status is written back to the BD.
182
//
183
// Revision 1.10  2002/02/06 14:10:21  mohor
184
// non-DMA host interface added. Select the right configutation in eth_defines.
185
//
186
// Revision 1.9  2002/01/23 10:28:16  mohor
187
// Link in the header changed.
188
//
189
// Revision 1.8  2001/12/05 15:00:16  mohor
190
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
191
// instead of the number of RX descriptors).
192
//
193
// Revision 1.7  2001/12/05 10:45:59  mohor
194
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
195
//
196
// Revision 1.6  2001/10/19 11:24:29  mohor
197
// Number of addresses (wb_adr_i) minimized.
198
//
199
// Revision 1.5  2001/10/19 08:43:51  mohor
200
// eth_timescale.v changed to timescale.v This is done because of the
201
// simulation of the few cores in a one joined project.
202
//
203
// Revision 1.4  2001/10/18 12:07:11  mohor
204
// Status signals changed, Adress decoding changed, interrupt controller
205
// added.
206
//
207
// Revision 1.3  2001/09/24 15:02:56  mohor
208
// Defines changed (All precede with ETH_). Small changes because some
209
// tools generate warnings when two operands are together. Synchronization
210
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
211
// demands).
212
//
213
// Revision 1.2  2001/08/15 14:03:59  mohor
214
// Signal names changed on the top level for easier pad insertion (ASIC).
215
//
216
// Revision 1.1  2001/08/06 14:44:29  mohor
217
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
218
// Include files fixed to contain no path.
219
// File names and module names changed ta have a eth_ prologue in the name.
220
// File eth_timescale.v is used to define timescale
221
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
222
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
223
// and Mdo_OE. The bidirectional signal must be created on the top level. This
224
// is done due to the ASIC tools.
225
//
226
// Revision 1.2  2001/08/02 09:25:31  mohor
227
// Unconnected signals are now connected.
228
//
229
// Revision 1.1  2001/07/30 21:23:42  mohor
230
// Directory structure changed. Files checked and joind together.
231
//
232
//
233
//
234
// 
235
 
236
 
237
`include "eth_defines.v"
238
`include "timescale.v"
239
 
240
 
241
module eth_top
242
(
243
  // WISHBONE common
244
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
245
 
246
  // WISHBONE slave
247
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
248
 
249
  // WISHBONE master
250
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
251
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
252
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
253
 
254
`ifdef ETH_WISHBONE_B3
255
  m_wb_cti_o, m_wb_bte_o,
256
`endif
257
 
258
  //TX
259
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
260
 
261
  //RX
262
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
263
 
264
  // MIIM
265
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
266
 
267
  int_o
268
 
269
  // Bist
270
`ifdef ETH_BIST
271
  ,
272
  // debug chain signals
273
  mbist_si_i,       // bist scan serial in
274
  mbist_so_o,       // bist scan serial out
275
  mbist_ctrl_i        // bist chain shift control
276
`endif
277
 
278
);
279
 
280
 
281
parameter Tp = 1;
282
 
283
 
284
// WISHBONE common
285
input           wb_clk_i;     // WISHBONE clock
286
input           wb_rst_i;     // WISHBONE reset
287
input   [31:0]  wb_dat_i;     // WISHBONE data input
288
output  [31:0]  wb_dat_o;     // WISHBONE data output
289
output          wb_err_o;     // WISHBONE error output
290
 
291
// WISHBONE slave
292
input   [11:2]  wb_adr_i;     // WISHBONE address input
293
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
294
input           wb_we_i;      // WISHBONE write enable input
295
input           wb_cyc_i;     // WISHBONE cycle input
296
input           wb_stb_i;     // WISHBONE strobe input
297
output          wb_ack_o;     // WISHBONE acknowledge output
298
 
299
// WISHBONE master
300
output  [31:0]  m_wb_adr_o;
301
output   [3:0]  m_wb_sel_o;
302
output          m_wb_we_o;
303
input   [31:0]  m_wb_dat_i;
304
output  [31:0]  m_wb_dat_o;
305
output          m_wb_cyc_o;
306
output          m_wb_stb_o;
307
input           m_wb_ack_i;
308
input           m_wb_err_i;
309
 
310
wire    [29:0]  m_wb_adr_tmp;
311
 
312
`ifdef ETH_WISHBONE_B3
313
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
314
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
315
`endif
316
 
317
// Tx
318
input           mtx_clk_pad_i; // Transmit clock (from PHY)
319
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
320
output          mtxen_pad_o;   // Transmit enable (to PHY)
321
output          mtxerr_pad_o;  // Transmit error (to PHY)
322
 
323
// Rx
324
input           mrx_clk_pad_i; // Receive clock (from PHY)
325
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
326
input           mrxdv_pad_i;   // Receive data valid (from PHY)
327
input           mrxerr_pad_i;  // Receive data error (from PHY)
328
 
329
// Common Tx and Rx
330
input           mcoll_pad_i;   // Collision (from PHY)
331
input           mcrs_pad_i;    // Carrier sense (from PHY)
332
 
333
// MII Management interface
334
input           md_pad_i;      // MII data input (from I/O cell)
335
output          mdc_pad_o;     // MII Management data clock (to PHY)
336
output          md_pad_o;      // MII data output (to I/O cell)
337
output          md_padoe_o;    // MII data output enable (to I/O cell)
338
 
339
output          int_o;         // Interrupt output
340
 
341
// Bist
342
`ifdef ETH_BIST
343
input   mbist_si_i;       // bist scan serial in
344
output  mbist_so_o;       // bist scan serial out
345
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
346
`endif
347
 
348
wire     [7:0]  r_ClkDiv;
349
wire            r_MiiNoPre;
350
wire    [15:0]  r_CtrlData;
351
wire     [4:0]  r_FIAD;
352
wire     [4:0]  r_RGAD;
353
wire            r_WCtrlData;
354
wire            r_RStat;
355
wire            r_ScanStat;
356
wire            NValid_stat;
357
wire            Busy_stat;
358
wire            LinkFail;
359
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
360
wire            WCtrlDataStart;
361
wire            RStatStart;
362
wire            UpdateMIIRX_DATAReg;
363
 
364
wire            TxStartFrm;
365
wire            TxEndFrm;
366
wire            TxUsedData;
367
wire     [7:0]  TxData;
368
wire            TxRetry;
369
wire            TxAbort;
370
wire            TxUnderRun;
371
wire            TxDone;
372
 
373
 
374
reg             WillSendControlFrame_sync1;
375
reg             WillSendControlFrame_sync2;
376
reg             WillSendControlFrame_sync3;
377
reg             RstTxPauseRq;
378
 
379
reg             TxPauseRq_sync1;
380
reg             TxPauseRq_sync2;
381
reg             TxPauseRq_sync3;
382
reg             TPauseRq;
383
 
384
 
385
// Connecting Miim module
386
eth_miim miim1
387
(
388
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
389
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
390
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
391
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
392
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
393
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
394
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
395
);
396
 
397
 
398
 
399
 
400
wire  [3:0] RegCs;          // Connected to registers
401
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
402
wire        r_RecSmall;     // Receive small frames
403
wire        r_LoopBck;      // Loopback
404
wire        r_TxEn;         // Tx Enable
405
wire        r_RxEn;         // Rx Enable
406
 
407
wire        MRxDV_Lb;       // Muxed MII receive data valid
408
wire        MRxErr_Lb;      // Muxed MII Receive Error
409
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
410
wire        Transmitting;   // Indication that TxEthMAC is transmitting
411
wire        r_HugEn;        // Huge packet enable
412
wire        r_DlyCrcEn;     // Delayed CRC enabled
413
wire [15:0] r_MaxFL;        // Maximum frame length
414
 
415
wire [15:0] r_MinFL;        // Minimum frame length
416
wire        ShortFrame;
417
wire        DribbleNibble;  // Extra nibble received
418
wire        ReceivedPacketTooBig; // Received packet is too big
419
wire [47:0] r_MAC;          // MAC address
420
wire        LoadRxStatus;   // Rx status was loaded
421
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
422
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
423
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
424
wire  [6:0] r_IPGT;         // 
425
wire  [6:0] r_IPGR1;        // 
426
wire  [6:0] r_IPGR2;        // 
427
wire  [5:0] r_CollValid;    // 
428
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
429
wire        r_TxPauseRq;    // Transmit PAUSE request
430
 
431
wire  [3:0] r_MaxRet;       //
432
wire        r_NoBckof;      // 
433
wire        r_ExDfrEn;      // 
434
wire        r_TxFlow;       // Tx flow control enable
435
wire        r_IFG;          // Minimum interframe gap for incoming packets
436
 
437
wire        TxB_IRQ;        // Interrupt Tx Buffer
438
wire        TxE_IRQ;        // Interrupt Tx Error
439
wire        RxB_IRQ;        // Interrupt Rx Buffer
440
wire        RxE_IRQ;        // Interrupt Rx Error
441
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
442
 
443
//wire        DWord;
444
wire        ByteSelected;
445
wire        BDAck;
446
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
447
wire  [3:0] BDCs;           // Buffer descriptor CS
448
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
449
                            // but data is not valid.
450
wire        r_Pad;
451
wire        r_CrcEn;
452
wire        r_FullD;
453
wire        r_Pro;
454
wire        r_Bro;
455
wire        r_NoPre;
456
wire        r_RxFlow;
457
wire        r_PassAll;
458
wire        TxCtrlEndFrm;
459
wire        StartTxDone;
460
wire        SetPauseTimer;
461
wire        TxUsedDataIn;
462
wire        TxDoneIn;
463
wire        TxAbortIn;
464
wire        PerPacketPad;
465
wire        PadOut;
466
wire        PerPacketCrcEn;
467
wire        CrcEnOut;
468
wire        TxStartFrmOut;
469
wire        TxEndFrmOut;
470
wire        ReceivedPauseFrm;
471
wire        ControlFrmAddressOK;
472
wire        RxStatusWriteLatched_sync2;
473
wire        LateCollision;
474
wire        DeferIndication;
475
wire        LateCollLatched;
476
wire        DeferLatched;
477
wire        RstDeferLatched;
478
wire        CarrierSenseLost;
479
 
480
wire        temp_wb_ack_o;
481
wire [31:0] temp_wb_dat_o;
482
wire        temp_wb_err_o;
483
 
484
`ifdef ETH_REGISTERED_OUTPUTS
485
  reg         temp_wb_ack_o_reg;
486
  reg [31:0]  temp_wb_dat_o_reg;
487
  reg         temp_wb_err_o_reg;
488
`endif
489
 
490
//assign DWord = &wb_sel_i;
491
assign ByteSelected = |wb_sel_i;
492
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
493
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
494
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
495
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
496
assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
497
assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
498
assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
499
assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
500
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
501
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
502
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
503
 
504
`ifdef ETH_REGISTERED_OUTPUTS
505
  assign wb_ack_o = temp_wb_ack_o_reg;
506
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
507
  assign wb_err_o = temp_wb_err_o_reg;
508
`else
509
  assign wb_ack_o = temp_wb_ack_o;
510
  assign wb_dat_o[31:0] = temp_wb_dat_o;
511
  assign wb_err_o = temp_wb_err_o;
512
`endif
513
 
514
`ifdef ETH_AVALON_BUS
515
  // As Avalon has no corresponding "error" signal, I (erroneously) will
516
  // send an ack to Avalon, even when accessing undefined memory. This
517
  // is a grey area in Avalon vs. Wishbone specs: My understanding
518
  // is that Avalon expects all memory addressable by the addr bus feeding
519
  // a slave to be, at the very minimum, readable.
520
  assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
521
`else // WISHBONE
522
  assign temp_wb_ack_o = (|RegCs) | BDAck;
523
`endif
524
 
525
`ifdef ETH_REGISTERED_OUTPUTS
526
  always @ (posedge wb_clk_i or posedge wb_rst_i)
527
  begin
528
    if(wb_rst_i)
529
      begin
530
        temp_wb_ack_o_reg <=#Tp 1'b0;
531
        temp_wb_dat_o_reg <=#Tp 32'h0;
532
        temp_wb_err_o_reg <=#Tp 1'b0;
533
      end
534
    else
535
      begin
536
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
537
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
538
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
539
      end
540
  end
541
`endif
542
 
543
 
544
// Connecting Ethernet registers
545
eth_registers ethreg1
546
(
547
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
548
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
549
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
550
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
551
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
552
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
553
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
554
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
555
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
556
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
557
  .r_IPGT(r_IPGT),
558
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
559
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
560
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
561
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
562
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
563
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
564
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
565
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
566
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
567
  .r_TxBDNum(r_TxBDNum),                  .int_o(int_o),
568
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
569
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
570
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
571
  .SetPauseTimer(SetPauseTimer)
572
 
573
);
574
 
575
 
576
 
577
wire  [7:0] RxData;
578
wire        RxValid;
579
wire        RxStartFrm;
580
wire        RxEndFrm;
581
wire        RxAbort;
582
 
583
wire        WillTransmit;            // Will transmit (to RxEthMAC)
584
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
585
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
586
wire        WillSendControlFrame;
587
wire        ReceiveEnd;
588
wire        ReceivedPacketGood;
589
wire        ReceivedLengthOK;
590
wire        InvalidSymbol;
591
wire        LatchedCrcError;
592
wire        RxLateCollision;
593
wire  [3:0] RetryCntLatched;
594
wire  [3:0] RetryCnt;
595
wire        StartTxAbort;
596
wire        MaxCollisionOccured;
597
wire        RetryLimit;
598
wire        StatePreamble;
599
wire  [1:0] StateData;
600
 
601
// Connecting MACControl
602
eth_maccontrol maccontrol1
603
(
604
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
605
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
606
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
607
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
608
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
609
  .RxData(RxData),                              .RxValid(RxValid),
610
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
611
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
612
  .TxFlow(r_TxFlow),
613
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
614
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
615
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
616
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
617
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
618
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
619
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
620
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
621
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
622
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
623
  .SetPauseTimer(SetPauseTimer),
624
  .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),                .r_PassAll(r_PassAll)
625
);
626
 
627
 
628
 
629
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
630
wire Collision;               // Synchronized Collision
631
 
632
reg CarrierSense_Tx1;
633
reg CarrierSense_Tx2;
634
reg Collision_Tx1;
635
reg Collision_Tx2;
636
 
637
reg RxEnSync;                 // Synchronized Receive Enable
638
reg WillTransmit_q;
639
reg WillTransmit_q2;
640
 
641
 
642
 
643
// Muxed MII receive data valid
644
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
645
 
646
// Muxed MII Receive Error
647
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
648
 
649
// Muxed MII Receive Data
650
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
651
 
652
 
653
 
654
// Connecting TxEthMAC
655
eth_txethmac txethmac1
656
(
657
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
658
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
659
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
660
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
661
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
662
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
663
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
664
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
665
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
666
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
667
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
668
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
669
  .DeferIndication(DeferIndication),  .StatePreamble(StatePreamble),      .StateData(StateData)
670
);
671
 
672
 
673
 
674
 
675
wire  [15:0]  RxByteCnt;
676
wire          RxByteCntEq0;
677
wire          RxByteCntGreat2;
678
wire          RxByteCntMaxFrame;
679
wire          RxCrcError;
680
wire          RxStateIdle;
681
wire          RxStatePreamble;
682
wire          RxStateSFD;
683
wire   [1:0]  RxStateData;
684
wire          AddressMiss;
685
 
686
 
687
 
688
// Connecting RxEthMAC
689
eth_rxethmac rxethmac1
690
(
691
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
692
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
693
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
694
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
695
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
696
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
697
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
698
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
699
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
700
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
701
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
702
);
703
 
704
 
705
// MII Carrier Sense Synchronization
706
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
707
begin
708
  if(wb_rst_i)
709
    begin
710
      CarrierSense_Tx1 <= #Tp 1'b0;
711
      CarrierSense_Tx2 <= #Tp 1'b0;
712
    end
713
  else
714
    begin
715
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
716
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
717
    end
718
end
719
 
720
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
721
 
722
 
723
// MII Collision Synchronization
724
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
725
begin
726
  if(wb_rst_i)
727
    begin
728
      Collision_Tx1 <= #Tp 1'b0;
729
      Collision_Tx2 <= #Tp 1'b0;
730
    end
731
  else
732
    begin
733
      Collision_Tx1 <= #Tp mcoll_pad_i;
734
      if(ResetCollision)
735
        Collision_Tx2 <= #Tp 1'b0;
736
      else
737
      if(Collision_Tx1)
738
        Collision_Tx2 <= #Tp 1'b1;
739
    end
740
end
741
 
742
 
743
// Synchronized Collision
744
assign Collision = ~r_FullD & Collision_Tx2;
745
 
746
 
747
 
748
// Delayed WillTransmit
749
always @ (posedge mrx_clk_pad_i)
750
begin
751
  WillTransmit_q <= #Tp WillTransmit;
752
  WillTransmit_q2 <= #Tp WillTransmit_q;
753
end
754
 
755
 
756
assign Transmitting = ~r_FullD & WillTransmit_q2;
757
 
758
 
759
 
760
// Synchronized Receive Enable
761
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
762
begin
763
  if(wb_rst_i)
764
    RxEnSync <= #Tp 1'b0;
765
  else
766
  if(~mrxdv_pad_i)
767
    RxEnSync <= #Tp r_RxEn;
768
end
769
 
770
 
771
 
772
// Synchronizing WillSendControlFrame to WB_CLK;
773
always @ (posedge wb_clk_i or posedge wb_rst_i)
774
begin
775
  if(wb_rst_i)
776
    WillSendControlFrame_sync1 <= 1'b0;
777
  else
778
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
779
end
780
 
781
always @ (posedge wb_clk_i or posedge wb_rst_i)
782
begin
783
  if(wb_rst_i)
784
    WillSendControlFrame_sync2 <= 1'b0;
785
  else
786
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
787
end
788
 
789
always @ (posedge wb_clk_i or posedge wb_rst_i)
790
begin
791
  if(wb_rst_i)
792
    WillSendControlFrame_sync3 <= 1'b0;
793
  else
794
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
795
end
796
 
797
always @ (posedge wb_clk_i or posedge wb_rst_i)
798
begin
799
  if(wb_rst_i)
800
    RstTxPauseRq <= 1'b0;
801
  else
802
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
803
end
804
 
805
 
806
 
807
 
808
// TX Pause request Synchronization
809
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
810
begin
811
  if(wb_rst_i)
812
    begin
813
      TxPauseRq_sync1 <= #Tp 1'b0;
814
      TxPauseRq_sync2 <= #Tp 1'b0;
815
      TxPauseRq_sync3 <= #Tp 1'b0;
816
    end
817
  else
818
    begin
819
      TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
820
      TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
821
      TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
822
    end
823
end
824
 
825
 
826
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
827
begin
828
  if(wb_rst_i)
829
    TPauseRq <= #Tp 1'b0;
830
  else
831
    TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
832
end
833
 
834
 
835
wire LatchedMRxErr;
836
reg RxAbort_latch;
837
reg RxAbort_sync1;
838
reg RxAbort_wb;
839
reg RxAbortRst_sync1;
840
reg RxAbortRst;
841
 
842
// Synchronizing RxAbort to the WISHBONE clock
843
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
844
begin
845
  if(wb_rst_i)
846
    RxAbort_latch <= #Tp 1'b0;
847
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
848
    RxAbort_latch <= #Tp 1'b1;
849
  else if(RxAbortRst)
850
    RxAbort_latch <= #Tp 1'b0;
851
end
852
 
853
always @ (posedge wb_clk_i or posedge wb_rst_i)
854
begin
855
  if(wb_rst_i)
856
    begin
857
      RxAbort_sync1 <= #Tp 1'b0;
858
      RxAbort_wb    <= #Tp 1'b0;
859
      RxAbort_wb    <= #Tp 1'b0;
860
    end
861
  else
862
    begin
863
      RxAbort_sync1 <= #Tp RxAbort_latch;
864
      RxAbort_wb    <= #Tp RxAbort_sync1;
865
    end
866
end
867
 
868
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
869
begin
870
  if(wb_rst_i)
871
    begin
872
      RxAbortRst_sync1 <= #Tp 1'b0;
873
      RxAbortRst       <= #Tp 1'b0;
874
    end
875
  else
876
    begin
877
      RxAbortRst_sync1 <= #Tp RxAbort_wb;
878
      RxAbortRst       <= #Tp RxAbortRst_sync1;
879
    end
880
end
881
 
882
 
883
 
884
// Connecting Wishbone module
885
eth_wishbone wishbone
886
(
887
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
888
  .WB_DAT_O(BD_WB_DAT_O),
889
 
890
  // WISHBONE slave
891
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
892
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
893
 
894
  .Reset(wb_rst_i),
895
 
896
  // WISHBONE master
897
  .m_wb_adr_o(m_wb_adr_tmp),          .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
898
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
899
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
900
 
901
`ifdef ETH_WISHBONE_B3
902
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
903
`endif
904
 
905
 
906
    //TX
907
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
908
  .TxUsedData(TxUsedData),            .TxData(TxData),
909
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
910
  .TxDone(TxDone),
911
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
912
 
913
  // Register
914
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
915
  .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
916
 
917
  //RX
918
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
919
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
920
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
921
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
922
 
923
  .RxAbort(RxAbort_wb),               .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
924
 
925
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
926
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
927
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
928
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
929
  .RstDeferLatched(RstDeferLatched),
930
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
931
  .ReceivedPauseFrm(ReceivedPauseFrm)
932
 
933
`ifdef ETH_BIST
934
  ,
935
  .mbist_si_i       (mbist_si_i),
936
  .mbist_so_o       (mbist_so_o),
937
  .mbist_ctrl_i       (mbist_ctrl_i)
938
`endif
939
);
940
 
941
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
942
 
943
// Connecting MacStatus module
944
eth_macstatus macstatus1
945
(
946
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
947
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
948
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
949
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
950
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
951
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
952
  .InvalidSymbol(InvalidSymbol),
953
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
954
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
955
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
956
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
957
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
958
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
959
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
960
  .LateCollLatched(LateCollLatched),  .DeferIndication(DeferIndication),           .DeferLatched(DeferLatched),
961
  .RstDeferLatched(RstDeferLatched),
962
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
963
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
964
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
965
);
966
 
967
 
968
endmodule

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