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[/] [amber/] [trunk/] [hw/] [vlog/] [lib/] [xs6_sram_256x128_byte_en.v] - Blame information for rev 2

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1 2 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Wrapper for Xilinx Spartan-6 RAM Block                      //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  256 words x 128 bits with a write enable per byte           //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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module xs6_sram_256x128_byte_en
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#(
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parameter DATA_WIDTH    = 128,
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parameter ADDRESS_WIDTH = 8
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)
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(
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input                           i_clk,
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input      [DATA_WIDTH-1:0]     i_write_data,
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input                           i_write_enable,
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input      [ADDRESS_WIDTH-1:0]  i_address,
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input      [DATA_WIDTH/8-1:0]   i_byte_enable,
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output     [DATA_WIDTH-1:0]     o_read_data
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);
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genvar      i;
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wire [DATA_WIDTH/8-1:0] byte_write_enable;
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assign byte_write_enable = {DATA_WIDTH/8{i_write_enable}} & i_byte_enable;
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generate
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    for (i=0;i<4;i=i+1) begin : u_gen
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        RAMB8BWER #(
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            .DATA_WIDTH_A        ( 36                        ),
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            .DATA_WIDTH_B        ( 36                        ),
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            .RAM_MODE            ( "SDP"                     ),
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            .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY"         ),
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            .WRITE_MODE_A        ( "READ_FIRST"              ),
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            .WRITE_MODE_B        ( "READ_FIRST"              )
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         )
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        u_ramb8bwer (
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            .CLKAWRCLK      ( i_clk                          ),
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            .CLKBRDCLK      ( i_clk                          ),
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            .ADDRAWRADDR    ( {i_address, 5'd0}              ),
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            .ADDRBRDADDR    ( {i_address, 5'd0}              ),
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            .ENAWREN        ( i_write_enable                 ),
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            .ENBRDEN        ( ~i_write_enable                ),
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            // Port A is lower 2 bytes
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            .WEAWEL         ( byte_write_enable[4*i+1:4*i+0] ),
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            .DIADI          ( i_write_data[32*i+15:32*i+ 0]  ),
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            .DOADO          ( o_read_data [32*i+15:32*i+ 0]  ),
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            // Port B is upper 2 bytes
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            .WEBWEU         ( byte_write_enable[4*i+3:4*i+2] ),
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            .DIBDI          ( i_write_data[32*i+31:32*i+16]  ),
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            .DOBDO          ( o_read_data [32*i+31:32*i+16]  ),
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            // These guys are not used, so they are just tied off
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            // ----------------------------------------------------
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            .DIPBDIP        ( 2'd0                           ),
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            .DIPADIP        ( 2'd0                           ),
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            .DOPADOP        (                                ),
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            .DOPBDOP        (                                ),
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            .REGCEA         ( 1'd0                           ),
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            .REGCEBREGCE    ( 1'd0                           ),
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            .RSTA           ( 1'd0                           ),
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            .RSTBRST        ( 1'd0                           )
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        );
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    end
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endgenerate
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//synopsys translate_off
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initial
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    begin
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    if ( DATA_WIDTH    != 128 ) $display("%M Warning: Incorrect parameter DATA_WIDTH");
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    if ( ADDRESS_WIDTH != 8   ) $display("%M Warning: Incorrect parameter ADDRESS_WIDTH");
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    end
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//synopsys translate_on
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endmodule
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