OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [ddr3_afifo.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Asynchronous FIFO set for Wishbone to Xilinx Virtex-6       //
4
//  DDR3 Bridge                                                 //
5
//                                                              //
6
//  This file is part of the Amber project                      //
7
//  http://www.opencores.org/project,amber                      //
8
//                                                              //
9
//  Description                                                 //
10
//                                                              //
11
//  Author(s):                                                  //
12
//      - Conor Santifort, csantifort.amber@gmail.com           //
13
//                                                              //
14
//////////////////////////////////////////////////////////////////
15
//                                                              //
16
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
17
//                                                              //
18
// This source file may be used and distributed without         //
19
// restriction provided that this copyright statement is not    //
20
// removed from the file and that any derivative work contains  //
21
// the original copyright notice and the associated disclaimer. //
22
//                                                              //
23
// This source file is free software; you can redistribute it   //
24
// and/or modify it under the terms of the GNU Lesser General   //
25
// Public License as published by the Free Software Foundation; //
26
// either version 2.1 of the License, or (at your option) any   //
27
// later version.                                               //
28
//                                                              //
29
// This source is distributed in the hope that it will be       //
30
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
31
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
32
// PURPOSE.  See the GNU Lesser General Public License for more //
33
// details.                                                     //
34
//                                                              //
35
// You should have received a copy of the GNU Lesser General    //
36
// Public License along with this source; if not, download it   //
37
// from http://www.opencores.org/lgpl.shtml                     //
38
//                                                              //
39
//////////////////////////////////////////////////////////////////
40
 
41
 
42
module ddr3_afifo
43
#(
44
parameter ADDR_WIDTH = 30,
45
parameter DATA_WIDTH = 32
46
)
47
(
48
input                          i_sys_clk,
49
input                          i_ddr_clk,
50
 
51
// Write-Side Ports
52
input                          i_cmd_en,               // Command Enable
53
input     [2:0]                i_cmd_instr,            // write = 000, read = 001
54
input     [ADDR_WIDTH-1:0]     i_cmd_byte_addr,        // Memory address
55
output                         o_cmd_full,             // DDR3 I/F Command FIFO is full
56
 
57
output                         o_wr_full,              // DDR3 I/F Write Data FIFO is full
58
input                          i_wr_en,                // Write data enable
59
input     [DATA_WIDTH/8-1:0]   i_wr_mask,              // 1 bit per byte
60
input     [DATA_WIDTH-1:0]     i_wr_data,              // 16 bytes write data
61
input     [1:0]                i_wr_addr_32,           // address bits [3:2]
62
output    [DATA_WIDTH-1:0]     o_rd_data,              // 16 bytes of read data
63
output                         o_rd_valid,             // low when read data is valid
64
 
65
// Read-Side Ports
66
output                         o_ddr_cmd_en,           // Command Enable
67
output     [2:0]               o_ddr_cmd_instr,        // write = 000, read = 001
68
output     [ADDR_WIDTH-1:0]    o_ddr_cmd_byte_addr,    // Memory address
69
input                          i_ddr_cmd_full,         // DDR3 I/F Command FIFO is full
70
 
71
input                          i_ddr_wr_full,          // DDR3 I/F Write Data FIFO is full
72
output                         o_ddr_wr_en,            // Write data enable
73
output     [DATA_WIDTH/8-1:0]  o_ddr_wr_mask,          // 1 bit per byte
74
output     [DATA_WIDTH-1:0]    o_ddr_wr_data,          // 16 bytes write data
75
output     [1:0]               o_ddr_wr_addr_32,       // address bits [3:2]
76
input      [DATA_WIDTH-1:0]    i_ddr_rd_data,          // 16 bytes of read data
77
input                          i_ddr_rd_valid          // low when read data is valid
78
 
79
);
80
 
81
wire cmd_empty, wr_empty, rd_empty;
82
 
83
assign o_ddr_cmd_en = !cmd_empty;
84
assign o_ddr_wr_en  = !wr_empty;
85
assign o_rd_valid   = !rd_empty;
86
 
87
 
88
afifo #(.D_WIDTH(ADDR_WIDTH+3)) u_afifo_cmd (
89
    .wr_clk     ( i_sys_clk                                 ),
90
    .rd_clk     ( i_ddr_clk                                 ),
91
 
92
    .i_data     ( {i_cmd_instr, i_cmd_byte_addr}            ),
93
    .o_data     ( {o_ddr_cmd_instr, o_ddr_cmd_byte_addr}    ),
94
    .i_push     ( i_cmd_en                                  ),
95
    .i_pop      ( o_ddr_cmd_en && !i_ddr_cmd_full           ),
96
 
97
    .o_full     ( o_cmd_full                                ),
98
    .o_empty    ( cmd_empty                                 )
99
);
100
 
101
 
102
afifo #(.D_WIDTH(DATA_WIDTH+DATA_WIDTH/8+2)) u_afifo_wr (
103
    .wr_clk     ( i_sys_clk                                 ),
104
    .rd_clk     ( i_ddr_clk                                 ),
105
 
106
    .i_data     ( {i_wr_addr_32, i_wr_mask, i_wr_data }     ),
107
    .o_data     ( {o_ddr_wr_addr_32, o_ddr_wr_mask, o_ddr_wr_data} ),
108
    .i_push     ( i_wr_en                                   ),
109
    .i_pop      ( o_ddr_wr_en && !i_ddr_wr_full             ),
110
 
111
    .o_full     ( o_wr_full                                 ),
112
    .o_empty    ( wr_empty                                  )
113
);
114
 
115
 
116
afifo #(.D_WIDTH(DATA_WIDTH)) u_afifo_rd (
117
    .wr_clk     ( i_ddr_clk                                 ),
118
    .rd_clk     ( i_sys_clk                                 ),
119
 
120
    .i_data     ( i_ddr_rd_data                             ),
121
    .o_data     ( o_rd_data                                 ),
122
    .i_push     ( i_ddr_rd_valid                            ),
123
    .i_pop      ( o_rd_valid                                ),
124
 
125
    .o_full     (                                           ),
126
    .o_empty    ( rd_empty                                  )
127
);
128
 
129
endmodule
130
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.