OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [main_mem.v] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Main memory for simulations.                                //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  Non-synthesizable main memory. Holds 128MBytes              //
10
//  The memory path in this module is purely combinational.     //
11
//  Addresses and write_cmd_req data are registered as          //
12
//  the leave the execute module and read data is registered    //
13
//  as it enters the instruction_decode module.                 //
14
//                                                              //
15
//  Author(s):                                                  //
16
//      - Conor Santifort, csantifort.amber@gmail.com           //
17
//                                                              //
18
//////////////////////////////////////////////////////////////////
19
//                                                              //
20
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
21
//                                                              //
22
// This source file may be used and distributed without         //
23
// restriction provided that this copyright statement is not    //
24
// removed from the file and that any derivative work contains  //
25
// the original copyright notice and the associated disclaimer. //
26
//                                                              //
27
// This source file is free software; you can redistribute it   //
28
// and/or modify it under the terms of the GNU Lesser General   //
29
// Public License as published by the Free Software Foundation; //
30
// either version 2.1 of the License, or (at your option) any   //
31
// later version.                                               //
32
//                                                              //
33
// This source is distributed in the hope that it will be       //
34
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
35
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
36
// PURPOSE.  See the GNU Lesser General Public License for more //
37
// details.                                                     //
38
//                                                              //
39
// You should have received a copy of the GNU Lesser General    //
40
// Public License along with this source; if not, download it   //
41
// from http://www.opencores.org/lgpl.shtml                     //
42
//                                                              //
43
//////////////////////////////////////////////////////////////////
44
 
45
 
46
module main_mem
47
(
48
input                          i_clk,
49 11 csantifort
input                          i_mem_ctrl,  // 0=128MB, 1=32MB
50 2 csantifort
// Wishbone Bus
51
input       [31:0]             i_wb_adr,
52
input       [3:0]              i_wb_sel,
53
input                          i_wb_we,
54
output reg  [31:0]             o_wb_dat         = 'd0,
55
input       [31:0]             i_wb_dat,
56
input                          i_wb_cyc,
57
input                          i_wb_stb,
58
output                         o_wb_ack,
59
output                         o_wb_err
60
 
61
);
62
 
63
`include "memory_configuration.v"
64
 
65
reg     [127:0]     ram   [2**(MAIN_MSB-2)-1:0];
66
wire                start_write;
67
wire                start_read;
68
reg                 start_read_d1;
69
reg                 start_read_d2;
70
wire    [127:0]     rd_data;
71
wire    [127:0]     masked_wdata;
72
 
73
reg                 wr_en           = 'd0;
74
reg     [15:0]      wr_mask         = 'd0;
75
reg     [127:0]     wr_data         = 'd0;
76
reg     [27:0]      addr_d1         = 'd0;
77
wire                busy;
78
genvar              i;
79
 
80
 
81
assign start_write = i_wb_stb &&  i_wb_we && !busy;
82
assign start_read  = i_wb_stb && !i_wb_we && !busy;
83
assign busy        = start_read_d1 || start_read_d2;
84
 
85
assign o_wb_err    = 'd0;
86
 
87
 
88
// ------------------------------------------------------
89
// Write
90
// ------------------------------------------------------
91
always @( posedge i_clk )
92
    begin
93
    wr_en          <= start_write;
94
    wr_mask        <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel          } :
95
                      i_wb_adr[3:2] == 2'd1 ? { 8'hff,   ~i_wb_sel, 4'hf    } :
96
                      i_wb_adr[3:2] == 2'd2 ? { 4'hf,    ~i_wb_sel, 8'hff   } :
97
                                              {          ~i_wb_sel, 12'hfff } ;
98
    wr_data        <= {4{i_wb_dat}};
99 11 csantifort
 
100
                      // Wrap the address at 32 MB, or full width
101
    addr_d1        <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
102 2 csantifort
 
103
    if ( wr_en )
104
        ram [addr_d1[27:2]]  <= masked_wdata;
105
    end
106
 
107
 
108
generate
109
for (i=0;i<16;i=i+1) begin : masked
110
    assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
111
end
112
endgenerate
113
 
114
 
115
 
116
// ------------------------------------------------------
117
// Read
118
// ------------------------------------------------------
119
assign rd_data = ram [addr_d1[27:2]];
120
 
121
 
122
always @( posedge i_clk )
123
    begin
124
    start_read_d1   <= start_read;
125
    start_read_d2   <= start_read_d1;
126
    if ( start_read_d1 )
127
        begin
128
        o_wb_dat  <= addr_d1[1:0] == 2'd0 ? rd_data[ 31: 0] :
129
                     addr_d1[1:0] == 2'd1 ? rd_data[ 63:32] :
130
                     addr_d1[1:0] == 2'd2 ? rd_data[ 95:64] :
131
                                            rd_data[127:96] ;
132
        end
133
    end
134
 
135
assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
136
 
137
 
138
endmodule
139
 
140
 
141
 
142
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.