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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Top-level module instantiating the entire Amber 2 system.   //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  This is the highest level synthesizable module in the       //
10
//  project. The ports in this module represent pins on the     //
11
//  FPGA.                                                       //
12
//                                                              //
13
//  Author(s):                                                  //
14
//      - Conor Santifort, csantifort.amber@gmail.com           //
15
//                                                              //
16
//////////////////////////////////////////////////////////////////
17
//                                                              //
18
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
19
//                                                              //
20
// This source file may be used and distributed without         //
21
// restriction provided that this copyright statement is not    //
22
// removed from the file and that any derivative work contains  //
23
// the original copyright notice and the associated disclaimer. //
24
//                                                              //
25
// This source file is free software; you can redistribute it   //
26
// and/or modify it under the terms of the GNU Lesser General   //
27
// Public License as published by the Free Software Foundation; //
28
// either version 2.1 of the License, or (at your option) any   //
29
// later version.                                               //
30
//                                                              //
31
// This source is distributed in the hope that it will be       //
32
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
33
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
34
// PURPOSE.  See the GNU Lesser General Public License for more //
35
// details.                                                     //
36
//                                                              //
37
// You should have received a copy of the GNU Lesser General    //
38
// Public License along with this source; if not, download it   //
39
// from http://www.opencores.org/lgpl.shtml                     //
40
//                                                              //
41
//////////////////////////////////////////////////////////////////
42
 
43
 
44
module system
45
(
46
input                       brd_rst,
47
input                       brd_clk_n,
48
input                       brd_clk_p,
49
 
50
`ifdef XILINX_VIRTEX6_FPGA
51
input                       sys_clk_p,
52
input                       sys_clk_n,
53
`endif
54
 
55
// UART 0 Interface
56
input                       i_uart0_rts,
57
output                      o_uart0_rx,
58
output                      o_uart0_cts,
59
input                       i_uart0_tx,
60
 
61
// Xilinx Spartan 6 MCB DDR3 Interface
62
inout  [15:0]               ddr3_dq,
63
output [12:0]               ddr3_addr,
64
output [2:0]                ddr3_ba,
65
output                      ddr3_ras_n,
66
output                      ddr3_cas_n,
67
output                      ddr3_we_n,
68
output                      ddr3_odt,
69
output                      ddr3_reset_n,
70
output                      ddr3_cke,
71
output [1:0]                ddr3_dm,
72
inout  [1:0]                ddr3_dqs_p,
73
inout  [1:0]                ddr3_dqs_n,
74
output                      ddr3_ck_p,
75
output                      ddr3_ck_n,
76
`ifdef XILINX_VIRTEX6_FPGA
77
output                      ddr3_cs_n,
78
`endif
79
`ifdef XILINX_SPARTAN6_FPGA
80
inout                       mcb3_rzq,
81
inout                       mcb3_zio,
82
`endif
83
 
84
 
85
// Ethmac B100 MAC to PHY Interface
86
input                       mtx_clk_pad_i,
87
output  [3:0]               mtxd_pad_o,
88
output                      mtxen_pad_o,
89
output                      mtxerr_pad_o,
90
input                       mrx_clk_pad_i,
91
input   [3:0]               mrxd_pad_i,
92
input                       mrxdv_pad_i,
93
input                       mrxerr_pad_i,
94
input                       mcoll_pad_i,
95
input                       mcrs_pad_i,
96
inout                       md_pad_io,
97
output                      mdc_pad_o,
98
output                      phy_reset_n
99
);
100
 
101
 
102
wire            sys_clk;    // System clock
103
wire            sys_rst;    // Active low reset, synchronous to sys_clk
104
wire            clk_200;    // 200MHz from board
105
 
106
 
107
// ======================================
108
// Xilinx MCB DDR3 Controller connections
109
// ======================================
110
`ifdef XILINX_SPARTAN6_FPGA
111
wire            c3_p0_cmd_en;
112
wire  [2:0]     c3_p0_cmd_instr;
113
wire  [29:0]    c3_p0_cmd_byte_addr;
114
wire            c3_p0_wr_en;
115
wire  [15:0]    c3_p0_wr_mask;
116
wire  [127:0]   c3_p0_wr_data;
117
wire  [127:0]   c3_p0_rd_data;
118
wire            c3_p0_rd_empty;
119
wire            c3_p0_cmd_full;
120
wire            c3_p0_wr_full;
121
`endif
122
 
123
wire            phy_init_done;
124 11 csantifort
wire            test_mem_ctrl;
125 2 csantifort
 
126
// ======================================
127
// Xilinx Virtex-6 DDR3 Controller connections
128
// ======================================
129
`ifdef XILINX_VIRTEX6_FPGA
130
wire            phy_init_done1;
131
wire            xv6_cmd_en;
132
wire  [2:0]     xv6_cmd_instr;
133
wire  [26:0]    xv6_cmd_byte_addr;
134
wire            xv6_cmd_full;
135
wire            xv6_wr_full;
136
wire            xv6_wr_en;
137
wire            xv6_wr_end;
138
wire  [7:0]     xv6_wr_mask;
139
wire  [63:0]    xv6_wr_data;
140
wire  [63:0]    xv6_rd_data;
141
wire            xv6_rd_data_valid;
142
wire            xv6_ddr3_clk;
143
`endif
144
 
145
// ======================================
146
// Ethmac MII
147
// ======================================
148
wire            md_pad_i;
149
wire            md_pad_o;
150
wire            md_padoe_o;
151
 
152
// ======================================
153
// Wishbone Buses
154
// ======================================
155
 
156
localparam WB_MASTERS = 2;
157
localparam WB_SLAVES  = 9;
158
 
159
 
160
// Wishbone Master Buses
161
wire      [31:0]            m_wb_adr      [WB_MASTERS-1:0];
162
wire      [3:0]             m_wb_sel      [WB_MASTERS-1:0];
163
wire      [WB_MASTERS-1:0]  m_wb_we                       ;
164
wire      [31:0]            m_wb_dat_w    [WB_MASTERS-1:0];
165
wire      [31:0]            m_wb_dat_r    [WB_MASTERS-1:0];
166
wire      [WB_MASTERS-1:0]  m_wb_cyc                      ;
167
wire      [WB_MASTERS-1:0]  m_wb_stb                      ;
168
wire      [WB_MASTERS-1:0]  m_wb_ack                      ;
169
wire      [WB_MASTERS-1:0]  m_wb_err                      ;
170
 
171
 
172
// Wishbone Slave Buses
173
wire      [31:0]            s_wb_adr      [WB_SLAVES-1:0];
174
wire      [3:0]             s_wb_sel      [WB_SLAVES-1:0];
175
wire      [WB_SLAVES-1:0]   s_wb_we                      ;
176
wire      [31:0]            s_wb_dat_w    [WB_SLAVES-1:0];
177
wire      [31:0]            s_wb_dat_r    [WB_SLAVES-1:0];
178
wire      [WB_SLAVES-1:0]   s_wb_cyc                     ;
179
wire      [WB_SLAVES-1:0]   s_wb_stb                     ;
180
wire      [WB_SLAVES-1:0]   s_wb_ack                     ;
181
wire      [WB_SLAVES-1:0]   s_wb_err                     ;
182
 
183
 
184
// ======================================
185
// Interrupts
186
// ======================================
187
wire                        amber_irq;
188
wire                        amber_firq;
189
wire                        ethmac_int;
190
wire                        test_reg_irq;
191
wire                        test_reg_firq;
192
wire                        uart0_int;
193
wire                        uart1_int;
194
wire      [2:0]             timer_int;
195
 
196
 
197
// ======================================
198
// Clocks and Resets Module
199
// ======================================
200
clocks_resets u_clocks_resets (
201
    .i_brd_rst          ( brd_rst           ),
202
    .i_brd_clk_n        ( brd_clk_n         ),
203
    .i_brd_clk_p        ( brd_clk_p         ),
204
    .i_ddr_calib_done   ( phy_init_done     ),
205
    .o_sys_rst          ( sys_rst           ),
206
    .o_sys_clk          ( sys_clk           ),
207
    .o_clk_200          ( clk_200           )
208
);
209
 
210
 
211
// -------------------------------------------------------------
212
// Instantiate Amber Processor Core
213
// -------------------------------------------------------------
214
 
215
amber u_amber (
216
    .i_clk          ( sys_clk         ),
217
 
218
    .i_irq          ( amber_irq       ),
219
    .i_firq         ( amber_firq      ),
220
 
221
    .i_system_rdy   ( phy_init_done   ),
222
 
223
    .o_wb_adr       ( m_wb_adr  [1]   ),
224
    .o_wb_sel       ( m_wb_sel  [1]   ),
225
    .o_wb_we        ( m_wb_we   [1]   ),
226
    .i_wb_dat       ( m_wb_dat_r[1]   ),
227
    .o_wb_dat       ( m_wb_dat_w[1]   ),
228
    .o_wb_cyc       ( m_wb_cyc  [1]   ),
229
    .o_wb_stb       ( m_wb_stb  [1]   ),
230
    .i_wb_ack       ( m_wb_ack  [1]   ),
231
    .i_wb_err       ( m_wb_err  [1]   )
232
);
233
 
234
 
235
// -------------------------------------------------------------
236
// Instantiate B100 Ethernet MAC
237
// -------------------------------------------------------------
238
 
239
eth_top u_eth_top (
240
    .wb_clk_i                   ( sys_clk                ),
241
    .wb_rst_i                   ( sys_rst                ),
242
 
243
    // WISHBONE slave
244
    .wb_adr_i                   ( s_wb_adr   [0][11:2]   ),
245
    .wb_sel_i                   ( s_wb_sel   [0]         ),
246
    .wb_we_i                    ( s_wb_we    [0]         ),
247
    .wb_cyc_i                   ( s_wb_cyc   [0]         ),
248
    .wb_stb_i                   ( s_wb_stb   [0]         ),
249
    .wb_ack_o                   ( s_wb_ack   [0]         ),
250
    .wb_dat_i                   ( s_wb_dat_w [0]         ),
251
    .wb_dat_o                   ( s_wb_dat_r [0]         ),
252
    .wb_err_o                   ( s_wb_err   [0]         ),
253
 
254
    // WISHBONE master
255
    .m_wb_adr_o                 ( m_wb_adr   [0]         ),
256
    .m_wb_sel_o                 ( m_wb_sel   [0]         ),
257
    .m_wb_we_o                  ( m_wb_we    [0]         ),
258
    .m_wb_dat_i                 ( m_wb_dat_r [0]         ),
259
    .m_wb_dat_o                 ( m_wb_dat_w [0]         ),
260
    .m_wb_cyc_o                 ( m_wb_cyc   [0]         ),
261
    .m_wb_stb_o                 ( m_wb_stb   [0]         ),
262
    .m_wb_ack_i                 ( m_wb_ack   [0]         ),
263
    .m_wb_err_i                 ( m_wb_err   [0]         ),
264
 
265
    // MAC to PHY I/F
266
    .mtx_clk_pad_i              ( mtx_clk_pad_i          ),
267
    .mtxd_pad_o                 ( mtxd_pad_o             ),
268
    .mtxen_pad_o                ( mtxen_pad_o            ),
269
    .mtxerr_pad_o               ( mtxerr_pad_o           ),
270
    .mrx_clk_pad_i              ( mrx_clk_pad_i          ),
271
    .mrxd_pad_i                 ( mrxd_pad_i             ),
272
    .mrxdv_pad_i                ( mrxdv_pad_i            ),
273
    .mrxerr_pad_i               ( mrxerr_pad_i           ),
274
    .mcoll_pad_i                ( mcoll_pad_i            ),
275
    .mcrs_pad_i                 ( mcrs_pad_i             ),
276
    .md_pad_i                   ( md_pad_i               ),
277
    .mdc_pad_o                  ( mdc_pad_o              ),
278
    .md_pad_o                   ( md_pad_o               ),
279
    .md_padoe_o                 ( md_padoe_o             ),
280
 
281
    // Interrupt
282
    .int_o                      ( ethmac_int             )
283
);
284
 
285
 
286
 
287
// -------------------------------------------------------------
288
// Instantiate Ethernet Control Interface tri-state buffer
289
// -------------------------------------------------------------
290
`ifdef XILINX_FPGA
291
IOBUF u_iobuf (
292
`else
293
generic_iobuf u_iobuf (
294
`endif
295
    .O                          ( md_pad_i              ),
296
    .IO                         ( md_pad_io             ),
297
    .I                          ( md_pad_o              ),
298
    // T is high for tri-state output
299
    .T                          ( ~md_padoe_o           )
300
);
301
 
302
// Ethernet MII PHY reset
303
assign phy_reset_n = !sys_rst;
304
 
305
 
306
// -------------------------------------------------------------
307
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
308
// -------------------------------------------------------------
309
boot_mem u_boot_mem (
310
    .i_wb_clk               ( sys_clk         ),
311
 
312
    .i_wb_adr               ( s_wb_adr  [1]   ),
313
    .i_wb_sel               ( s_wb_sel  [1]   ),
314
    .i_wb_we                ( s_wb_we   [1]   ),
315
    .o_wb_dat               ( s_wb_dat_r[1]   ),
316
    .i_wb_dat               ( s_wb_dat_w[1]   ),
317
    .i_wb_cyc               ( s_wb_cyc  [1]   ),
318
    .i_wb_stb               ( s_wb_stb  [1]   ),
319
    .o_wb_ack               ( s_wb_ack  [1]   ),
320
    .o_wb_err               ( s_wb_err  [1]   )
321
);
322
 
323
 
324
 
325
// -------------------------------------------------------------
326
// Instantiate UART0
327
// -------------------------------------------------------------
328
uart u_uart0 (
329
    .i_clk                  ( sys_clk        ),
330
 
331
    .o_uart_int             ( uart0_int      ),
332
 
333
    .i_uart_cts_n           ( i_uart0_rts    ),
334
    .o_uart_txd             ( o_uart0_rx     ),
335
    .o_uart_rts_n           ( o_uart0_cts    ),
336
    .i_uart_rxd             ( i_uart0_tx     ),
337
 
338
    .i_wb_adr               ( s_wb_adr  [3]  ),
339
    .i_wb_sel               ( s_wb_sel  [3]  ),
340
    .i_wb_we                ( s_wb_we   [3]  ),
341
    .o_wb_dat               ( s_wb_dat_r[3]  ),
342
    .i_wb_dat               ( s_wb_dat_w[3]  ),
343
    .i_wb_cyc               ( s_wb_cyc  [3]  ),
344
    .i_wb_stb               ( s_wb_stb  [3]  ),
345
    .o_wb_ack               ( s_wb_ack  [3]  ),
346
    .o_wb_err               ( s_wb_err  [3]  )
347
);
348
 
349
 
350
// -------------------------------------------------------------
351
// Instantiate UART1
352
// -------------------------------------------------------------
353
uart u_uart1 (
354
    .i_clk                  ( sys_clk        ),
355
 
356
    .o_uart_int             ( uart1_int      ),
357
 
358
    // These are not connected. ONly pins for 1 UART
359
    // on my development board
360
    .i_uart_cts_n           ( 1'd1           ),
361
    .o_uart_txd             (                ),
362
    .o_uart_rts_n           (                ),
363
    .i_uart_rxd             ( 1'd1           ),
364
 
365
    .i_wb_adr               ( s_wb_adr  [4]  ),
366
    .i_wb_sel               ( s_wb_sel  [4]  ),
367
    .i_wb_we                ( s_wb_we   [4]  ),
368
    .o_wb_dat               ( s_wb_dat_r[4]  ),
369
    .i_wb_dat               ( s_wb_dat_w[4]  ),
370
    .i_wb_cyc               ( s_wb_cyc  [4]  ),
371
    .i_wb_stb               ( s_wb_stb  [4]  ),
372
    .o_wb_ack               ( s_wb_ack  [4]  ),
373
    .o_wb_err               ( s_wb_err  [4]  )
374
);
375
 
376
 
377
// -------------------------------------------------------------
378
// Instantiate Test Module
379
//   - includes register used to terminate tests
380
// -------------------------------------------------------------
381
test_module u_test_module (
382
    .i_clk                  ( sys_clk        ),
383
 
384
    .o_irq                  ( test_reg_irq   ),
385
    .o_firq                 ( test_reg_firq  ),
386 11 csantifort
    .o_mem_ctrl             ( test_mem_ctrl  ),
387 2 csantifort
    .i_wb_adr               ( s_wb_adr  [5]  ),
388
    .i_wb_sel               ( s_wb_sel  [5]  ),
389
    .i_wb_we                ( s_wb_we   [5]  ),
390
    .o_wb_dat               ( s_wb_dat_r[5]  ),
391
    .i_wb_dat               ( s_wb_dat_w[5]  ),
392
    .i_wb_cyc               ( s_wb_cyc  [5]  ),
393
    .i_wb_stb               ( s_wb_stb  [5]  ),
394
    .o_wb_ack               ( s_wb_ack  [5]  ),
395
    .o_wb_err               ( s_wb_err  [5]  )
396
);
397
 
398
 
399
// -------------------------------------------------------------
400
// Instantiate Timer Module
401
// -------------------------------------------------------------
402
timer_module u_timer_module (
403
    .i_clk                  ( sys_clk        ),
404
 
405
    // Interrupt outputs
406
    .o_timer_int            ( timer_int      ),
407
 
408
    // Wishbone interface
409
    .i_wb_adr               ( s_wb_adr  [6]  ),
410
    .i_wb_sel               ( s_wb_sel  [6]  ),
411
    .i_wb_we                ( s_wb_we   [6]  ),
412
    .o_wb_dat               ( s_wb_dat_r[6]  ),
413
    .i_wb_dat               ( s_wb_dat_w[6]  ),
414
    .i_wb_cyc               ( s_wb_cyc  [6]  ),
415
    .i_wb_stb               ( s_wb_stb  [6]  ),
416
    .o_wb_ack               ( s_wb_ack  [6]  ),
417
    .o_wb_err               ( s_wb_err  [6]  )
418
);
419
 
420
 
421
// -------------------------------------------------------------
422
// Instantiate Interrupt Controller Module
423
// -------------------------------------------------------------
424
interrupt_controller u_interrupt_controller (
425
    .i_clk                  ( sys_clk        ),
426
 
427
    // Interrupt outputs
428
    .o_irq                  ( amber_irq      ),
429
    .o_firq                 ( amber_firq     ),
430
 
431
    // Interrupt inputs
432
    .i_uart0_int            ( uart0_int      ),
433
    .i_uart1_int            ( uart1_int      ),
434
    .i_ethmac_int           ( ethmac_int     ),
435
    .i_test_reg_irq         ( test_reg_irq   ),
436
    .i_test_reg_firq        ( test_reg_firq  ),
437
    .i_tm_timer_int         ( timer_int      ),
438
 
439
    // Wishbone interface
440
    .i_wb_adr               ( s_wb_adr  [7]  ),
441
    .i_wb_sel               ( s_wb_sel  [7]  ),
442
    .i_wb_we                ( s_wb_we   [7]  ),
443
    .o_wb_dat               ( s_wb_dat_r[7]  ),
444
    .i_wb_dat               ( s_wb_dat_w[7]  ),
445
    .i_wb_cyc               ( s_wb_cyc  [7]  ),
446
    .i_wb_stb               ( s_wb_stb  [7]  ),
447
    .o_wb_ack               ( s_wb_ack  [7]  ),
448
    .o_wb_err               ( s_wb_err  [7]  )
449
);
450
 
451
 
452
 
453
 
454
`ifndef XILINX_FPGA
455
    // ======================================
456
    // Instantiate non-synthesizable main memory model
457
    // ======================================
458
 
459
    assign phy_init_done = 1'd1;
460
 
461
    main_mem u_main_mem (
462
               .i_clk                  ( sys_clk               ),
463 11 csantifort
               .i_mem_ctrl             ( test_mem_ctrl         ),
464 2 csantifort
               .i_wb_adr               ( s_wb_adr  [2]         ),
465
               .i_wb_sel               ( s_wb_sel  [2]         ),
466
               .i_wb_we                ( s_wb_we   [2]         ),
467
               .o_wb_dat               ( s_wb_dat_r[2]         ),
468
               .i_wb_dat               ( s_wb_dat_w[2]         ),
469
               .i_wb_cyc               ( s_wb_cyc  [2]         ),
470
               .i_wb_stb               ( s_wb_stb  [2]         ),
471
               .o_wb_ack               ( s_wb_ack  [2]         ),
472
               .o_wb_err               ( s_wb_err  [2]         )
473
            );
474
 
475
`endif
476
 
477
 
478
`ifdef XILINX_SPARTAN6_FPGA
479
    // -------------------------------------------------------------
480
    // Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
481
    // -------------------------------------------------------------
482
    // The clock crossing fifo for spartan-6 is build into the mcb
483
    wb_xs6_ddr3_bridge u_wb_xs6_ddr3_bridge (
484
        .i_clk                  ( sys_clk               ),
485
 
486
        .o_cmd_en               ( c3_p0_cmd_en          ),
487
        .o_cmd_instr            ( c3_p0_cmd_instr       ),
488
        .o_cmd_byte_addr        ( c3_p0_cmd_byte_addr   ),
489
        .i_cmd_full             ( c3_p0_cmd_full        ),
490
        .i_wr_full              ( c3_p0_wr_full         ),
491
        .o_wr_en                ( c3_p0_wr_en           ),
492
        .o_wr_mask              ( c3_p0_wr_mask         ),
493
        .o_wr_data              ( c3_p0_wr_data         ),
494
        .i_rd_data              ( c3_p0_rd_data         ),
495
        .i_rd_empty             ( c3_p0_rd_empty        ),
496
 
497 11 csantifort
        .i_mem_ctrl             ( test_mem_ctrl         ),
498 2 csantifort
        .i_wb_adr               ( s_wb_adr  [2]         ),
499
        .i_wb_sel               ( s_wb_sel  [2]         ),
500
        .i_wb_we                ( s_wb_we   [2]         ),
501
        .o_wb_dat               ( s_wb_dat_r[2]         ),
502
        .i_wb_dat               ( s_wb_dat_w[2]         ),
503
        .i_wb_cyc               ( s_wb_cyc  [2]         ),
504
        .i_wb_stb               ( s_wb_stb  [2]         ),
505
        .o_wb_ack               ( s_wb_ack  [2]         ),
506
        .o_wb_err               ( s_wb_err  [2]         )
507
    );
508
 
509
 
510
    // -------------------------------------------------------------
511
    // Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
512
    // -------------------------------------------------------------
513
    mcb_ddr3 u_mcb_ddr3  (
514
 
515
                // DDR3 signals
516
               .mcb3_dram_dq            ( ddr3_dq               ),
517
               .mcb3_dram_a             ( ddr3_addr             ),
518
               .mcb3_dram_ba            ( ddr3_ba               ),
519
               .mcb3_dram_ras_n         ( ddr3_ras_n            ),
520
               .mcb3_dram_cas_n         ( ddr3_cas_n            ),
521
               .mcb3_dram_we_n          ( ddr3_we_n             ),
522
               .mcb3_dram_odt           ( ddr3_odt              ),
523
               .mcb3_dram_reset_n       ( ddr3_reset_n          ),
524
               .mcb3_dram_cke           ( ddr3_cke              ),
525
               .mcb3_dram_udm           ( ddr3_dm[1]            ),
526
               .mcb3_dram_dm            ( ddr3_dm[0]            ),
527
               .mcb3_rzq                ( mcb3_rzq              ),
528
               .mcb3_zio                ( mcb3_zio              ),
529
               .mcb3_dram_udqs          ( ddr3_dqs_p[1]         ),
530
               .mcb3_dram_dqs           ( ddr3_dqs_p[0]         ),
531
               .mcb3_dram_udqs_n        ( ddr3_dqs_n[1]         ),
532
               .mcb3_dram_dqs_n         ( ddr3_dqs_n[0]         ),
533
               .mcb3_dram_ck            ( ddr3_ck_p             ),
534
               .mcb3_dram_ck_n          ( ddr3_ck_n             ),
535
 
536
               .sys_clk_ibufg           ( clk_200               ),
537
               .c3_sys_rst_n            ( brd_rst               ),
538
 
539
               .c3_calib_done           ( phy_init_done         ),
540
 
541
               .c3_p0_cmd_clk           ( sys_clk               ),
542
 
543
               .c3_p0_cmd_en            ( c3_p0_cmd_en          ),
544
               .c3_p0_cmd_instr         ( c3_p0_cmd_instr       ),
545
               .c3_p0_cmd_bl            ( 6'd0                  ),
546
               .c3_p0_cmd_byte_addr     ( c3_p0_cmd_byte_addr   ),
547
               .c3_p0_cmd_empty         (                       ),
548
               .c3_p0_cmd_full          ( c3_p0_cmd_full        ),
549
 
550
               .c3_p0_wr_clk            ( sys_clk               ),
551
 
552
               .c3_p0_wr_en             ( c3_p0_wr_en           ),
553
               .c3_p0_wr_mask           ( c3_p0_wr_mask         ),
554
               .c3_p0_wr_data           ( c3_p0_wr_data         ),
555
               .c3_p0_wr_full           ( c3_p0_wr_full         ),
556
               .c3_p0_wr_empty          (                       ),
557
               .c3_p0_wr_count          (                       ),
558
               .c3_p0_wr_underrun       (                       ),
559
               .c3_p0_wr_error          (                       ),
560
 
561
               .c3_p0_rd_clk            ( sys_clk               ),
562
 
563
               .c3_p0_rd_en             ( 1'd1                  ),
564
               .c3_p0_rd_data           ( c3_p0_rd_data         ),
565
               .c3_p0_rd_full           (                       ),
566
               .c3_p0_rd_empty          ( c3_p0_rd_empty        ),
567
               .c3_p0_rd_count          (                       ),
568
               .c3_p0_rd_overflow       (                       ),
569
               .c3_p0_rd_error          (                       )
570
       );
571
`endif
572
 
573
 
574
`ifdef XILINX_VIRTEX6_FPGA
575
    // -------------------------------------------------------------
576
    // Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
577
    // -------------------------------------------------------------
578
    // The clock crossing fifo for virtex-6 is insode the bridge
579
    // module
580
    wb_xv6_ddr3_bridge u_wb_xv6_ddr3_bridge (
581
        .i_sys_clk              ( sys_clk               ),
582
        .i_ddr_clk              ( xv6_ddr3_clk          ),
583
 
584
        .o_ddr_cmd_en           ( xv6_cmd_en            ),
585
        .o_ddr_cmd_instr        ( xv6_cmd_instr         ),
586
        .o_ddr_cmd_byte_addr    ( xv6_cmd_byte_addr     ),
587
        .i_ddr_cmd_full         ( xv6_cmd_full          ),
588
 
589
        .i_ddr_wr_full          ( xv6_wr_full           ),
590
        .o_ddr_wr_en            ( xv6_wr_en             ),
591
        .o_ddr_wr_end           ( xv6_wr_end            ),
592
        .o_ddr_wr_mask          ( xv6_wr_mask           ),
593
        .o_ddr_wr_data          ( xv6_wr_data           ),
594
 
595
        .i_ddr_rd_data          ( xv6_rd_data           ),
596
        .i_ddr_rd_valid         ( xv6_rd_data_valid     ),
597
 
598
        .i_phy_init_done        ( phy_init_done1        ),
599
        .o_phy_init_done        ( phy_init_done         ),  // delayed version
600
 
601 11 csantifort
        .i_mem_ctrl             ( test_mem_ctrl         ),
602 2 csantifort
        .i_wb_adr               ( s_wb_adr  [2]         ),
603
        .i_wb_sel               ( s_wb_sel  [2]         ),
604
        .i_wb_we                ( s_wb_we   [2]         ),
605
        .o_wb_dat               ( s_wb_dat_r[2]         ),
606
        .i_wb_dat               ( s_wb_dat_w[2]         ),
607
        .i_wb_cyc               ( s_wb_cyc  [2]         ),
608
        .i_wb_stb               ( s_wb_stb  [2]         ),
609
        .o_wb_ack               ( s_wb_ack  [2]         ),
610
        .o_wb_err               ( s_wb_err  [2]         )
611
    );
612
 
613
 
614
    // -------------------------------------------------------------
615
    // Instantiate Xilinx Virtex-6 FPGA DDR3 Controller
616
    // -------------------------------------------------------------
617
    xv6_ddr3
618
    #(          // - Skip the memory initilization sequence,
619
                .SIM_INIT_OPTION        ("SKIP_PU_DLY"              ),
620
                // - Skip the delay Calibration process
621
                .SIM_CAL_OPTION         ("FAST_CAL"                 ),
622
                .RST_ACT_LOW            ( 0                         )
623
                )
624
    u_xv6_ddr3  (
625
                // DDR3 signals
626
                .ddr3_dq                ( ddr3_dq                   ),
627
                .ddr3_addr              ( ddr3_addr                 ),
628
                .ddr3_ba                ( ddr3_ba                   ),
629
                .ddr3_ras_n             ( ddr3_ras_n                ),
630
                .ddr3_cas_n             ( ddr3_cas_n                ),
631
                .ddr3_we_n              ( ddr3_we_n                 ),
632
                .ddr3_odt               ( ddr3_odt                  ),
633
                .ddr3_reset_n           ( ddr3_reset_n              ),
634
                .ddr3_cke               ( ddr3_cke                  ),
635
                .ddr3_dm                ( ddr3_dm                   ),
636
                .ddr3_dqs_p             ( ddr3_dqs_p                ),
637
                .ddr3_dqs_n             ( ddr3_dqs_n                ),
638
                .ddr3_ck_p              ( ddr3_ck_p                 ),
639
                .ddr3_ck_n              ( ddr3_ck_n                 ),
640
                .ddr3_cs_n              ( ddr3_cs_n                 ),
641
 
642
                // DDR clock
643
                .sys_clk_p              ( sys_clk_p                 ),
644
                .sys_clk_n              ( sys_clk_n                 ),
645
                .clk_ref                ( clk_200                   ),
646
                .sys_rst                ( brd_rst                   ),
647
                .tb_rst                 (                           ),
648
                .tb_clk                 ( xv6_ddr3_clk              ),
649
                .phy_init_done          ( phy_init_done1             ),
650
 
651
                .app_en                 ( xv6_cmd_en                ),
652
                .app_cmd                ( xv6_cmd_instr             ),
653
                .tg_addr                ( xv6_cmd_byte_addr         ),
654
                .app_full               ( xv6_cmd_full              ),
655
 
656
                .app_wdf_wren           ( xv6_wr_en                 ),
657
                .app_wdf_mask           ( xv6_wr_mask               ),
658
                .app_wdf_data           ( xv6_wr_data               ),
659
                .app_wdf_end            ( xv6_wr_end                ),
660
                .app_wdf_full           ( xv6_wr_full               ),
661
 
662
                .app_rd_data            ( xv6_rd_data               ),
663
                .app_rd_data_valid      ( xv6_rd_data_valid         )
664
                );
665
 
666
`endif
667
 
668
 
669
 
670
// -------------------------------------------------------------
671
// Instantiate Wishbone Arbiter
672
// -------------------------------------------------------------
673
wishbone_arbiter u_wishbone_arbiter (
674
    .i_wb_clk               ( sys_clk           ),
675
 
676
    // WISHBONE master 0 - Ethmac
677
    .i_m0_wb_adr            ( m_wb_adr   [0]    ),
678
    .i_m0_wb_sel            ( m_wb_sel   [0]    ),
679
    .i_m0_wb_we             ( m_wb_we    [0]    ),
680
    .o_m0_wb_dat            ( m_wb_dat_r [0]    ),
681
    .i_m0_wb_dat            ( m_wb_dat_w [0]    ),
682
    .i_m0_wb_cyc            ( m_wb_cyc   [0]    ),
683
    .i_m0_wb_stb            ( m_wb_stb   [0]    ),
684
    .o_m0_wb_ack            ( m_wb_ack   [0]    ),
685
    .o_m0_wb_err            ( m_wb_err   [0]    ),
686
 
687
 
688
    // WISHBONE master 1 - Amber Process or
689
    .i_m1_wb_adr            ( m_wb_adr   [1]    ),
690
    .i_m1_wb_sel            ( m_wb_sel   [1]    ),
691
    .i_m1_wb_we             ( m_wb_we    [1]    ),
692
    .o_m1_wb_dat            ( m_wb_dat_r [1]    ),
693
    .i_m1_wb_dat            ( m_wb_dat_w [1]    ),
694
    .i_m1_wb_cyc            ( m_wb_cyc   [1]    ),
695
    .i_m1_wb_stb            ( m_wb_stb   [1]    ),
696
    .o_m1_wb_ack            ( m_wb_ack   [1]    ),
697
    .o_m1_wb_err            ( m_wb_err   [1]    ),
698
 
699
 
700
    // WISHBONE slave 0 - Ethmac
701
    .o_s0_wb_adr            ( s_wb_adr   [0]    ),
702
    .o_s0_wb_sel            ( s_wb_sel   [0]    ),
703
    .o_s0_wb_we             ( s_wb_we    [0]    ),
704
    .i_s0_wb_dat            ( s_wb_dat_r [0]    ),
705
    .o_s0_wb_dat            ( s_wb_dat_w [0]    ),
706
    .o_s0_wb_cyc            ( s_wb_cyc   [0]    ),
707
    .o_s0_wb_stb            ( s_wb_stb   [0]    ),
708
    .i_s0_wb_ack            ( s_wb_ack   [0]    ),
709
    .i_s0_wb_err            ( s_wb_err   [0]    ),
710
 
711
 
712
    // WISHBONE slave 1 - Boot Memory
713
    .o_s1_wb_adr            ( s_wb_adr   [1]    ),
714
    .o_s1_wb_sel            ( s_wb_sel   [1]    ),
715
    .o_s1_wb_we             ( s_wb_we    [1]    ),
716
    .i_s1_wb_dat            ( s_wb_dat_r [1]    ),
717
    .o_s1_wb_dat            ( s_wb_dat_w [1]    ),
718
    .o_s1_wb_cyc            ( s_wb_cyc   [1]    ),
719
    .o_s1_wb_stb            ( s_wb_stb   [1]    ),
720
    .i_s1_wb_ack            ( s_wb_ack   [1]    ),
721
    .i_s1_wb_err            ( s_wb_err   [1]    ),
722
 
723
 
724
    // WISHBONE slave 2 - Main Memory
725
    .o_s2_wb_adr            ( s_wb_adr   [2]    ),
726
    .o_s2_wb_sel            ( s_wb_sel   [2]    ),
727
    .o_s2_wb_we             ( s_wb_we    [2]    ),
728
    .i_s2_wb_dat            ( s_wb_dat_r [2]    ),
729
    .o_s2_wb_dat            ( s_wb_dat_w [2]    ),
730
    .o_s2_wb_cyc            ( s_wb_cyc   [2]    ),
731
    .o_s2_wb_stb            ( s_wb_stb   [2]    ),
732
    .i_s2_wb_ack            ( s_wb_ack   [2]    ),
733
    .i_s2_wb_err            ( s_wb_err   [2]    ),
734
 
735
 
736
    // WISHBONE slave 3 - UART 0
737
    .o_s3_wb_adr            ( s_wb_adr   [3]    ),
738
    .o_s3_wb_sel            ( s_wb_sel   [3]    ),
739
    .o_s3_wb_we             ( s_wb_we    [3]    ),
740
    .i_s3_wb_dat            ( s_wb_dat_r [3]    ),
741
    .o_s3_wb_dat            ( s_wb_dat_w [3]    ),
742
    .o_s3_wb_cyc            ( s_wb_cyc   [3]    ),
743
    .o_s3_wb_stb            ( s_wb_stb   [3]    ),
744
    .i_s3_wb_ack            ( s_wb_ack   [3]    ),
745
    .i_s3_wb_err            ( s_wb_err   [3]    ),
746
 
747
 
748
    // WISHBONE slave 4 - UART 1
749
    .o_s4_wb_adr            ( s_wb_adr   [4]    ),
750
    .o_s4_wb_sel            ( s_wb_sel   [4]    ),
751
    .o_s4_wb_we             ( s_wb_we    [4]    ),
752
    .i_s4_wb_dat            ( s_wb_dat_r [4]    ),
753
    .o_s4_wb_dat            ( s_wb_dat_w [4]    ),
754
    .o_s4_wb_cyc            ( s_wb_cyc   [4]    ),
755
    .o_s4_wb_stb            ( s_wb_stb   [4]    ),
756
    .i_s4_wb_ack            ( s_wb_ack   [4]    ),
757
    .i_s4_wb_err            ( s_wb_err   [4]    ),
758
 
759
 
760
    // WISHBONE slave 5 - Test Module
761
    .o_s5_wb_adr            ( s_wb_adr   [5]    ),
762
    .o_s5_wb_sel            ( s_wb_sel   [5]    ),
763
    .o_s5_wb_we             ( s_wb_we    [5]    ),
764
    .i_s5_wb_dat            ( s_wb_dat_r [5]    ),
765
    .o_s5_wb_dat            ( s_wb_dat_w [5]    ),
766
    .o_s5_wb_cyc            ( s_wb_cyc   [5]    ),
767
    .o_s5_wb_stb            ( s_wb_stb   [5]    ),
768
    .i_s5_wb_ack            ( s_wb_ack   [5]    ),
769
    .i_s5_wb_err            ( s_wb_err   [5]    ),
770
 
771
 
772
    // WISHBONE slave 6 - Timer Module
773
    .o_s6_wb_adr            ( s_wb_adr   [6]    ),
774
    .o_s6_wb_sel            ( s_wb_sel   [6]    ),
775
    .o_s6_wb_we             ( s_wb_we    [6]    ),
776
    .i_s6_wb_dat            ( s_wb_dat_r [6]    ),
777
    .o_s6_wb_dat            ( s_wb_dat_w [6]    ),
778
    .o_s6_wb_cyc            ( s_wb_cyc   [6]    ),
779
    .o_s6_wb_stb            ( s_wb_stb   [6]    ),
780
    .i_s6_wb_ack            ( s_wb_ack   [6]    ),
781
    .i_s6_wb_err            ( s_wb_err   [6]    ),
782
 
783
 
784
    // WISHBONE slave 7 - Interrupt Controller
785
    .o_s7_wb_adr            ( s_wb_adr   [7]    ),
786
    .o_s7_wb_sel            ( s_wb_sel   [7]    ),
787
    .o_s7_wb_we             ( s_wb_we    [7]    ),
788
    .i_s7_wb_dat            ( s_wb_dat_r [7]    ),
789
    .o_s7_wb_dat            ( s_wb_dat_w [7]    ),
790
    .o_s7_wb_cyc            ( s_wb_cyc   [7]    ),
791
    .o_s7_wb_stb            ( s_wb_stb   [7]    ),
792
    .i_s7_wb_ack            ( s_wb_ack   [7]    ),
793
    .i_s7_wb_err            ( s_wb_err   [7]    )
794
    );
795
 
796
 
797
 
798
endmodule
799
 

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