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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [system.v] - Blame information for rev 78

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1 2 csantifort
//////////////////////////////////////////////////////////////////
2
//                                                              //
3
//  Top-level module instantiating the entire Amber 2 system.   //
4
//                                                              //
5
//  This file is part of the Amber project                      //
6
//  http://www.opencores.org/project,amber                      //
7
//                                                              //
8
//  Description                                                 //
9
//  This is the highest level synthesizable module in the       //
10
//  project. The ports in this module represent pins on the     //
11
//  FPGA.                                                       //
12
//                                                              //
13
//  Author(s):                                                  //
14
//      - Conor Santifort, csantifort.amber@gmail.com           //
15
//                                                              //
16
//////////////////////////////////////////////////////////////////
17
//                                                              //
18
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
19
//                                                              //
20
// This source file may be used and distributed without         //
21
// restriction provided that this copyright statement is not    //
22
// removed from the file and that any derivative work contains  //
23
// the original copyright notice and the associated disclaimer. //
24
//                                                              //
25
// This source file is free software; you can redistribute it   //
26
// and/or modify it under the terms of the GNU Lesser General   //
27
// Public License as published by the Free Software Foundation; //
28
// either version 2.1 of the License, or (at your option) any   //
29
// later version.                                               //
30
//                                                              //
31
// This source is distributed in the hope that it will be       //
32
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
33
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
34
// PURPOSE.  See the GNU Lesser General Public License for more //
35
// details.                                                     //
36
//                                                              //
37
// You should have received a copy of the GNU Lesser General    //
38
// Public License along with this source; if not, download it   //
39
// from http://www.opencores.org/lgpl.shtml                     //
40
//                                                              //
41
//////////////////////////////////////////////////////////////////
42
 
43
 
44 78 csantifort
module system
45 2 csantifort
(
46
input                       brd_rst,
47 78 csantifort
input                       brd_clk_n,
48
input                       brd_clk_p,
49 2 csantifort
 
50
 
51
// UART 0 Interface
52
input                       i_uart0_rts,
53
output                      o_uart0_rx,
54
output                      o_uart0_cts,
55
input                       i_uart0_tx,
56
 
57
// Xilinx Spartan 6 MCB DDR3 Interface
58
inout  [15:0]               ddr3_dq,
59
output [12:0]               ddr3_addr,
60
output [2:0]                ddr3_ba,
61
output                      ddr3_ras_n,
62
output                      ddr3_cas_n,
63
output                      ddr3_we_n,
64
output                      ddr3_odt,
65
output                      ddr3_reset_n,
66
output                      ddr3_cke,
67
output [1:0]                ddr3_dm,
68
inout  [1:0]                ddr3_dqs_p,
69
inout  [1:0]                ddr3_dqs_n,
70
output                      ddr3_ck_p,
71
output                      ddr3_ck_n,
72 64 csantifort
 
73 78 csantifort
`ifdef XILINX_SPARTAN6_FPGA
74 2 csantifort
inout                       mcb3_rzq,
75
`endif
76
 
77
 
78
// Ethmac B100 MAC to PHY Interface
79
input                       mtx_clk_pad_i,
80 78 csantifort
output  [3:0]               mtxd_pad_o,
81 2 csantifort
output                      mtxen_pad_o,
82
output                      mtxerr_pad_o,
83
input                       mrx_clk_pad_i,
84
input   [3:0]               mrxd_pad_i,
85
input                       mrxdv_pad_i,
86
input                       mrxerr_pad_i,
87
input                       mcoll_pad_i,
88
input                       mcrs_pad_i,
89
inout                       md_pad_io,
90 78 csantifort
output                      mdc_pad_o,
91 61 csantifort
output                      phy_reset_n,
92
 
93
output  [3:0]               led
94 2 csantifort
);
95
 
96
 
97
wire            sys_clk;    // System clock
98 78 csantifort
wire            sys_rst;    // Active high reset, synchronous to sys_clk
99 2 csantifort
wire            clk_200;    // 200MHz from board
100
 
101
 
102
// ======================================
103
// Xilinx MCB DDR3 Controller connections
104
// ======================================
105 78 csantifort
`ifdef XILINX_SPARTAN6_FPGA
106 2 csantifort
wire            c3_p0_cmd_en;
107
wire  [2:0]     c3_p0_cmd_instr;
108
wire  [29:0]    c3_p0_cmd_byte_addr;
109
wire            c3_p0_wr_en;
110
wire  [15:0]    c3_p0_wr_mask;
111
wire  [127:0]   c3_p0_wr_data;
112
wire  [127:0]   c3_p0_rd_data;
113
wire            c3_p0_rd_empty;
114
wire            c3_p0_cmd_full;
115
wire            c3_p0_wr_full;
116
`endif
117
 
118
wire            phy_init_done;
119 11 csantifort
wire            test_mem_ctrl;
120 15 csantifort
wire            system_rdy;
121 2 csantifort
 
122
 
123
// ======================================
124
// Ethmac MII
125
// ======================================
126
wire            md_pad_i;
127
wire            md_pad_o;
128
wire            md_padoe_o;
129
 
130
// ======================================
131
// Wishbone Buses
132
// ======================================
133
 
134
localparam WB_MASTERS = 2;
135
localparam WB_SLAVES  = 9;
136
 
137 35 csantifort
`ifdef AMBER_A25_CORE
138
localparam WB_DWIDTH  = 128;
139
localparam WB_SWIDTH  = 16;
140
`else
141
localparam WB_DWIDTH  = 32;
142
localparam WB_SWIDTH  = 4;
143
`endif
144 2 csantifort
 
145 35 csantifort
 
146 2 csantifort
// Wishbone Master Buses
147
wire      [31:0]            m_wb_adr      [WB_MASTERS-1:0];
148 35 csantifort
wire      [WB_SWIDTH-1:0]   m_wb_sel      [WB_MASTERS-1:0];
149 2 csantifort
wire      [WB_MASTERS-1:0]  m_wb_we                       ;
150 35 csantifort
wire      [WB_DWIDTH-1:0]   m_wb_dat_w    [WB_MASTERS-1:0];
151
wire      [WB_DWIDTH-1:0]   m_wb_dat_r    [WB_MASTERS-1:0];
152 2 csantifort
wire      [WB_MASTERS-1:0]  m_wb_cyc                      ;
153
wire      [WB_MASTERS-1:0]  m_wb_stb                      ;
154
wire      [WB_MASTERS-1:0]  m_wb_ack                      ;
155
wire      [WB_MASTERS-1:0]  m_wb_err                      ;
156
 
157
 
158
// Wishbone Slave Buses
159
wire      [31:0]            s_wb_adr      [WB_SLAVES-1:0];
160 35 csantifort
wire      [WB_SWIDTH-1:0]   s_wb_sel      [WB_SLAVES-1:0];
161 2 csantifort
wire      [WB_SLAVES-1:0]   s_wb_we                      ;
162 35 csantifort
wire      [WB_DWIDTH-1:0]   s_wb_dat_w    [WB_SLAVES-1:0];
163
wire      [WB_DWIDTH-1:0]   s_wb_dat_r    [WB_SLAVES-1:0];
164 2 csantifort
wire      [WB_SLAVES-1:0]   s_wb_cyc                     ;
165
wire      [WB_SLAVES-1:0]   s_wb_stb                     ;
166
wire      [WB_SLAVES-1:0]   s_wb_ack                     ;
167
wire      [WB_SLAVES-1:0]   s_wb_err                     ;
168
 
169 78 csantifort
wire      [31:0]            emm_wb_adr;
170
wire      [3:0]             emm_wb_sel;
171
wire                        emm_wb_we;
172
wire      [31:0]            emm_wb_rdat;
173
wire      [31:0]            emm_wb_wdat;
174
wire                        emm_wb_cyc;
175
wire                        emm_wb_stb;
176
wire                        emm_wb_ack;
177
wire                        emm_wb_err;
178 2 csantifort
 
179 78 csantifort
wire      [31:0]            ems_wb_adr;
180
wire      [3:0]             ems_wb_sel;
181
wire                        ems_wb_we;
182
wire      [31:0]            ems_wb_rdat;
183
wire      [31:0]            ems_wb_wdat;
184
wire                        ems_wb_cyc;
185
wire                        ems_wb_stb;
186
wire                        ems_wb_ack;
187
wire                        ems_wb_err;
188 35 csantifort
 
189
 
190 2 csantifort
// ======================================
191
// Interrupts
192
// ======================================
193
wire                        amber_irq;
194
wire                        amber_firq;
195
wire                        ethmac_int;
196
wire                        test_reg_irq;
197
wire                        test_reg_firq;
198
wire                        uart0_int;
199
wire                        uart1_int;
200
wire      [2:0]             timer_int;
201
 
202
 
203
// ======================================
204
// Clocks and Resets Module
205
// ======================================
206
clocks_resets u_clocks_resets (
207
    .i_brd_rst          ( brd_rst           ),
208 78 csantifort
    .i_brd_clk_n        ( brd_clk_n         ),
209
    .i_brd_clk_p        ( brd_clk_p         ),
210 2 csantifort
    .i_ddr_calib_done   ( phy_init_done     ),
211
    .o_sys_rst          ( sys_rst           ),
212
    .o_sys_clk          ( sys_clk           ),
213
    .o_clk_200          ( clk_200           )
214
);
215
 
216 78 csantifort
 
217 2 csantifort
// -------------------------------------------------------------
218
// Instantiate Amber Processor Core
219
// -------------------------------------------------------------
220 15 csantifort
`ifdef AMBER_A25_CORE
221
a25_core u_amber (
222
`else
223
a23_core u_amber (
224
`endif
225 2 csantifort
    .i_clk          ( sys_clk         ),
226 78 csantifort
 
227 2 csantifort
    .i_irq          ( amber_irq       ),
228
    .i_firq         ( amber_firq      ),
229
 
230 15 csantifort
    .i_system_rdy   ( system_rdy      ),
231 78 csantifort
 
232 2 csantifort
    .o_wb_adr       ( m_wb_adr  [1]   ),
233
    .o_wb_sel       ( m_wb_sel  [1]   ),
234
    .o_wb_we        ( m_wb_we   [1]   ),
235
    .i_wb_dat       ( m_wb_dat_r[1]   ),
236
    .o_wb_dat       ( m_wb_dat_w[1]   ),
237
    .o_wb_cyc       ( m_wb_cyc  [1]   ),
238
    .o_wb_stb       ( m_wb_stb  [1]   ),
239
    .i_wb_ack       ( m_wb_ack  [1]   ),
240
    .i_wb_err       ( m_wb_err  [1]   )
241
);
242
 
243
 
244
// -------------------------------------------------------------
245
// Instantiate B100 Ethernet MAC
246
// -------------------------------------------------------------
247
eth_top u_eth_top (
248
    .wb_clk_i                   ( sys_clk                ),
249
    .wb_rst_i                   ( sys_rst                ),
250
 
251
    // WISHBONE slave
252 78 csantifort
    .wb_adr_i                   ( ems_wb_adr [11:2]      ),
253
    .wb_sel_i                   ( ems_wb_sel             ),
254
    .wb_we_i                    ( ems_wb_we              ),
255
    .wb_cyc_i                   ( ems_wb_cyc             ),
256
    .wb_stb_i                   ( ems_wb_stb             ),
257
    .wb_ack_o                   ( ems_wb_ack             ),
258
    .wb_dat_i                   ( ems_wb_wdat            ),
259
    .wb_dat_o                   ( ems_wb_rdat            ),
260
    .wb_err_o                   ( ems_wb_err             ),
261 2 csantifort
 
262
    // WISHBONE master
263 78 csantifort
    .m_wb_adr_o                 ( emm_wb_adr             ),
264
    .m_wb_sel_o                 ( emm_wb_sel             ),
265
    .m_wb_we_o                  ( emm_wb_we              ),
266
    .m_wb_dat_i                 ( emm_wb_rdat            ),
267
    .m_wb_dat_o                 ( emm_wb_wdat            ),
268
    .m_wb_cyc_o                 ( emm_wb_cyc             ),
269
    .m_wb_stb_o                 ( emm_wb_stb             ),
270
    .m_wb_ack_i                 ( emm_wb_ack             ),
271
    .m_wb_err_i                 ( emm_wb_err             ),
272 2 csantifort
 
273
    // MAC to PHY I/F
274
    .mtx_clk_pad_i              ( mtx_clk_pad_i          ),
275
    .mtxd_pad_o                 ( mtxd_pad_o             ),
276
    .mtxen_pad_o                ( mtxen_pad_o            ),
277
    .mtxerr_pad_o               ( mtxerr_pad_o           ),
278
    .mrx_clk_pad_i              ( mrx_clk_pad_i          ),
279
    .mrxd_pad_i                 ( mrxd_pad_i             ),
280
    .mrxdv_pad_i                ( mrxdv_pad_i            ),
281 78 csantifort
    .mrxerr_pad_i               ( mrxerr_pad_i           ),
282
    .mcoll_pad_i                ( mcoll_pad_i            ),
283
    .mcrs_pad_i                 ( mcrs_pad_i             ),
284
    .md_pad_i                   ( md_pad_i               ),
285
    .mdc_pad_o                  ( mdc_pad_o              ),
286
    .md_pad_o                   ( md_pad_o               ),
287
    .md_padoe_o                 ( md_padoe_o             ),
288 2 csantifort
 
289
    // Interrupt
290
    .int_o                      ( ethmac_int             )
291
);
292
 
293
 
294
// -------------------------------------------------------------
295
// Instantiate Ethernet Control Interface tri-state buffer
296
// -------------------------------------------------------------
297
`ifdef XILINX_FPGA
298
IOBUF u_iobuf (
299
`else
300
generic_iobuf u_iobuf (
301
`endif
302 78 csantifort
    .O                          ( md_pad_i              ),
303
    .IO                         ( md_pad_io             ),
304
    .I                          ( md_pad_o              ),
305 2 csantifort
    // T is high for tri-state output
306 78 csantifort
    .T                          ( ~md_padoe_o           )
307 2 csantifort
);
308
 
309
// Ethernet MII PHY reset
310 15 csantifort
// Halt core until system is ready
311
assign system_rdy = phy_init_done && !sys_rst;
312 2 csantifort
 
313
// -------------------------------------------------------------
314
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
315
// -------------------------------------------------------------
316
 
317 36 csantifort
generate
318
if (WB_DWIDTH == 32) begin : boot_mem32
319
    boot_mem32 u_boot_mem (
320
        .i_wb_clk               ( sys_clk         ),
321
        .i_wb_adr               ( s_wb_adr  [1]   ),
322
        .i_wb_sel               ( s_wb_sel  [1]   ),
323
        .i_wb_we                ( s_wb_we   [1]   ),
324
        .o_wb_dat               ( s_wb_dat_r[1]   ),
325
        .i_wb_dat               ( s_wb_dat_w[1]   ),
326
        .i_wb_cyc               ( s_wb_cyc  [1]   ),
327
        .i_wb_stb               ( s_wb_stb  [1]   ),
328
        .o_wb_ack               ( s_wb_ack  [1]   ),
329
        .o_wb_err               ( s_wb_err  [1]   )
330
    );
331
end
332
else begin : boot_mem128
333
    boot_mem128 u_boot_mem (
334
        .i_wb_clk               ( sys_clk         ),
335
        .i_wb_adr               ( s_wb_adr  [1]   ),
336
        .i_wb_sel               ( s_wb_sel  [1]   ),
337
        .i_wb_we                ( s_wb_we   [1]   ),
338
        .o_wb_dat               ( s_wb_dat_r[1]   ),
339
        .i_wb_dat               ( s_wb_dat_w[1]   ),
340
        .i_wb_cyc               ( s_wb_cyc  [1]   ),
341
        .i_wb_stb               ( s_wb_stb  [1]   ),
342
        .o_wb_ack               ( s_wb_ack  [1]   ),
343
        .o_wb_err               ( s_wb_err  [1]   )
344
    );
345
end
346
endgenerate
347 2 csantifort
 
348
 
349
// -------------------------------------------------------------
350
// Instantiate UART0
351
// -------------------------------------------------------------
352 35 csantifort
uart  #(
353
    .WB_DWIDTH              ( WB_DWIDTH       ),
354
    .WB_SWIDTH              ( WB_SWIDTH       )
355
    )
356
u_uart0 (
357 2 csantifort
    .i_clk                  ( sys_clk        ),
358
 
359
    .o_uart_int             ( uart0_int      ),
360 78 csantifort
 
361 2 csantifort
    .i_uart_cts_n           ( i_uart0_rts    ),
362
    .o_uart_txd             ( o_uart0_rx     ),
363
    .o_uart_rts_n           ( o_uart0_cts    ),
364
    .i_uart_rxd             ( i_uart0_tx     ),
365 78 csantifort
 
366 2 csantifort
    .i_wb_adr               ( s_wb_adr  [3]  ),
367
    .i_wb_sel               ( s_wb_sel  [3]  ),
368
    .i_wb_we                ( s_wb_we   [3]  ),
369
    .o_wb_dat               ( s_wb_dat_r[3]  ),
370
    .i_wb_dat               ( s_wb_dat_w[3]  ),
371
    .i_wb_cyc               ( s_wb_cyc  [3]  ),
372
    .i_wb_stb               ( s_wb_stb  [3]  ),
373
    .o_wb_ack               ( s_wb_ack  [3]  ),
374
    .o_wb_err               ( s_wb_err  [3]  )
375
);
376
 
377
 
378
// -------------------------------------------------------------
379
// Instantiate UART1
380
// -------------------------------------------------------------
381 35 csantifort
uart  #(
382
    .WB_DWIDTH              ( WB_DWIDTH       ),
383
    .WB_SWIDTH              ( WB_SWIDTH       )
384 78 csantifort
    )
385 35 csantifort
u_uart1 (
386 2 csantifort
    .i_clk                  ( sys_clk        ),
387
 
388
    .o_uart_int             ( uart1_int      ),
389 78 csantifort
 
390 2 csantifort
    // These are not connected. ONly pins for 1 UART
391
    // on my development board
392
    .i_uart_cts_n           ( 1'd1           ),
393
    .o_uart_txd             (                ),
394
    .o_uart_rts_n           (                ),
395
    .i_uart_rxd             ( 1'd1           ),
396 78 csantifort
 
397 2 csantifort
    .i_wb_adr               ( s_wb_adr  [4]  ),
398
    .i_wb_sel               ( s_wb_sel  [4]  ),
399
    .i_wb_we                ( s_wb_we   [4]  ),
400
    .o_wb_dat               ( s_wb_dat_r[4]  ),
401
    .i_wb_dat               ( s_wb_dat_w[4]  ),
402
    .i_wb_cyc               ( s_wb_cyc  [4]  ),
403
    .i_wb_stb               ( s_wb_stb  [4]  ),
404
    .o_wb_ack               ( s_wb_ack  [4]  ),
405
    .o_wb_err               ( s_wb_err  [4]  )
406
);
407
 
408
 
409
// -------------------------------------------------------------
410
// Instantiate Test Module
411
//   - includes register used to terminate tests
412
// -------------------------------------------------------------
413 35 csantifort
test_module #(
414
    .WB_DWIDTH              ( WB_DWIDTH      ),
415
    .WB_SWIDTH              ( WB_SWIDTH      )
416 78 csantifort
    )
417 35 csantifort
u_test_module (
418 2 csantifort
    .i_clk                  ( sys_clk        ),
419 78 csantifort
 
420 2 csantifort
    .o_irq                  ( test_reg_irq   ),
421
    .o_firq                 ( test_reg_firq  ),
422 11 csantifort
    .o_mem_ctrl             ( test_mem_ctrl  ),
423 2 csantifort
    .i_wb_adr               ( s_wb_adr  [5]  ),
424
    .i_wb_sel               ( s_wb_sel  [5]  ),
425
    .i_wb_we                ( s_wb_we   [5]  ),
426
    .o_wb_dat               ( s_wb_dat_r[5]  ),
427
    .i_wb_dat               ( s_wb_dat_w[5]  ),
428
    .i_wb_cyc               ( s_wb_cyc  [5]  ),
429
    .i_wb_stb               ( s_wb_stb  [5]  ),
430
    .o_wb_ack               ( s_wb_ack  [5]  ),
431 61 csantifort
    .o_wb_err               ( s_wb_err  [5]  ),
432
    .o_led                  ( led            ),
433
    .o_phy_rst_n            ( phy_reset_n    )
434 2 csantifort
);
435
 
436
 
437
// -------------------------------------------------------------
438
// Instantiate Timer Module
439
// -------------------------------------------------------------
440 35 csantifort
timer_module  #(
441
    .WB_DWIDTH              ( WB_DWIDTH      ),
442
    .WB_SWIDTH              ( WB_SWIDTH      )
443 78 csantifort
    )
444 35 csantifort
u_timer_module (
445 2 csantifort
    .i_clk                  ( sys_clk        ),
446 78 csantifort
 
447 2 csantifort
    // Interrupt outputs
448
    .o_timer_int            ( timer_int      ),
449 78 csantifort
 
450 2 csantifort
    // Wishbone interface
451
    .i_wb_adr               ( s_wb_adr  [6]  ),
452
    .i_wb_sel               ( s_wb_sel  [6]  ),
453
    .i_wb_we                ( s_wb_we   [6]  ),
454
    .o_wb_dat               ( s_wb_dat_r[6]  ),
455
    .i_wb_dat               ( s_wb_dat_w[6]  ),
456
    .i_wb_cyc               ( s_wb_cyc  [6]  ),
457
    .i_wb_stb               ( s_wb_stb  [6]  ),
458
    .o_wb_ack               ( s_wb_ack  [6]  ),
459
    .o_wb_err               ( s_wb_err  [6]  )
460
);
461
 
462
 
463
// -------------------------------------------------------------
464
// Instantiate Interrupt Controller Module
465
// -------------------------------------------------------------
466 35 csantifort
interrupt_controller  #(
467
    .WB_DWIDTH              ( WB_DWIDTH      ),
468
    .WB_SWIDTH              ( WB_SWIDTH      )
469
    )
470
u_interrupt_controller (
471 2 csantifort
    .i_clk                  ( sys_clk        ),
472 78 csantifort
 
473 2 csantifort
    // Interrupt outputs
474
    .o_irq                  ( amber_irq      ),
475
    .o_firq                 ( amber_firq     ),
476 78 csantifort
 
477 2 csantifort
    // Interrupt inputs
478
    .i_uart0_int            ( uart0_int      ),
479
    .i_uart1_int            ( uart1_int      ),
480
    .i_ethmac_int           ( ethmac_int     ),
481
    .i_test_reg_irq         ( test_reg_irq   ),
482
    .i_test_reg_firq        ( test_reg_firq  ),
483
    .i_tm_timer_int         ( timer_int      ),
484 78 csantifort
 
485 2 csantifort
    // Wishbone interface
486
    .i_wb_adr               ( s_wb_adr  [7]  ),
487
    .i_wb_sel               ( s_wb_sel  [7]  ),
488
    .i_wb_we                ( s_wb_we   [7]  ),
489
    .o_wb_dat               ( s_wb_dat_r[7]  ),
490
    .i_wb_dat               ( s_wb_dat_w[7]  ),
491
    .i_wb_cyc               ( s_wb_cyc  [7]  ),
492
    .i_wb_stb               ( s_wb_stb  [7]  ),
493
    .o_wb_ack               ( s_wb_ack  [7]  ),
494
    .o_wb_err               ( s_wb_err  [7]  )
495
);
496
 
497
 
498
 
499
 
500
`ifndef XILINX_FPGA
501
    // ======================================
502
    // Instantiate non-synthesizable main memory model
503
    // ======================================
504 78 csantifort
 
505 2 csantifort
    assign phy_init_done = 1'd1;
506 78 csantifort
 
507 35 csantifort
    main_mem #(
508
                .WB_DWIDTH             ( WB_DWIDTH             ),
509
                .WB_SWIDTH             ( WB_SWIDTH             )
510 78 csantifort
                )
511 35 csantifort
    u_main_mem (
512 2 csantifort
               .i_clk                  ( sys_clk               ),
513 11 csantifort
               .i_mem_ctrl             ( test_mem_ctrl         ),
514 78 csantifort
               .i_wb_adr               ( s_wb_adr  [2]         ),
515
               .i_wb_sel               ( s_wb_sel  [2]         ),
516
               .i_wb_we                ( s_wb_we   [2]         ),
517
               .o_wb_dat               ( s_wb_dat_r[2]         ),
518
               .i_wb_dat               ( s_wb_dat_w[2]         ),
519
               .i_wb_cyc               ( s_wb_cyc  [2]         ),
520
               .i_wb_stb               ( s_wb_stb  [2]         ),
521
               .o_wb_ack               ( s_wb_ack  [2]         ),
522
               .o_wb_err               ( s_wb_err  [2]         )
523 2 csantifort
            );
524
 
525
`endif
526
 
527
 
528 78 csantifort
`ifdef XILINX_SPARTAN6_FPGA
529 2 csantifort
    // -------------------------------------------------------------
530
    // Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
531
    // -------------------------------------------------------------
532
    // The clock crossing fifo for spartan-6 is build into the mcb
533 36 csantifort
    wb_xs6_ddr3_bridge   #(
534
        .WB_DWIDTH              ( WB_DWIDTH             ),
535
        .WB_SWIDTH              ( WB_SWIDTH             )
536
        )
537
    u_wb_xs6_ddr3_bridge(
538 2 csantifort
        .i_clk                  ( sys_clk               ),
539
 
540 78 csantifort
        .o_cmd_en               ( c3_p0_cmd_en          ),
541
        .o_cmd_instr            ( c3_p0_cmd_instr       ),
542
        .o_cmd_byte_addr        ( c3_p0_cmd_byte_addr   ),
543
        .i_cmd_full             ( c3_p0_cmd_full        ),
544
        .i_wr_full              ( c3_p0_wr_full         ),
545
        .o_wr_en                ( c3_p0_wr_en           ),
546
        .o_wr_mask              ( c3_p0_wr_mask         ),
547
        .o_wr_data              ( c3_p0_wr_data         ),
548
        .i_rd_data              ( c3_p0_rd_data         ),
549 2 csantifort
        .i_rd_empty             ( c3_p0_rd_empty        ),
550 78 csantifort
 
551 11 csantifort
        .i_mem_ctrl             ( test_mem_ctrl         ),
552 78 csantifort
        .i_wb_adr               ( s_wb_adr  [2]         ),
553
        .i_wb_sel               ( s_wb_sel  [2]         ),
554
        .i_wb_we                ( s_wb_we   [2]         ),
555
        .o_wb_dat               ( s_wb_dat_r[2]         ),
556
        .i_wb_dat               ( s_wb_dat_w[2]         ),
557
        .i_wb_cyc               ( s_wb_cyc  [2]         ),
558
        .i_wb_stb               ( s_wb_stb  [2]         ),
559
        .o_wb_ack               ( s_wb_ack  [2]         ),
560
        .o_wb_err               ( s_wb_err  [2]         )
561 2 csantifort
    );
562
 
563 78 csantifort
 
564 2 csantifort
    // -------------------------------------------------------------
565
    // Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
566
    // -------------------------------------------------------------
567 64 csantifort
    ddr3 u_ddr3  (
568 2 csantifort
 
569
                // DDR3 signals
570
               .mcb3_dram_dq            ( ddr3_dq               ),
571
               .mcb3_dram_a             ( ddr3_addr             ),
572
               .mcb3_dram_ba            ( ddr3_ba               ),
573
               .mcb3_dram_ras_n         ( ddr3_ras_n            ),
574
               .mcb3_dram_cas_n         ( ddr3_cas_n            ),
575
               .mcb3_dram_we_n          ( ddr3_we_n             ),
576
               .mcb3_dram_odt           ( ddr3_odt              ),
577
               .mcb3_dram_reset_n       ( ddr3_reset_n          ),
578
               .mcb3_dram_cke           ( ddr3_cke              ),
579
               .mcb3_dram_udm           ( ddr3_dm[1]            ),
580
               .mcb3_dram_dm            ( ddr3_dm[0]            ),
581
               .mcb3_rzq                ( mcb3_rzq              ),
582
               .mcb3_dram_udqs          ( ddr3_dqs_p[1]         ),
583
               .mcb3_dram_dqs           ( ddr3_dqs_p[0]         ),
584
               .mcb3_dram_udqs_n        ( ddr3_dqs_n[1]         ),
585
               .mcb3_dram_dqs_n         ( ddr3_dqs_n[0]         ),
586
               .mcb3_dram_ck            ( ddr3_ck_p             ),
587
               .mcb3_dram_ck_n          ( ddr3_ck_n             ),
588 78 csantifort
 
589
               .c3_sys_clk              ( clk_200               ),
590 64 csantifort
               .c3_sys_rst_i            ( brd_rst               ), // active-high
591
               .c3_clk0                 (                       ),
592
               .c3_rst0                 (                       ),
593 2 csantifort
               .c3_calib_done           ( phy_init_done         ),
594 78 csantifort
 
595 2 csantifort
               .c3_p0_cmd_clk           ( sys_clk               ),
596 78 csantifort
 
597 2 csantifort
               .c3_p0_cmd_en            ( c3_p0_cmd_en          ),
598
               .c3_p0_cmd_instr         ( c3_p0_cmd_instr       ),
599
               .c3_p0_cmd_bl            ( 6'd0                  ),
600
               .c3_p0_cmd_byte_addr     ( c3_p0_cmd_byte_addr   ),
601
               .c3_p0_cmd_empty         (                       ),
602
               .c3_p0_cmd_full          ( c3_p0_cmd_full        ),
603 78 csantifort
 
604 2 csantifort
               .c3_p0_wr_clk            ( sys_clk               ),
605 78 csantifort
 
606 2 csantifort
               .c3_p0_wr_en             ( c3_p0_wr_en           ),
607
               .c3_p0_wr_mask           ( c3_p0_wr_mask         ),
608
               .c3_p0_wr_data           ( c3_p0_wr_data         ),
609
               .c3_p0_wr_full           ( c3_p0_wr_full         ),
610
               .c3_p0_wr_empty          (                       ),
611
               .c3_p0_wr_count          (                       ),
612
               .c3_p0_wr_underrun       (                       ),
613
               .c3_p0_wr_error          (                       ),
614 78 csantifort
 
615 2 csantifort
               .c3_p0_rd_clk            ( sys_clk               ),
616 78 csantifort
 
617 2 csantifort
               .c3_p0_rd_en             ( 1'd1                  ),
618
               .c3_p0_rd_data           ( c3_p0_rd_data         ),
619
               .c3_p0_rd_full           (                       ),
620
               .c3_p0_rd_empty          ( c3_p0_rd_empty        ),
621
               .c3_p0_rd_count          (                       ),
622
               .c3_p0_rd_overflow       (                       ),
623
               .c3_p0_rd_error          (                       )
624
       );
625
`endif
626
 
627
 
628
 
629
// -------------------------------------------------------------
630
// Instantiate Wishbone Arbiter
631
// -------------------------------------------------------------
632 35 csantifort
wishbone_arbiter #(
633
    .WB_DWIDTH              ( WB_DWIDTH         ),
634
    .WB_SWIDTH              ( WB_SWIDTH         )
635
    )
636
u_wishbone_arbiter (
637 2 csantifort
    .i_wb_clk               ( sys_clk           ),
638
 
639
    // WISHBONE master 0 - Ethmac
640
    .i_m0_wb_adr            ( m_wb_adr   [0]    ),
641
    .i_m0_wb_sel            ( m_wb_sel   [0]    ),
642
    .i_m0_wb_we             ( m_wb_we    [0]    ),
643
    .o_m0_wb_dat            ( m_wb_dat_r [0]    ),
644
    .i_m0_wb_dat            ( m_wb_dat_w [0]    ),
645
    .i_m0_wb_cyc            ( m_wb_cyc   [0]    ),
646
    .i_m0_wb_stb            ( m_wb_stb   [0]    ),
647
    .o_m0_wb_ack            ( m_wb_ack   [0]    ),
648
    .o_m0_wb_err            ( m_wb_err   [0]    ),
649
 
650
 
651
    // WISHBONE master 1 - Amber Process or
652
    .i_m1_wb_adr            ( m_wb_adr   [1]    ),
653
    .i_m1_wb_sel            ( m_wb_sel   [1]    ),
654
    .i_m1_wb_we             ( m_wb_we    [1]    ),
655
    .o_m1_wb_dat            ( m_wb_dat_r [1]    ),
656
    .i_m1_wb_dat            ( m_wb_dat_w [1]    ),
657
    .i_m1_wb_cyc            ( m_wb_cyc   [1]    ),
658
    .i_m1_wb_stb            ( m_wb_stb   [1]    ),
659
    .o_m1_wb_ack            ( m_wb_ack   [1]    ),
660
    .o_m1_wb_err            ( m_wb_err   [1]    ),
661
 
662
 
663
    // WISHBONE slave 0 - Ethmac
664
    .o_s0_wb_adr            ( s_wb_adr   [0]    ),
665
    .o_s0_wb_sel            ( s_wb_sel   [0]    ),
666
    .o_s0_wb_we             ( s_wb_we    [0]    ),
667
    .i_s0_wb_dat            ( s_wb_dat_r [0]    ),
668
    .o_s0_wb_dat            ( s_wb_dat_w [0]    ),
669
    .o_s0_wb_cyc            ( s_wb_cyc   [0]    ),
670
    .o_s0_wb_stb            ( s_wb_stb   [0]    ),
671
    .i_s0_wb_ack            ( s_wb_ack   [0]    ),
672
    .i_s0_wb_err            ( s_wb_err   [0]    ),
673
 
674
 
675
    // WISHBONE slave 1 - Boot Memory
676
    .o_s1_wb_adr            ( s_wb_adr   [1]    ),
677
    .o_s1_wb_sel            ( s_wb_sel   [1]    ),
678
    .o_s1_wb_we             ( s_wb_we    [1]    ),
679
    .i_s1_wb_dat            ( s_wb_dat_r [1]    ),
680
    .o_s1_wb_dat            ( s_wb_dat_w [1]    ),
681
    .o_s1_wb_cyc            ( s_wb_cyc   [1]    ),
682
    .o_s1_wb_stb            ( s_wb_stb   [1]    ),
683
    .i_s1_wb_ack            ( s_wb_ack   [1]    ),
684
    .i_s1_wb_err            ( s_wb_err   [1]    ),
685
 
686
 
687
    // WISHBONE slave 2 - Main Memory
688
    .o_s2_wb_adr            ( s_wb_adr   [2]    ),
689
    .o_s2_wb_sel            ( s_wb_sel   [2]    ),
690
    .o_s2_wb_we             ( s_wb_we    [2]    ),
691
    .i_s2_wb_dat            ( s_wb_dat_r [2]    ),
692
    .o_s2_wb_dat            ( s_wb_dat_w [2]    ),
693
    .o_s2_wb_cyc            ( s_wb_cyc   [2]    ),
694
    .o_s2_wb_stb            ( s_wb_stb   [2]    ),
695
    .i_s2_wb_ack            ( s_wb_ack   [2]    ),
696
    .i_s2_wb_err            ( s_wb_err   [2]    ),
697
 
698
 
699
    // WISHBONE slave 3 - UART 0
700
    .o_s3_wb_adr            ( s_wb_adr   [3]    ),
701
    .o_s3_wb_sel            ( s_wb_sel   [3]    ),
702
    .o_s3_wb_we             ( s_wb_we    [3]    ),
703
    .i_s3_wb_dat            ( s_wb_dat_r [3]    ),
704
    .o_s3_wb_dat            ( s_wb_dat_w [3]    ),
705
    .o_s3_wb_cyc            ( s_wb_cyc   [3]    ),
706
    .o_s3_wb_stb            ( s_wb_stb   [3]    ),
707
    .i_s3_wb_ack            ( s_wb_ack   [3]    ),
708
    .i_s3_wb_err            ( s_wb_err   [3]    ),
709
 
710
 
711
    // WISHBONE slave 4 - UART 1
712
    .o_s4_wb_adr            ( s_wb_adr   [4]    ),
713
    .o_s4_wb_sel            ( s_wb_sel   [4]    ),
714
    .o_s4_wb_we             ( s_wb_we    [4]    ),
715
    .i_s4_wb_dat            ( s_wb_dat_r [4]    ),
716
    .o_s4_wb_dat            ( s_wb_dat_w [4]    ),
717
    .o_s4_wb_cyc            ( s_wb_cyc   [4]    ),
718
    .o_s4_wb_stb            ( s_wb_stb   [4]    ),
719
    .i_s4_wb_ack            ( s_wb_ack   [4]    ),
720
    .i_s4_wb_err            ( s_wb_err   [4]    ),
721
 
722
 
723
    // WISHBONE slave 5 - Test Module
724
    .o_s5_wb_adr            ( s_wb_adr   [5]    ),
725
    .o_s5_wb_sel            ( s_wb_sel   [5]    ),
726
    .o_s5_wb_we             ( s_wb_we    [5]    ),
727
    .i_s5_wb_dat            ( s_wb_dat_r [5]    ),
728
    .o_s5_wb_dat            ( s_wb_dat_w [5]    ),
729
    .o_s5_wb_cyc            ( s_wb_cyc   [5]    ),
730
    .o_s5_wb_stb            ( s_wb_stb   [5]    ),
731
    .i_s5_wb_ack            ( s_wb_ack   [5]    ),
732
    .i_s5_wb_err            ( s_wb_err   [5]    ),
733
 
734
 
735
    // WISHBONE slave 6 - Timer Module
736
    .o_s6_wb_adr            ( s_wb_adr   [6]    ),
737
    .o_s6_wb_sel            ( s_wb_sel   [6]    ),
738
    .o_s6_wb_we             ( s_wb_we    [6]    ),
739
    .i_s6_wb_dat            ( s_wb_dat_r [6]    ),
740
    .o_s6_wb_dat            ( s_wb_dat_w [6]    ),
741
    .o_s6_wb_cyc            ( s_wb_cyc   [6]    ),
742
    .o_s6_wb_stb            ( s_wb_stb   [6]    ),
743
    .i_s6_wb_ack            ( s_wb_ack   [6]    ),
744
    .i_s6_wb_err            ( s_wb_err   [6]    ),
745
 
746
 
747
    // WISHBONE slave 7 - Interrupt Controller
748
    .o_s7_wb_adr            ( s_wb_adr   [7]    ),
749
    .o_s7_wb_sel            ( s_wb_sel   [7]    ),
750
    .o_s7_wb_we             ( s_wb_we    [7]    ),
751
    .i_s7_wb_dat            ( s_wb_dat_r [7]    ),
752
    .o_s7_wb_dat            ( s_wb_dat_w [7]    ),
753
    .o_s7_wb_cyc            ( s_wb_cyc   [7]    ),
754
    .o_s7_wb_stb            ( s_wb_stb   [7]    ),
755
    .i_s7_wb_ack            ( s_wb_ack   [7]    ),
756
    .i_s7_wb_err            ( s_wb_err   [7]    )
757
    );
758
 
759
 
760 35 csantifort
ethmac_wb #(
761
    .WB_DWIDTH              ( WB_DWIDTH         ),
762
    .WB_SWIDTH              ( WB_SWIDTH         )
763
    )
764
u_ethmac_wb (
765
    // Wishbone arbiter side
766
    .o_m_wb_adr             ( m_wb_adr   [0]    ),
767
    .o_m_wb_sel             ( m_wb_sel   [0]    ),
768
    .o_m_wb_we              ( m_wb_we    [0]    ),
769
    .i_m_wb_rdat            ( m_wb_dat_r [0]    ),
770
    .o_m_wb_wdat            ( m_wb_dat_w [0]    ),
771
    .o_m_wb_cyc             ( m_wb_cyc   [0]    ),
772
    .o_m_wb_stb             ( m_wb_stb   [0]    ),
773
    .i_m_wb_ack             ( m_wb_ack   [0]    ),
774
    .i_m_wb_err             ( m_wb_err   [0]    ),
775 2 csantifort
 
776 35 csantifort
    // Wishbone arbiter side
777
    .i_s_wb_adr             ( s_wb_adr   [0]    ),
778
    .i_s_wb_sel             ( s_wb_sel   [0]    ),
779
    .i_s_wb_we              ( s_wb_we    [0]    ),
780
    .i_s_wb_cyc             ( s_wb_cyc   [0]    ),
781
    .i_s_wb_stb             ( s_wb_stb   [0]    ),
782
    .o_s_wb_ack             ( s_wb_ack   [0]    ),
783
    .i_s_wb_wdat            ( s_wb_dat_w [0]    ),
784
    .o_s_wb_rdat            ( s_wb_dat_r [0]    ),
785
    .o_s_wb_err             ( s_wb_err   [0]    ),
786
 
787
    // Ethmac side
788
    .i_m_wb_adr             ( emm_wb_adr        ),
789
    .i_m_wb_sel             ( emm_wb_sel        ),
790
    .i_m_wb_we              ( emm_wb_we         ),
791
    .o_m_wb_rdat            ( emm_wb_rdat       ),
792
    .i_m_wb_wdat            ( emm_wb_wdat       ),
793
    .i_m_wb_cyc             ( emm_wb_cyc        ),
794
    .i_m_wb_stb             ( emm_wb_stb        ),
795
    .o_m_wb_ack             ( emm_wb_ack        ),
796
    .o_m_wb_err             ( emm_wb_err        ),
797
 
798
    // Ethmac side
799
    .o_s_wb_adr             ( ems_wb_adr        ),
800
    .o_s_wb_sel             ( ems_wb_sel        ),
801
    .o_s_wb_we              ( ems_wb_we         ),
802
    .i_s_wb_rdat            ( ems_wb_rdat       ),
803
    .o_s_wb_wdat            ( ems_wb_wdat       ),
804
    .o_s_wb_cyc             ( ems_wb_cyc        ),
805
    .o_s_wb_stb             ( ems_wb_stb        ),
806
    .i_s_wb_ack             ( ems_wb_ack        ),
807
    .i_s_wb_err             ( ems_wb_err        )
808
);
809
 
810
 
811
 
812
 
813 2 csantifort
endmodule
814
 
815 35 csantifort
 

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