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//////////////////////////////////////////////////////////////////
//                                                              //
//  Test Module                                                 //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Contains a random number generator and a couple of timers   //
//  that connect to interrupt lines. Used for testing the       //
//  ssytem.                                                     //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
 
module test_module   #(
parameter WB_DWIDTH  = 32,
parameter WB_SWIDTH  = 4
)(
input                       i_clk,
 
output                      o_irq,
output                      o_firq,
output                      o_mem_ctrl,  // 0=128MB, 1=32MB
input       [31:0]          i_wb_adr,
input       [WB_SWIDTH-1:0] i_wb_sel,
input                       i_wb_we,
output      [WB_DWIDTH-1:0] o_wb_dat,
input       [WB_DWIDTH-1:0] i_wb_dat,
input                       i_wb_cyc,
input                       i_wb_stb,
output                      o_wb_ack,
output                      o_wb_err,
output     [3:0]            o_led,
output                      o_phy_rst_n
 
);
 
`include "register_addresses.vh"
 
 
reg [7:0]       firq_timer          = 'd0;
reg [7:0]       irq_timer           = 'd0;
reg [7:0]       random_num          = 8'hf3;
 
//synopsys translate_off
reg [1:0]       tb_uart_control_reg = 'd0;
reg [1:0]       tb_uart_status_reg  = 'd0;
reg             tb_uart_push        = 'd0;
reg [7:0]       tb_uart_txd_reg     = 'd0;
//synopsys translate_on
 
reg [2:0]       sim_ctrl_reg        = 'd0; // 0 = fpga, other values for simulations
reg             mem_ctrl_reg        = 'd0; // 0 = 128MB, 1 = 32MB main memory
reg [31:0]      test_status_reg     = 'd0;
reg             test_status_set     = 'd0; // used to terminate tests
reg [31:0]      cycles_reg          = 'd0;
 
wire            wb_start_write;
wire            wb_start_read;
reg             wb_start_read_d1    = 'd0;
reg  [31:0]     wb_rdata32          = 'd0;
wire [31:0]     wb_wdata32;
 
reg  [3:0]      led_reg             = 'd0;
reg             phy_rst_reg         = 'd0;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
assign wb_start_read  = i_wb_stb && !i_wb_we && !o_wb_ack;
 
always @( posedge i_clk )
    wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack     = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err     = 1'd0;
assign o_mem_ctrl   = mem_ctrl_reg;
assign o_led        = led_reg;
assign o_phy_rst_n  = phy_rst_reg;
 
generate
if (WB_DWIDTH == 128)
    begin : wb128
    assign wb_wdata32   = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
                          i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
                          i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
                                                  i_wb_dat[ 31: 0] ;
 
    assign o_wb_dat    = {4{wb_rdata32}};
    end
else
    begin : wb32
    assign wb_wdata32  = i_wb_dat;
    assign o_wb_dat    = wb_rdata32;
    end
endgenerate
 
 
// ========================================================
// Register Reads
// ========================================================
always @( posedge i_clk )
    if ( wb_start_read )
        case ( i_wb_adr[15:0] )
            AMBER_TEST_STATUS:           wb_rdata32 <= test_status_reg;
            AMBER_TEST_FIRQ_TIMER:       wb_rdata32 <= {24'd0, firq_timer};
            AMBER_TEST_IRQ_TIMER:        wb_rdata32 <= {24'd0, irq_timer};
            AMBER_TEST_RANDOM_NUM:       wb_rdata32 <= {24'd0, random_num};
 
            /* Allow access to the random register over
               a 16-word address range to load a series
               of random numbers using lmd instruction. */
            AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};
            AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};
 
            //synopsys translate_off
            AMBER_TEST_UART_CONTROL:     wb_rdata32 <= {30'd0, tb_uart_control_reg};
            AMBER_TEST_UART_STATUS:      wb_rdata32 <= {30'd0, tb_uart_status_reg};
            AMBER_TEST_UART_TXD:         wb_rdata32 <= {24'd0, tb_uart_txd_reg};
            //synopsys translate_on
 
            AMBER_TEST_SIM_CTRL:         wb_rdata32 <= {29'd0, sim_ctrl_reg};
            AMBER_TEST_MEM_CTRL:         wb_rdata32 <= {31'd0, mem_ctrl_reg};
 
            AMBER_TEST_CYCLES:           wb_rdata32 <=  cycles_reg;
            AMBER_TEST_LED:              wb_rdata32 <= {27'd0, led_reg};
            AMBER_TEST_PHY_RST:          wb_rdata32 <= {31'd0, phy_rst_reg};
            default:                     wb_rdata32 <= 32'haabbccdd;
 
        endcase
 
 
// ======================================
// Simulation bit
// ======================================
 
// This register bit is a 1 in simulation but a 0 in the real fpga
// Used by software to tell the difference    
//synopsys translate_off
 
`ifndef AMBER_SIM_CTRL
    `define AMBER_SIM_CTRL 0
`endif
 
always @( posedge i_clk )
    begin
    // Value reads as 1 in simulation, and zero in the FPGA
    sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
    end
//synopsys translate_on
 
 
// ======================================
// Interrupts
// ======================================
assign o_irq  = irq_timer  == 8'd1;
assign o_firq = firq_timer == 8'd1;
 
 
// ======================================
// FIRQ Timer Register
// ======================================
    // Write a value > 1 to set the firq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )
        firq_timer <= wb_wdata32[7:0];
    else if ( firq_timer > 8'd1 )
        firq_timer <= firq_timer - 1'd1;
 
 
// ======================================
// IRQ Timer Register
// ======================================
    // Write a value > 1 to set the irq timer
    // Write 0 to clear it
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )
        irq_timer <= wb_wdata32[7:0];
    else if ( irq_timer > 8'd1 )
        irq_timer <= irq_timer - 1'd1;
 
 
// ======================================
// Random Number Generator Register
// ======================================
// Write a value > 1 to set the irq timer
// Write 0 to clear it
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= wb_wdata32[7:0];
 
    // generate a new random number on every read access
    else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )
        random_num <= { random_num[3]^random_num[1],
                        random_num[0]^random_num[5],
                        ~random_num[7]^random_num[4],
                        ~random_num[2],
                        random_num[6],
                        random_num[4]^~random_num[3],
                        random_num[7]^~random_num[1],
                        random_num[7]
                      };
    end
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_reg <= wb_wdata32;
 
 
// ======================================
// Test Status Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
        test_status_set <= 1'd1;
 
 
// ======================================
// Cycles counter
// ======================================
always @( posedge i_clk )
    cycles_reg <= cycles_reg + 1'd1;
 
 
// ======================================
// Memory Configuration Register Write
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )
        mem_ctrl_reg <= wb_wdata32[0];
 
 
// ======================================
// Test LEDs
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
        led_reg <= wb_wdata32[3:0];
 
 
// ======================================
// PHY Reset Register
// ======================================
always @( posedge i_clk )
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
        phy_rst_reg <= wb_wdata32[0];
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
// UART in system
 
//synopsys translate_off
always @( posedge i_clk )
    begin
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )
        tb_uart_control_reg <= wb_wdata32[1:0];
 
    if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )
        begin
        tb_uart_txd_reg   <= wb_wdata32[7:0];
        tb_uart_push      <= !tb_uart_push;
        end
    end
//synopsys translate_on
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Test Module //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Contains a random number generator and a couple of timers //`
10			`// that connect to interrupt lines. Used for testing the //`
11			`// ssytem. //`
12			`// //`
13			`// Author(s): //`
14			`// - Conor Santifort, csantifort.amber@gmail.com //`
15			`// //`
16			`//////////////////////////////////////////////////////////////////`
17			`// //`
18			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
19			`// //`
20			`// This source file may be used and distributed without //`
21			`// restriction provided that this copyright statement is not //`
22			`// removed from the file and that any derivative work contains //`
23			`// the original copyright notice and the associated disclaimer. //`
24			`// //`
25			`// This source file is free software; you can redistribute it //`
26			`// and/or modify it under the terms of the GNU Lesser General //`
27			`// Public License as published by the Free Software Foundation; //`
28			`// either version 2.1 of the License, or (at your option) any //`
29			`// later version. //`
30			`// //`
31			`// This source is distributed in the hope that it will be //`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
34			`// PURPOSE. See the GNU Lesser General Public License for more //`
35			`// details. //`
36			`// //`
37			`// You should have received a copy of the GNU Lesser General //`
38			`// Public License along with this source; if not, download it //`
39			`// from http://www.opencores.org/lgpl.shtml //`
40			`// //`
41			`//////////////////////////////////////////////////////////////////`
42
43
44	35	csantifort	`module test_module #(`
45			`parameter WB_DWIDTH = 32,`
46			`parameter WB_SWIDTH = 4`
47			`)(`
48	2	csantifort	`input i_clk,`
49
50			`output o_irq,`
51			`output o_firq,`
52	11	csantifort	`output o_mem_ctrl, // 0=128MB, 1=32MB`
53	2	csantifort	`input [31:0] i_wb_adr,`
54	35	csantifort	`input [WB_SWIDTH-1:0] i_wb_sel,`
55	2	csantifort	`input i_wb_we,`
56	35	csantifort	`output [WB_DWIDTH-1:0] o_wb_dat,`
57			`input [WB_DWIDTH-1:0] i_wb_dat,`
58	2	csantifort	`input i_wb_cyc,`
59			`input i_wb_stb,`
60			`output o_wb_ack,`
61	61	csantifort	`output o_wb_err,`
62			`output [3:0] o_led,`
63			`output o_phy_rst_n`
64	2	csantifort
65			`);`
66
67	82	csantifort	`include "register_addresses.vh"
68	2	csantifort
69
70			`reg [7:0] firq_timer = 'd0;`
71			`reg [7:0] irq_timer = 'd0;`
72			`reg [7:0] random_num = 8'hf3;`
73
74			`//synopsys translate_off`
75			`reg [1:0] tb_uart_control_reg = 'd0;`
76			`reg [1:0] tb_uart_status_reg = 'd0;`
77			`reg tb_uart_push = 'd0;`
78			`reg [7:0] tb_uart_txd_reg = 'd0;`
79			`//synopsys translate_on`
80
81	11	csantifort	`reg [2:0] sim_ctrl_reg = 'd0; // 0 = fpga, other values for simulations`
82			`reg mem_ctrl_reg = 'd0; // 0 = 128MB, 1 = 32MB main memory`
83	2	csantifort	`reg [31:0] test_status_reg = 'd0;`
84			`reg test_status_set = 'd0; // used to terminate tests`
85	32	csantifort	`reg [31:0] cycles_reg = 'd0;`
86	2	csantifort
87			`wire wb_start_write;`
88			`wire wb_start_read;`
89			`reg wb_start_read_d1 = 'd0;`
90	35	csantifort	`reg [31:0] wb_rdata32 = 'd0;`
91			`wire [31:0] wb_wdata32;`
92	2	csantifort
93	61	csantifort	`reg [3:0] led_reg = 'd0;`
94			`reg phy_rst_reg = 'd0;`
95
96
97	2	csantifort	`// Can't start a write while a read is completing. The ack for the read cycle`
98			`// needs to be sent first`
99			`assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;`
100			`assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;`
101
102			`always @( posedge i_clk )`
103			`wb_start_read_d1 <= wb_start_read;`
104
105	61	csantifort	`assign o_wb_ack = i_wb_stb && ( wb_start_write \|\| wb_start_read_d1 );`
106			`assign o_wb_err = 1'd0;`
107			`assign o_mem_ctrl = mem_ctrl_reg;`
108			`assign o_led = led_reg;`
109			`assign o_phy_rst_n = phy_rst_reg;`
110	2	csantifort
111	35	csantifort	`generate`
112			`if (WB_DWIDTH == 128)`
113			`begin : wb128`
114			`assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :`
115			`i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :`
116			`i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :`
117			`i_wb_dat[ 31: 0] ;`
118
119			`assign o_wb_dat = {4{wb_rdata32}};`
120			`end`
121			`else`
122			`begin : wb32`
123			`assign wb_wdata32 = i_wb_dat;`
124			`assign o_wb_dat = wb_rdata32;`
125			`end`
126			`endgenerate`
127
128	61	csantifort
129	2	csantifort	`// ========================================================`
130			`// Register Reads`
131			`// ========================================================`
132			`always @( posedge i_clk )`
133			`if ( wb_start_read )`
134			`case ( i_wb_adr[15:0] )`
135	35	csantifort	`AMBER_TEST_STATUS: wb_rdata32 <= test_status_reg;`
136			`AMBER_TEST_FIRQ_TIMER: wb_rdata32 <= {24'd0, firq_timer};`
137			`AMBER_TEST_IRQ_TIMER: wb_rdata32 <= {24'd0, irq_timer};`
138			`AMBER_TEST_RANDOM_NUM: wb_rdata32 <= {24'd0, random_num};`
139	2	csantifort
140			`/* Allow access to the random register over`
141			`a 16-word address range to load a series`
142			`of random numbers using lmd instruction. */`
143	35	csantifort	`AMBER_TEST_RANDOM_NUM00: wb_rdata32 <= {24'd0, random_num};`
144			`AMBER_TEST_RANDOM_NUM01: wb_rdata32 <= {24'd0, random_num};`
145			`AMBER_TEST_RANDOM_NUM02: wb_rdata32 <= {24'd0, random_num};`
146			`AMBER_TEST_RANDOM_NUM03: wb_rdata32 <= {24'd0, random_num};`
147			`AMBER_TEST_RANDOM_NUM04: wb_rdata32 <= {24'd0, random_num};`
148			`AMBER_TEST_RANDOM_NUM05: wb_rdata32 <= {24'd0, random_num};`
149			`AMBER_TEST_RANDOM_NUM06: wb_rdata32 <= {24'd0, random_num};`
150			`AMBER_TEST_RANDOM_NUM07: wb_rdata32 <= {24'd0, random_num};`
151			`AMBER_TEST_RANDOM_NUM08: wb_rdata32 <= {24'd0, random_num};`
152			`AMBER_TEST_RANDOM_NUM09: wb_rdata32 <= {24'd0, random_num};`
153			`AMBER_TEST_RANDOM_NUM10: wb_rdata32 <= {24'd0, random_num};`
154			`AMBER_TEST_RANDOM_NUM11: wb_rdata32 <= {24'd0, random_num};`
155			`AMBER_TEST_RANDOM_NUM12: wb_rdata32 <= {24'd0, random_num};`
156			`AMBER_TEST_RANDOM_NUM13: wb_rdata32 <= {24'd0, random_num};`
157			`AMBER_TEST_RANDOM_NUM14: wb_rdata32 <= {24'd0, random_num};`
158			`AMBER_TEST_RANDOM_NUM15: wb_rdata32 <= {24'd0, random_num};`
159	2	csantifort
160			`//synopsys translate_off`
161	35	csantifort	`AMBER_TEST_UART_CONTROL: wb_rdata32 <= {30'd0, tb_uart_control_reg};`
162			`AMBER_TEST_UART_STATUS: wb_rdata32 <= {30'd0, tb_uart_status_reg};`
163			`AMBER_TEST_UART_TXD: wb_rdata32 <= {24'd0, tb_uart_txd_reg};`
164	2	csantifort	`//synopsys translate_on`
165
166	35	csantifort	`AMBER_TEST_SIM_CTRL: wb_rdata32 <= {29'd0, sim_ctrl_reg};`
167			`AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};`
168	32	csantifort
169	35	csantifort	`AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;`
170	61	csantifort	`AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};`
171			`AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};`
172	35	csantifort	`default: wb_rdata32 <= 32'haabbccdd;`
173	2	csantifort
174			`endcase`
175
176
177			`// ======================================`
178			`// Simulation bit`
179			`// ======================================`
180
181			`// This register bit is a 1 in simulation but a 0 in the real fpga`
182			`// Used by software to tell the difference`
183			`//synopsys translate_off`
184
185			`ifndef AMBER_SIM_CTRL
186			`define AMBER_SIM_CTRL 0
187			`endif
188
189			`always @( posedge i_clk )`
190			`begin`
191			`// Value reads as 1 in simulation, and zero in the FPGA`
192	11	csantifort	sim_ctrl_reg <= 3'd `AMBER_SIM_CTRL ;
193	2	csantifort	`end`
194			`//synopsys translate_on`
195
196
197			`// ======================================`
198			`// Interrupts`
199			`// ======================================`
200			`assign o_irq = irq_timer == 8'd1;`
201			`assign o_firq = firq_timer == 8'd1;`
202
203
204			`// ======================================`
205			`// FIRQ Timer Register`
206			`// ======================================`
207			`// Write a value > 1 to set the firq timer`
208			`// Write 0 to clear it`
209			`always @( posedge i_clk )`
210			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_FIRQ_TIMER )`
211	35	csantifort	`firq_timer <= wb_wdata32[7:0];`
212	2	csantifort	`else if ( firq_timer > 8'd1 )`
213			`firq_timer <= firq_timer - 1'd1;`
214
215
216			`// ======================================`
217			`// IRQ Timer Register`
218			`// ======================================`
219			`// Write a value > 1 to set the irq timer`
220			`// Write 0 to clear it`
221			`always @( posedge i_clk )`
222			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_IRQ_TIMER )`
223	35	csantifort	`irq_timer <= wb_wdata32[7:0];`
224	2	csantifort	`else if ( irq_timer > 8'd1 )`
225			`irq_timer <= irq_timer - 1'd1;`
226
227
228			`// ======================================`
229			`// Random Number Generator Register`
230			`// ======================================`
231			`// Write a value > 1 to set the irq timer`
232			`// Write 0 to clear it`
233			`always @( posedge i_clk )`
234			`begin`
235			`if ( wb_start_write && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
236	35	csantifort	`random_num <= wb_wdata32[7:0];`
237	2	csantifort
238			`// generate a new random number on every read access`
239			`else if ( wb_start_read && i_wb_adr[15:8] == AMBER_TEST_RANDOM_NUM[15:8] )`
240			`random_num <= { random_num[3]^random_num[1],`
241			`random_num[0]^random_num[5],`
242			`~random_num[7]^random_num[4],`
243			`~random_num[2],`
244			`random_num[6],`
245			`random_num[4]^~random_num[3],`
246			`random_num[7]^~random_num[1],`
247			`random_num[7]`
248			`};`
249			`end`
250
251
252			`// ======================================`
253			`// Test Status Write`
254			`// ======================================`
255			`always @( posedge i_clk )`
256			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
257	35	csantifort	`test_status_reg <= wb_wdata32;`
258	2	csantifort
259
260			`// ======================================`
261			`// Test Status Write`
262			`// ======================================`
263			`always @( posedge i_clk )`
264			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )`
265			`test_status_set <= 1'd1;`
266
267	61	csantifort
268	2	csantifort	`// ======================================`
269	32	csantifort	`// Cycles counter`
270			`// ======================================`
271			`always @( posedge i_clk )`
272			`cycles_reg <= cycles_reg + 1'd1;`
273	61	csantifort
274
275	32	csantifort	`// ======================================`
276	11	csantifort	`// Memory Configuration Register Write`
277			`// ======================================`
278			`always @( posedge i_clk )`
279			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_MEM_CTRL )`
280	35	csantifort	`mem_ctrl_reg <= wb_wdata32[0];`
281	11	csantifort
282
283			`// ======================================`
284	61	csantifort	`// Test LEDs`
285			`// ======================================`
286			`always @( posedge i_clk )`
287			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )`
288			`led_reg <= wb_wdata32[3:0];`
289
290
291			`// ======================================`
292			`// PHY Reset Register`
293			`// ======================================`
294			`always @( posedge i_clk )`
295			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )`
296			`phy_rst_reg <= wb_wdata32[0];`
297
298
299			`// ======================================`
300	2	csantifort	`// Test UART registers`
301			`// ======================================`
302			`// These control the testbench UART, not the real`
303			`// UART in system`
304
305			`//synopsys translate_off`
306			`always @( posedge i_clk )`
307			`begin`
308			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_CONTROL )`
309	35	csantifort	`tb_uart_control_reg <= wb_wdata32[1:0];`
310	2	csantifort
311			`if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_UART_TXD )`
312			`begin`
313	35	csantifort	`tb_uart_txd_reg <= wb_wdata32[7:0];`
314	2	csantifort	`tb_uart_push <= !tb_uart_push;`
315			`end`
316			`end`
317			`//synopsys translate_on`
318
319
320
321			`endmodule`
322

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