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1 2 csantifort
//////////////////////////////////////////////////////////////////
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//                                                              //
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//  Wishbone Arbiter                                            //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Arbitrates between two wishbone masters and 13 wishbone     //
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//  slave modules. The ethernet MAC wishbone master is given    //
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//  priority over the Amber core.                               //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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//////////////////////////////////////////////////////////////////
42
 
43 35 csantifort
// TODO add module to switch endianess of ethmac i/f
44 2 csantifort
 
45 35 csantifort
module wishbone_arbiter #(
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parameter WB_DWIDTH  = 32,
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parameter WB_SWIDTH  = 4
48
)(
49 2 csantifort
 
50 35 csantifort
input                       i_wb_clk,     // WISHBONE clock
51
 
52 2 csantifort
// WISHBONE master 0 - Amber
53 35 csantifort
input       [31:0]          i_m0_wb_adr,
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input       [WB_SWIDTH-1:0] i_m0_wb_sel,
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input                       i_m0_wb_we,
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output      [WB_DWIDTH-1:0] o_m0_wb_dat,
57
input       [WB_DWIDTH-1:0] i_m0_wb_dat,
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input                       i_m0_wb_cyc,
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input                       i_m0_wb_stb,
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output                      o_m0_wb_ack,
61
output                      o_m0_wb_err,
62 2 csantifort
 
63
 
64
// WISHBONE master 1 - Ethmac
65 35 csantifort
input       [31:0]          i_m1_wb_adr,
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input       [WB_SWIDTH-1:0] i_m1_wb_sel,
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input                       i_m1_wb_we,
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output      [WB_DWIDTH-1:0] o_m1_wb_dat,
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input       [WB_DWIDTH-1:0] i_m1_wb_dat,
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input                       i_m1_wb_cyc,
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input                       i_m1_wb_stb,
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output                      o_m1_wb_ack,
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output                      o_m1_wb_err,
74 2 csantifort
 
75
 
76
// WISHBONE slave 0 - Ethmac
77 35 csantifort
output      [31:0]          o_s0_wb_adr,
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output      [WB_SWIDTH-1:0] o_s0_wb_sel,
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output                      o_s0_wb_we,
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input       [WB_DWIDTH-1:0] i_s0_wb_dat,
81
output      [WB_DWIDTH-1:0] o_s0_wb_dat,
82
output                      o_s0_wb_cyc,
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output                      o_s0_wb_stb,
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input                       i_s0_wb_ack,
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input                       i_s0_wb_err,
86 2 csantifort
 
87
 
88
// WISHBONE slave 1 - Boot Memory
89 35 csantifort
output      [31:0]          o_s1_wb_adr,
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output      [WB_SWIDTH-1:0] o_s1_wb_sel,
91
output                      o_s1_wb_we,
92
input       [WB_DWIDTH-1:0] i_s1_wb_dat,
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output      [WB_DWIDTH-1:0] o_s1_wb_dat,
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output                      o_s1_wb_cyc,
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output                      o_s1_wb_stb,
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input                       i_s1_wb_ack,
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input                       i_s1_wb_err,
98 2 csantifort
 
99
 
100
// WISHBONE slave 2 - Main Memory
101 35 csantifort
output      [31:0]          o_s2_wb_adr,
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output      [WB_SWIDTH-1:0] o_s2_wb_sel,
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output                      o_s2_wb_we,
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input       [WB_DWIDTH-1:0] i_s2_wb_dat,
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output      [WB_DWIDTH-1:0] o_s2_wb_dat,
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output                      o_s2_wb_cyc,
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output                      o_s2_wb_stb,
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input                       i_s2_wb_ack,
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input                       i_s2_wb_err,
110 2 csantifort
 
111
 
112
// WISHBONE slave 3 - UART 0
113 35 csantifort
output      [31:0]          o_s3_wb_adr,
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output      [WB_SWIDTH-1:0] o_s3_wb_sel,
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output                      o_s3_wb_we,
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input       [WB_DWIDTH-1:0] i_s3_wb_dat,
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output      [WB_DWIDTH-1:0] o_s3_wb_dat,
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output                      o_s3_wb_cyc,
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output                      o_s3_wb_stb,
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input                       i_s3_wb_ack,
121
input                       i_s3_wb_err,
122 2 csantifort
 
123
 
124
// WISHBONE slave 4 - UART 1
125 35 csantifort
output      [31:0]          o_s4_wb_adr,
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output      [WB_SWIDTH-1:0] o_s4_wb_sel,
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output                      o_s4_wb_we,
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input       [WB_DWIDTH-1:0] i_s4_wb_dat,
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output      [WB_DWIDTH-1:0] o_s4_wb_dat,
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output                      o_s4_wb_cyc,
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output                      o_s4_wb_stb,
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input                       i_s4_wb_ack,
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input                       i_s4_wb_err,
134 2 csantifort
 
135
 
136
// WISHBONE slave 5 - Test Module
137 35 csantifort
output      [31:0]          o_s5_wb_adr,
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output      [WB_SWIDTH-1:0] o_s5_wb_sel,
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output                      o_s5_wb_we,
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input       [WB_DWIDTH-1:0] i_s5_wb_dat,
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output      [WB_DWIDTH-1:0] o_s5_wb_dat,
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output                      o_s5_wb_cyc,
143
output                      o_s5_wb_stb,
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input                       i_s5_wb_ack,
145
input                       i_s5_wb_err,
146 2 csantifort
 
147
 
148
// WISHBONE slave 6 - Timer Module
149 35 csantifort
output      [31:0]          o_s6_wb_adr,
150
output      [WB_SWIDTH-1:0] o_s6_wb_sel,
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output                      o_s6_wb_we,
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input       [WB_DWIDTH-1:0] i_s6_wb_dat,
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output      [WB_DWIDTH-1:0] o_s6_wb_dat,
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output                      o_s6_wb_cyc,
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output                      o_s6_wb_stb,
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input                       i_s6_wb_ack,
157
input                       i_s6_wb_err,
158 2 csantifort
 
159
 
160
 // WISHBONE slave 7 - Interrupt Controller
161 35 csantifort
output      [31:0]          o_s7_wb_adr,
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output      [WB_SWIDTH-1:0] o_s7_wb_sel,
163
output                      o_s7_wb_we,
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input       [WB_DWIDTH-1:0] i_s7_wb_dat,
165
output      [WB_DWIDTH-1:0] o_s7_wb_dat,
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output                      o_s7_wb_cyc,
167
output                      o_s7_wb_stb,
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input                       i_s7_wb_ack,
169
input                       i_s7_wb_err
170 2 csantifort
);
171
 
172
`include "memory_configuration.v"
173 35 csantifort
reg         m0_wb_hold_r = 'd0;
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reg         m1_wb_hold_r = 'd0;
175
// wire        m0_in_cycle;
176
// wire        m1_in_cycle;
177 2 csantifort
wire        current_master;
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reg         current_master_r = 'd0;
179
wire        next_master;
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wire        select_master;
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wire [3:0]  current_slave;
182
 
183 35 csantifort
wire [31:0]             master_adr;
184
wire [WB_SWIDTH-1:0]    master_sel;
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wire                    master_we;
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wire [WB_DWIDTH-1:0]    master_wdat;
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wire                    master_cyc;
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wire                    master_stb;
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wire [WB_DWIDTH-1:0]    master_rdat;
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wire                    master_ack;
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wire                    master_err;
192 2 csantifort
 
193 35 csantifort
 
194 2 csantifort
// Arbitrate between m0 and m1. Ethmac (m0) always gets priority
195
assign next_master    = i_m0_wb_cyc ? 1'd0 : 1'd1;
196
 
197
// Use cyc signal for arbitration so block accesses are not split up
198 35 csantifort
// assign m0_in_cycle    = m0_wb_hold_r && !master_ack;
199
// assign m1_in_cycle    = m1_wb_hold_r && !master_ack;
200 2 csantifort
 
201
// only select a new bus master when the current bus master
202 35 csantifort
// daccess ends
203
assign select_master  = current_master_r ? !m1_wb_hold_r : !m0_wb_hold_r;
204 2 csantifort
assign current_master = select_master ? next_master : current_master_r;
205
 
206
 
207
always @( posedge i_wb_clk )
208
    begin
209
    current_master_r    <= current_master;
210 35 csantifort
    m0_wb_hold_r        <= i_m0_wb_stb && !o_m0_wb_ack;
211
    m1_wb_hold_r        <= i_m1_wb_stb && !o_m1_wb_ack;
212 2 csantifort
    end
213
 
214
 
215
// Arbitrate between slaves
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assign current_slave = in_ethmac   ( master_adr ) ? 4'd0  :  // Ethmac
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                       in_boot_mem ( master_adr ) ? 4'd1  :  // Boot memory
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                       in_main_mem ( master_adr ) ? 4'd2  :  // Main memory
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                       in_uart0    ( master_adr ) ? 4'd3  :  // UART 0
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                       in_uart1    ( master_adr ) ? 4'd4  :  // UART 1
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                       in_test     ( master_adr ) ? 4'd5  :  // Test Module
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                       in_tm       ( master_adr ) ? 4'd6  :  // Timer Module
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                       in_ic       ( master_adr ) ? 4'd7  :  // Interrupt Controller
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                                                    4'd2  ;  // default to main memory
225
 
226
 
227
assign master_adr   = current_master ? i_m1_wb_adr : i_m0_wb_adr ;
228 35 csantifort
assign master_sel   = current_master ? i_m1_wb_sel : i_m0_wb_sel ;
229
assign master_wdat  = current_master ? i_m1_wb_dat : i_m0_wb_dat ;
230 2 csantifort
assign master_we    = current_master ? i_m1_wb_we  : i_m0_wb_we  ;
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assign master_cyc   = current_master ? i_m1_wb_cyc : i_m0_wb_cyc ;
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assign master_stb   = current_master ? i_m1_wb_stb : i_m0_wb_stb ;
233
 
234
 
235
// Ethmac Slave outputs
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assign o_s0_wb_adr  = master_adr;
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assign o_s0_wb_dat  = master_wdat;
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assign o_s0_wb_sel  = master_sel;
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assign o_s0_wb_we   = current_slave == 4'd0 ? master_we  : 1'd0;
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assign o_s0_wb_cyc  = current_slave == 4'd0 ? master_cyc : 1'd0;
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assign o_s0_wb_stb  = current_slave == 4'd0 ? master_stb : 1'd0;
242
 
243
// Boot Memory outputs
244
assign o_s1_wb_adr  = master_adr;
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assign o_s1_wb_dat  = master_wdat;
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assign o_s1_wb_sel  = master_sel;
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assign o_s1_wb_we   = current_slave == 4'd1 ? master_we  : 1'd0;
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assign o_s1_wb_cyc  = current_slave == 4'd1 ? master_cyc : 1'd0;
249
assign o_s1_wb_stb  = current_slave == 4'd1 ? master_stb : 1'd0;
250
 
251
// Main Memory Outputs
252
assign o_s2_wb_adr  = master_adr;
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assign o_s2_wb_dat  = master_wdat;
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assign o_s2_wb_sel  = master_sel;
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assign o_s2_wb_we   = current_slave == 4'd2 ? master_we  : 1'd0;
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assign o_s2_wb_cyc  = current_slave == 4'd2 ? master_cyc : 1'd0;
257
assign o_s2_wb_stb  = current_slave == 4'd2 ? master_stb : 1'd0;
258
 
259
// UART0 Outputs
260
assign o_s3_wb_adr  = master_adr;
261
assign o_s3_wb_dat  = master_wdat;
262
assign o_s3_wb_sel  = master_sel;
263
assign o_s3_wb_we   = current_slave == 4'd3 ? master_we  : 1'd0;
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assign o_s3_wb_cyc  = current_slave == 4'd3 ? master_cyc : 1'd0;
265
assign o_s3_wb_stb  = current_slave == 4'd3 ? master_stb : 1'd0;
266
 
267
// UART1 Outputs
268
assign o_s4_wb_adr  = master_adr;
269
assign o_s4_wb_dat  = master_wdat;
270
assign o_s4_wb_sel  = master_sel;
271
assign o_s4_wb_we   = current_slave == 4'd4 ? master_we  : 1'd0;
272
assign o_s4_wb_cyc  = current_slave == 4'd4 ? master_cyc : 1'd0;
273
assign o_s4_wb_stb  = current_slave == 4'd4 ? master_stb : 1'd0;
274
 
275
// Test Module Outputs
276
assign o_s5_wb_adr  = master_adr;
277
assign o_s5_wb_dat  = master_wdat;
278
assign o_s5_wb_sel  = master_sel;
279
assign o_s5_wb_we   = current_slave == 5'd5 ? master_we  : 1'd0;
280
assign o_s5_wb_cyc  = current_slave == 5'd5 ? master_cyc : 1'd0;
281
assign o_s5_wb_stb  = current_slave == 5'd5 ? master_stb : 1'd0;
282
 
283
// Timers Outputs
284
assign o_s6_wb_adr  = master_adr;
285
assign o_s6_wb_dat  = master_wdat;
286
assign o_s6_wb_sel  = master_sel;
287
assign o_s6_wb_we   = current_slave == 6'd6 ? master_we  : 1'd0;
288
assign o_s6_wb_cyc  = current_slave == 6'd6 ? master_cyc : 1'd0;
289
assign o_s6_wb_stb  = current_slave == 6'd6 ? master_stb : 1'd0;
290
 
291
// Interrupt Controller
292
assign o_s7_wb_adr  = master_adr;
293
assign o_s7_wb_dat  = master_wdat;
294
assign o_s7_wb_sel  = master_sel;
295
assign o_s7_wb_we   = current_slave == 4'd7 ? master_we  : 1'd0;
296
assign o_s7_wb_cyc  = current_slave == 4'd7 ? master_cyc : 1'd0;
297
assign o_s7_wb_stb  = current_slave == 4'd7 ? master_stb : 1'd0;
298
 
299
 
300
// Master Outputs
301
assign master_rdat  = current_slave == 4'd0  ? i_s0_wb_dat  :
302
                      current_slave == 4'd1  ? i_s1_wb_dat  :
303
                      current_slave == 4'd2  ? i_s2_wb_dat  :
304
                      current_slave == 4'd3  ? i_s3_wb_dat  :
305
                      current_slave == 4'd4  ? i_s4_wb_dat  :
306
                      current_slave == 4'd5  ? i_s5_wb_dat  :
307
                      current_slave == 4'd6  ? i_s6_wb_dat  :
308
                      current_slave == 4'd7  ? i_s7_wb_dat  :
309
                                               i_s2_wb_dat  ;
310
 
311
 
312
assign master_ack   = current_slave == 4'd0  ? i_s0_wb_ack  :
313
                      current_slave == 4'd1  ? i_s1_wb_ack  :
314
                      current_slave == 4'd2  ? i_s2_wb_ack  :
315
                      current_slave == 4'd3  ? i_s3_wb_ack  :
316
                      current_slave == 4'd4  ? i_s4_wb_ack  :
317
                      current_slave == 4'd5  ? i_s5_wb_ack  :
318
                      current_slave == 4'd6  ? i_s6_wb_ack  :
319
                      current_slave == 4'd7  ? i_s7_wb_ack  :
320
                                               i_s2_wb_ack  ;
321
 
322
 
323
assign master_err   = current_slave == 4'd0  ? i_s0_wb_err  :
324
                      current_slave == 4'd1  ? i_s1_wb_err  :
325
                      current_slave == 4'd2  ? i_s2_wb_err  :
326
                      current_slave == 4'd3  ? i_s3_wb_err  :
327
                      current_slave == 4'd4  ? i_s4_wb_err  :
328
                      current_slave == 4'd5  ? i_s5_wb_err  :
329
                      current_slave == 4'd6  ? i_s6_wb_err  :
330
                      current_slave == 4'd7  ? i_s7_wb_err  :
331
                                               i_s2_wb_err  ;
332
 
333
 
334
// Ethmac Master Outputs
335 35 csantifort
assign o_m0_wb_dat  = master_rdat;
336 2 csantifort
assign o_m0_wb_ack  = current_master  ? 1'd0 : master_ack ;
337
assign o_m0_wb_err  = current_master  ? 1'd0 : master_err ;
338
 
339
// Amber Master Outputs
340
assign o_m1_wb_dat  = master_rdat;
341
assign o_m1_wb_ack  = current_master  ?  master_ack : 1'd0 ;
342
assign o_m1_wb_err  = current_master  ?  master_err : 1'd0 ;
343
 
344
endmodule
345
 

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