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//////////////////////////////////////////////////////////////////
//                                                              //
//  Top Level testbench                                         //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Instantiates the system, ddr3 memory model and tb_uart      //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
`timescale  1 ps / 1 ps
 
`include "system_config_defines.v"
`include "global_defines.v"
 
 
module tb();
 
`include "debug_functions.v"
 
reg                     sysrst;
`ifdef XILINX_VIRTEX6_FPGA
reg                     clk_533mhz;
`endif
reg                     clk_200mhz;
reg                     clk_25mhz;
reg [31:0]              clk_count;
 
integer                 log_file;
 
`ifdef AMBER_LOAD_MAIN_MEM
integer                 main_mem_file;
reg     [31:0]          main_mem_file_address;
reg     [31:0]          main_mem_file_data;
reg     [127:0]         main_mem_file_data_128;
integer                 main_mem_line_count;
reg     [22:0]          mm_ddr3_addr;
`endif
 
integer                 boot_mem_file;
reg     [31:0]          boot_mem_file_address;
reg     [31:0]          boot_mem_file_data;
integer                 boot_mem_line_count;
integer                 fgets_return;
reg     [120*8-1:0]     line;
reg     [120*8-1:0]     aligned_line;
 
wire [12:0]             ddr3_addr;
wire [2:0]              ddr3_ba;
wire                    ddr3_ck_p;
wire                    ddr3_ck_n;
wire [15:0]             ddr3_dq;
wire [1:0]              ddr3_dqs_p;
wire [1:0]              ddr3_dqs_n;
wire [1:0]              ddr3_dm;
wire                    ddr3_ras_n;
wire                    ddr3_cas_n;
wire                    ddr3_we_n;
wire                    ddr3_cke;
wire                    ddr3_odt;
wire                    ddr3_reset_n;
 
 
`ifdef XILINX_SPARTAN6_FPGA
wire                    mcb3_rzq;
wire                    mcb3_zio;
`endif
 
tri1                    md_pad_io;
 
wire                    uart0_cts;
wire                    uart0_rx;
wire                    uart0_rts;
wire                    uart0_tx;
 
 
// ======================================
// Instantiate FPGA
// ======================================
system u_system (
    // Clocks and resets
    .brd_rst            ( sysrst            ),
    .brd_clk_p          ( clk_200mhz        ),
    .brd_clk_n          ( ~clk_200mhz       ),
 
    `ifdef XILINX_VIRTEX6_FPGA
    .sys_clk_p          ( clk_533mhz        ),
    .sys_clk_n          ( ~clk_533mhz       ),
    `endif
 
    // UART 0 signals
    .o_uart0_cts        ( uart0_cts         ),
    .o_uart0_rx         ( uart0_rx          ),
    .i_uart0_rts        ( uart0_rts         ),
    .i_uart0_tx         ( uart0_tx          ),
 
    // DDR3 signals
    .ddr3_dq            ( ddr3_dq           ),
    .ddr3_addr          ( ddr3_addr         ),
    .ddr3_ba            ( ddr3_ba           ),
    .ddr3_ras_n         ( ddr3_ras_n        ),
    .ddr3_cas_n         ( ddr3_cas_n        ),
    .ddr3_we_n          ( ddr3_we_n         ),
    .ddr3_odt           ( ddr3_odt          ),
    .ddr3_reset_n       ( ddr3_reset_n      ),
    .ddr3_cke           ( ddr3_cke          ),
    .ddr3_dm            ( ddr3_dm           ),
    .ddr3_dqs_p         ( ddr3_dqs_p        ),
    .ddr3_dqs_n         ( ddr3_dqs_n        ),
    .ddr3_ck_p          ( ddr3_ck_p         ),
    .ddr3_ck_n          ( ddr3_ck_n         ),
    `ifdef XILINX_VIRTEX6_FPGA
    .ddr3_cs_n          ( ddr3_cs_n         ),
    `endif
    `ifdef XILINX_SPARTAN6_FPGA
    .mcb3_rzq           ( mcb3_rzq          ),
    .mcb3_zio           ( mcb3_zio          ),
    `endif
 
    // Ethernet MII signals
    .mtx_clk_pad_i      ( clk_25mhz         ),
    .mtxd_pad_o         (                   ),
    .mtxen_pad_o        (                   ),
    .mtxerr_pad_o       (                   ),
    .mrx_clk_pad_i      ( clk_25mhz         ),
    .mrxd_pad_i         ( 4'd0              ),
    .mrxdv_pad_i        ( 1'd0              ),
    .mrxerr_pad_i       ( 1'd0              ),
    .mcoll_pad_i        ( 1'd0              ),
    .mcrs_pad_i         ( 1'd0              ),  // Assert Carrier Sense from PHY
    .phy_reset_n        (                   ),
 
    // Ethernet MD signals
    .md_pad_io          ( md_pad_io         ),
    .mdc_pad_o          (                   )
 
);
 
 
// ======================================
// Instantiate DDR3 Memory Model
// ======================================
`ifdef XILINX_FPGA
    ddr3_model_c3 #(
          .DEBUG      ( 0                   )   // Set to 1 to enable debug messages
          )
    u_ddr3_model (
          .ck         ( ddr3_ck_p           ),
          .ck_n       ( ddr3_ck_n           ),
          .cke        ( ddr3_cke            ),
          `ifdef XILINX_VIRTEX6_FPGA
          .cs_n       ( ddr3_cs_n           ),
          `else
          .cs_n       ( 1'b0                ),
          `endif
          .ras_n      ( ddr3_ras_n          ),
          .cas_n      ( ddr3_cas_n          ),
          .we_n       ( ddr3_we_n           ),
          .dm_tdqs    ( ddr3_dm             ),
          .ba         ( ddr3_ba             ),
          .addr       ( {1'd0, ddr3_addr}   ),
          .dq         ( ddr3_dq             ),
          .dqs        ( ddr3_dqs_p          ),
          .dqs_n      ( ddr3_dqs_n          ),
          .tdqs_n     (                     ),
          .odt        ( ddr3_odt            ),
          .rst_n      ( ddr3_reset_n        )
          );
`endif
 
 
// ======================================
// Instantiate Testbench UART
// ======================================
tb_uart u_tb_uart (
    .i_uart_cts_n   ( uart0_cts ),          // Clear To Send
    .i_uart_rxd     ( uart0_rx  ),
    .o_uart_rts_n   ( uart0_rts ),          // Request to Send
    .o_uart_txd     ( uart0_tx  )
 
);
 
 
// ======================================
// Global module for xilinx hardware simulations
// ======================================
`ifdef XILINX_FPGA
    `define GLBL
    glbl glbl();
`endif
 
 
// ======================================
// Clock and Reset
// ======================================
 
// 200 MHz clock
initial
    begin
    clk_200mhz = 1'd0;
    // Time unit is pico-seconds
    forever #2500 clk_200mhz = ~clk_200mhz;
    end
 
 
`ifdef XILINX_VIRTEX6_FPGA
// 400 MHz clock
initial
    begin
    clk_533mhz = 1'd0;
    // Time unit is pico-seconds
    forever #938 clk_533mhz = ~clk_533mhz;
    end
`endif
 
 
// 25 MHz clock
initial
    begin
    clk_25mhz = 1'd0;
    forever #20000 clk_25mhz = ~clk_25mhz;
    end
 
initial
    begin
    sysrst = 1'd1;
    #15002500
    sysrst = 1'd0;
    end
 
 
// ======================================
// Counter of system clock ticks        
// ======================================
always @ ( posedge `U_SYSTEM.sys_clk )
    if ( `U_SYSTEM.sys_rst )
        clk_count <= 'd0;
    else
        clk_count <= clk_count + 1'd1;
 
 
 
// ======================================
// Test Name
// ======================================
initial
    begin
    $display("Test %s, log file %s",`AMBER_TEST_NAME, `AMBER_LOG_FILE);
    log_file = $fopen(`AMBER_LOG_FILE, "a");
    end
 
 
 
// ======================================
// Initialize Boot Memory
// ======================================
`ifndef XILINX_FPGA
    initial
        begin
        $display("Load boot memory from %s", `BOOT_MEM_FILE);
        boot_mem_line_count   = 0;
        boot_mem_file         = $fopen(`BOOT_MEM_FILE,    "r");
        if (boot_mem_file == 0)
            begin
            `TB_ERROR_MESSAGE
            $display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
            end
 
        if (boot_mem_file != 0)
            begin
            fgets_return = 1;
            while (fgets_return != 0)
                begin
                fgets_return        = $fgets(line, boot_mem_file);
                boot_mem_line_count = boot_mem_line_count + 1;
                aligned_line        = align_line(line);
 
                // if the line does not start with a comment
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
                    begin
                    // check that line doesnt start with a '@' or a blank
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
                                 `BOOT_MEM_FILE, boot_mem_line_count, aligned_line[118*8-1:117*8]);
                        `TB_ERROR_MESSAGE
                        end
 
                    if (aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        boot_mem_file_address  =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
                        boot_mem_file_data     =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
 
                        tb.u_system.u_boot_mem.u_mem.mem [boot_mem_file_address[12:2]] = boot_mem_file_data;
 
                        `ifdef AMBER_LOAD_MEM_DEBUG
                            $display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
                                        boot_mem_file_address, boot_mem_file_data);
                        `endif
                        end
                    end
                end
 
            $display("Read in %1d lines", boot_mem_line_count);
            end
        end
 
`endif
 
 
// ======================================
// Initialize Main Memory
// ======================================
`ifdef AMBER_LOAD_MAIN_MEM
    initial
        begin
        $display("Load main memory from %s", `MAIN_MEM_FILE);
        `ifdef XILINX_FPGA
        // Wait for DDR3 initialization to complete
        $display("Wait for DDR3 initialization to complete before loading main memory");
        #70000000
        $display("Done waiting at %d ticks", `U_TB.clk_count);
        `endif
        main_mem_file   = $fopen(`MAIN_MEM_FILE, "r");
 
        // Read RAM File
        main_mem_line_count   = 0;
 
        if (main_mem_file == 0)
            begin
            $display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
            `TB_ERROR_MESSAGE
            end
 
 
        if (main_mem_file != 0)
            begin
            fgets_return = 1;
            while (fgets_return != 0)
                begin
                fgets_return        = $fgets(line, main_mem_file);
                main_mem_line_count = main_mem_line_count + 1;
                aligned_line        = align_line(line);
 
                // if the line does not start with a comment
                if (aligned_line[120*8-1:118*8] != 16'h2f2f)
                    begin
                    // check that line doesnt start with a '@' or a blank
                    if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        $display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
                                 `MAIN_MEM_FILE, main_mem_line_count, aligned_line[118*8-1:117*8]);
                        `TB_ERROR_MESSAGE
                        end
 
                    if (aligned_line[120*8-1:119*8] != 8'h00)
                        begin
                        main_mem_file_address =   hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
                        main_mem_file_data    =   hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
 
                        `ifdef XILINX_FPGA
                            mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
 
                            main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
                            tb.u_ddr3_model.memory [mm_ddr3_addr] =
                                    insert_32_into_128 ( main_mem_file_address[3:2],
                                                         main_mem_file_data_128,
                                                         main_mem_file_data );
 
                            `ifdef AMBER_LOAD_MEM_DEBUG
                                main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
                                $display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
                                          main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
                            `endif
 
                        `else
                            // Fast simulation model of main memory
 
                            // U_RAM - Can either point to simple or Xilinx DDR3 model. 
                            // Set in hierarchy_defines.v
 
                            main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
                            `U_RAM [main_mem_file_address[31:4]] =
                                insert_32_into_128 ( main_mem_file_address[3:2],
                                                     main_mem_file_data_128,
                                                     main_mem_file_data );
 
                            `ifdef AMBER_LOAD_MEM_DEBUG
                                $display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",
                                           main_mem_file_address, main_mem_file_data);
                            `endif
 
                        `endif
 
                        end
                    end
                end
 
            $display("Read in %1d lines", main_mem_line_count);
            end
        end
`endif
 
 
dumpvcd u_dumpvcd();
 
// ======================================
// Terminate Test  
// ======================================
`include "amber_localparams.v"
`include "amber_functions.v"
 
reg testfail;
wire        test_status_set;
wire [31:0] test_status_reg;
 
initial
    testfail = 1'd0;
 
assign test_status_set = `U_TEST_MODULE.test_status_set;
assign test_status_reg = `U_TEST_MODULE.test_status_reg;
 
always @*
        begin
        if ( test_status_set || testfail )
            begin
            if ( test_status_reg == 32'd17 && !testfail )
                begin
                display_registers;
                $display("++++++++++++++++++++");
                $write("Passed %s\n", `AMBER_TEST_NAME);
                $display("++++++++++++++++++++");
                $fwrite(`U_TB.log_file,"Passed %s\n", `AMBER_TEST_NAME);
                $finish;
                end
            else
                begin
                display_registers;
                if ( testfail )
                    begin
                    $display("++++++++++++++++++++");
                    $write("Failed %s - assertion error\n", `AMBER_TEST_NAME);
                    $display("++++++++++++++++++++");
                    $fwrite(`U_TB.log_file,"Failed %s - assertion error\n", `AMBER_TEST_NAME);
                    $finish;
                    end
                else
                    begin
                    $display("++++++++++++++++++++");
                    if (test_status_reg >= 32'h8000)
                        $write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
                    else
                        $write("Failed %s - with error %1d\n", `AMBER_TEST_NAME, test_status_reg);
                    $display("++++++++++++++++++++");
                    if (test_status_reg >= 32'h8000)
                        $fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
                    else
                        $fwrite(`U_TB.log_file,"Failed %s - with error %1d\n", `AMBER_TEST_NAME, test_status_reg);
                    $finish;
                    end
                end
            end
        end
 
 
 
// ======================================
// Tasks
// ======================================
task display_registers;
begin
    $display("");
    $display("----------------------------------------------------------------------------");
    $display("Amber Core");
 
    case (`U_EXECUTE.status_bits_mode)
        FIRQ:    $display("         User       > FIRQ         IRQ          SVC");
        IRQ:     $display("         User         FIRQ       > IRQ          SVC");
        SVC:     $display("         User         FIRQ         IRQ        > SVC");
        default: $display("       > User         FIRQ         IRQ          SVC");
    endcase
 
    $display("r0       0x%08x", `U_REGISTER_BANK.r0);
    $display("r1       0x%08x", `U_REGISTER_BANK.r1);
    $display("r2       0x%08x", `U_REGISTER_BANK.r2);
    $display("r3       0x%08x", `U_REGISTER_BANK.r3);
    $display("r4       0x%08x", `U_REGISTER_BANK.r4);
    $display("r5       0x%08x", `U_REGISTER_BANK.r5);
    $display("r6       0x%08x", `U_REGISTER_BANK.r6);
    $display("r7       0x%08x", `U_REGISTER_BANK.r7);
    $display("r8       0x%08x   0x%08x ", `U_REGISTER_BANK.r8,  `U_REGISTER_BANK.r8_firq);
    $display("r9       0x%08x   0x%08x ", `U_REGISTER_BANK.r9,  `U_REGISTER_BANK.r9_firq);
    $display("r10      0x%08x   0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
    $display("r11      0x%08x   0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
    $display("r12      0x%08x   0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
 
    $display("r13      0x%08x   0x%08x   0x%08x   0x%08x",
                                               `U_REGISTER_BANK.r13,
                                               `U_REGISTER_BANK.r13_firq,
                                               `U_REGISTER_BANK.r13_irq,
                                               `U_REGISTER_BANK.r13_svc);
    $display("r14 (lr) 0x%08x   0x%08x   0x%08x   0x%08x",
                                               `U_REGISTER_BANK.r14,
                                               `U_REGISTER_BANK.r14_firq,
                                               `U_REGISTER_BANK.r14_irq,
                                               `U_REGISTER_BANK.r14_svc);
 
 
    $display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
    $display("");
    $display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",
       `U_EXECUTE.status_bits_flags[3],
       `U_EXECUTE.status_bits_flags[2],
       `U_EXECUTE.status_bits_flags[1],
       `U_EXECUTE.status_bits_flags[0],
       `U_EXECUTE.status_bits_irq_mask,
       `U_EXECUTE.status_bits_firq_mask,
       mode_name (`U_EXECUTE.status_bits_mode) );
    $display("----------------------------------------------------------------------------");
    $display("");
 
end
endtask
 
 
// ======================================
// Functions
// ======================================
function [127:0] insert_32_into_128;
input [1:0]   pos;
input [127:0] word128;
input [31:0]  word32;
begin
     case (pos)
         2'd0: insert_32_into_128 = {word128[127:32], word32};
         2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};
         2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};
         2'd3: insert_32_into_128 = {word32, word128[95:0]};
     endcase
end
endfunction
 
endmodule
 
 
 
 
module WireDelay # (
  parameter Delay_g = 0,
  parameter Delay_rd = 0
)
(
  inout A,
  inout B,
  input reset
);
 
  reg A_r;
  reg B_r;
  reg line_en;
 
  assign A = A_r;
  assign B = B_r;
 
  always @(*) begin
    if (!reset) begin
      A_r <= 1'bz;
      B_r <= 1'bz;
      line_en <= 1'b0;
    end else begin
      if (line_en) begin
        A_r <= #Delay_rd B;
        B_r <= 1'bz;
      end else begin
        B_r <= #Delay_g A;
        A_r <= 1'bz;
      end
    end
  end
 
  always @(A or B) begin
    if (!reset) begin
      line_en <= 1'b0;
    end else if (A !== A_r) begin
      line_en <= 1'b0;
    end else if (B_r !== B) begin
      line_en <= 1'b1;
    end else begin
      line_en <= line_en;
    end
  end
endmodule

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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [tb.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Top Level testbench //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Instantiates the system, ddr3 memory model and tb_uart //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41			`timescale 1 ps / 1 ps
42
43			`include "system_config_defines.v"
44			`include "global_defines.v"
45
46
47			`module tb();`
48
49			`include "debug_functions.v"
50
51			`reg sysrst;`
52			`ifdef XILINX_VIRTEX6_FPGA
53			`reg clk_533mhz;`
54			`endif
55			`reg clk_200mhz;`
56			`reg clk_25mhz;`
57			`reg [31:0] clk_count;`
58
59			`integer log_file;`
60
61			`ifdef AMBER_LOAD_MAIN_MEM
62			`integer main_mem_file;`
63			`reg [31:0] main_mem_file_address;`
64			`reg [31:0] main_mem_file_data;`
65			`reg [127:0] main_mem_file_data_128;`
66			`integer main_mem_line_count;`
67			`reg [22:0] mm_ddr3_addr;`
68			`endif
69
70			`integer boot_mem_file;`
71			`reg [31:0] boot_mem_file_address;`
72			`reg [31:0] boot_mem_file_data;`
73			`integer boot_mem_line_count;`
74			`integer fgets_return;`
75			`reg [120*8-1:0] line;`
76			`reg [120*8-1:0] aligned_line;`
77
78			`wire [12:0] ddr3_addr;`
79			`wire [2:0] ddr3_ba;`
80			`wire ddr3_ck_p;`
81			`wire ddr3_ck_n;`
82			`wire [15:0] ddr3_dq;`
83			`wire [1:0] ddr3_dqs_p;`
84			`wire [1:0] ddr3_dqs_n;`
85			`wire [1:0] ddr3_dm;`
86			`wire ddr3_ras_n;`
87			`wire ddr3_cas_n;`
88			`wire ddr3_we_n;`
89			`wire ddr3_cke;`
90			`wire ddr3_odt;`
91			`wire ddr3_reset_n;`
92
93
94			`ifdef XILINX_SPARTAN6_FPGA
95			`wire mcb3_rzq;`
96			`wire mcb3_zio;`
97			`endif
98
99			`tri1 md_pad_io;`
100
101			`wire uart0_cts;`
102			`wire uart0_rx;`
103			`wire uart0_rts;`
104			`wire uart0_tx;`
105
106
107			`// ======================================`
108			`// Instantiate FPGA`
109			`// ======================================`
110			`system u_system (`
111			`// Clocks and resets`
112			`.brd_rst ( sysrst ),`
113			`.brd_clk_p ( clk_200mhz ),`
114			`.brd_clk_n ( ~clk_200mhz ),`
115
116			`ifdef XILINX_VIRTEX6_FPGA
117			`.sys_clk_p ( clk_533mhz ),`
118			`.sys_clk_n ( ~clk_533mhz ),`
119			`endif
120
121			`// UART 0 signals`
122			`.o_uart0_cts ( uart0_cts ),`
123			`.o_uart0_rx ( uart0_rx ),`
124			`.i_uart0_rts ( uart0_rts ),`
125			`.i_uart0_tx ( uart0_tx ),`
126
127			`// DDR3 signals`
128			`.ddr3_dq ( ddr3_dq ),`
129			`.ddr3_addr ( ddr3_addr ),`
130			`.ddr3_ba ( ddr3_ba ),`
131			`.ddr3_ras_n ( ddr3_ras_n ),`
132			`.ddr3_cas_n ( ddr3_cas_n ),`
133			`.ddr3_we_n ( ddr3_we_n ),`
134			`.ddr3_odt ( ddr3_odt ),`
135			`.ddr3_reset_n ( ddr3_reset_n ),`
136			`.ddr3_cke ( ddr3_cke ),`
137			`.ddr3_dm ( ddr3_dm ),`
138			`.ddr3_dqs_p ( ddr3_dqs_p ),`
139			`.ddr3_dqs_n ( ddr3_dqs_n ),`
140			`.ddr3_ck_p ( ddr3_ck_p ),`
141			`.ddr3_ck_n ( ddr3_ck_n ),`
142			`ifdef XILINX_VIRTEX6_FPGA
143			`.ddr3_cs_n ( ddr3_cs_n ),`
144			`endif
145			`ifdef XILINX_SPARTAN6_FPGA
146			`.mcb3_rzq ( mcb3_rzq ),`
147			`.mcb3_zio ( mcb3_zio ),`
148			`endif
149
150			`// Ethernet MII signals`
151			`.mtx_clk_pad_i ( clk_25mhz ),`
152			`.mtxd_pad_o ( ),`
153			`.mtxen_pad_o ( ),`
154			`.mtxerr_pad_o ( ),`
155			`.mrx_clk_pad_i ( clk_25mhz ),`
156			`.mrxd_pad_i ( 4'd0 ),`
157			`.mrxdv_pad_i ( 1'd0 ),`
158			`.mrxerr_pad_i ( 1'd0 ),`
159			`.mcoll_pad_i ( 1'd0 ),`
160			`.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY`
161			`.phy_reset_n ( ),`
162
163			`// Ethernet MD signals`
164			`.md_pad_io ( md_pad_io ),`
165			`.mdc_pad_o ( )`
166
167			`);`
168
169
170			`// ======================================`
171			`// Instantiate DDR3 Memory Model`
172			`// ======================================`
173			`ifdef XILINX_FPGA
174			`ddr3_model_c3 #(`
175			`.DEBUG ( 0 ) // Set to 1 to enable debug messages`
176			`)`
177			`u_ddr3_model (`
178			`.ck ( ddr3_ck_p ),`
179			`.ck_n ( ddr3_ck_n ),`
180			`.cke ( ddr3_cke ),`
181			`ifdef XILINX_VIRTEX6_FPGA
182			`.cs_n ( ddr3_cs_n ),`
183			`else
184			`.cs_n ( 1'b0 ),`
185			`endif
186			`.ras_n ( ddr3_ras_n ),`
187			`.cas_n ( ddr3_cas_n ),`
188			`.we_n ( ddr3_we_n ),`
189			`.dm_tdqs ( ddr3_dm ),`
190			`.ba ( ddr3_ba ),`
191			`.addr ( {1'd0, ddr3_addr} ),`
192	11	csantifort	`.dq ( ddr3_dq ),`
193			`.dqs ( ddr3_dqs_p ),`
194			`.dqs_n ( ddr3_dqs_n ),`
195	2	csantifort	`.tdqs_n ( ),`
196			`.odt ( ddr3_odt ),`
197			`.rst_n ( ddr3_reset_n )`
198			`);`
199			`endif
200
201
202			`// ======================================`
203			`// Instantiate Testbench UART`
204			`// ======================================`
205			`tb_uart u_tb_uart (`
206			`.i_uart_cts_n ( uart0_cts ), // Clear To Send`
207			`.i_uart_rxd ( uart0_rx ),`
208			`.o_uart_rts_n ( uart0_rts ), // Request to Send`
209			`.o_uart_txd ( uart0_tx )`
210
211			`);`
212
213
214			`// ======================================`
215			`// Global module for xilinx hardware simulations`
216			`// ======================================`
217			`ifdef XILINX_FPGA
218			`define GLBL
219			`glbl glbl();`
220			`endif
221
222
223			`// ======================================`
224			`// Clock and Reset`
225			`// ======================================`
226
227			`// 200 MHz clock`
228			`initial`
229			`begin`
230			`clk_200mhz = 1'd0;`
231			`// Time unit is pico-seconds`
232			`forever #2500 clk_200mhz = ~clk_200mhz;`
233			`end`
234
235
236			`ifdef XILINX_VIRTEX6_FPGA
237			`// 400 MHz clock`
238			`initial`
239			`begin`
240			`clk_533mhz = 1'd0;`
241			`// Time unit is pico-seconds`
242			`forever #938 clk_533mhz = ~clk_533mhz;`
243			`end`
244			`endif
245
246
247			`// 25 MHz clock`
248			`initial`
249			`begin`
250			`clk_25mhz = 1'd0;`
251			`forever #20000 clk_25mhz = ~clk_25mhz;`
252			`end`
253
254			`initial`
255			`begin`
256			`sysrst = 1'd1;`
257			`#15002500`
258			`sysrst = 1'd0;`
259			`end`
260
261
262			`// ======================================`
263			`// Counter of system clock ticks`
264			`// ======================================`
265			always @ ( posedge `U_SYSTEM.sys_clk )
266			if ( `U_SYSTEM.sys_rst )
267			`clk_count <= 'd0;`
268			`else`
269			`clk_count <= clk_count + 1'd1;`
270
271
272
273			`// ======================================`
274			`// Test Name`
275			`// ======================================`
276			`initial`
277			`begin`
278			$display("Test %s, log file %s",`AMBER_TEST_NAME, `AMBER_LOG_FILE);
279			log_file = $fopen(`AMBER_LOG_FILE, "a");
280			`end`
281
282
283
284			`// ======================================`
285			`// Initialize Boot Memory`
286			`// ======================================`
287			`ifndef XILINX_FPGA
288			`initial`
289			`begin`
290			$display("Load boot memory from %s", `BOOT_MEM_FILE);
291			`boot_mem_line_count = 0;`
292			boot_mem_file = $fopen(`BOOT_MEM_FILE, "r");
293			`if (boot_mem_file == 0)`
294			`begin`
295			`TB_ERROR_MESSAGE
296			$display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
297			`end`
298
299			`if (boot_mem_file != 0)`
300			`begin`
301			`fgets_return = 1;`
302			`while (fgets_return != 0)`
303			`begin`
304			`fgets_return = $fgets(line, boot_mem_file);`
305			`boot_mem_line_count = boot_mem_line_count + 1;`
306			`aligned_line = align_line(line);`
307
308			`// if the line does not start with a comment`
309			`if (aligned_line[1208-1:1188] != 16'h2f2f)`
310			`begin`
311			`// check that line doesnt start with a '@' or a blank`
312			`if (aligned_line[1208-1:1198] != 8'h40 && aligned_line[1208-1:1198] != 8'h00)`
313			`begin`
314			`$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",`
315			`BOOT_MEM_FILE, boot_mem_line_count, aligned_line[1188-1:1178]);
316			`TB_ERROR_MESSAGE
317			`end`
318
319			`if (aligned_line[1208-1:1198] != 8'h00)`
320			`begin`
321			`boot_mem_file_address = hex_chars_to_32bits (aligned_line[1198-1:1118]);`
322			`boot_mem_file_data = hex_chars_to_32bits (aligned_line[1108-1:1028]);`
323
324			`tb.u_system.u_boot_mem.u_mem.mem [boot_mem_file_address[12:2]] = boot_mem_file_data;`
325
326			`ifdef AMBER_LOAD_MEM_DEBUG
327			`$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",`
328			`boot_mem_file_address, boot_mem_file_data);`
329			`endif
330			`end`
331			`end`
332			`end`
333
334			`$display("Read in %1d lines", boot_mem_line_count);`
335			`end`
336			`end`
337
338			`endif
339
340
341			`// ======================================`
342			`// Initialize Main Memory`
343			`// ======================================`
344			`ifdef AMBER_LOAD_MAIN_MEM
345			`initial`
346			`begin`
347			$display("Load main memory from %s", `MAIN_MEM_FILE);
348			`ifdef XILINX_FPGA
349			`// Wait for DDR3 initialization to complete`
350			`$display("Wait for DDR3 initialization to complete before loading main memory");`
351			`#70000000`
352			$display("Done waiting at %d ticks", `U_TB.clk_count);
353			`endif
354			main_mem_file = $fopen(`MAIN_MEM_FILE, "r");
355
356			`// Read RAM File`
357			`main_mem_line_count = 0;`
358
359			`if (main_mem_file == 0)`
360			`begin`
361			$display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
362			`TB_ERROR_MESSAGE
363			`end`
364
365
366			`if (main_mem_file != 0)`
367			`begin`
368			`fgets_return = 1;`
369			`while (fgets_return != 0)`
370			`begin`
371			`fgets_return = $fgets(line, main_mem_file);`
372			`main_mem_line_count = main_mem_line_count + 1;`
373			`aligned_line = align_line(line);`
374
375			`// if the line does not start with a comment`
376			`if (aligned_line[1208-1:1188] != 16'h2f2f)`
377			`begin`
378			`// check that line doesnt start with a '@' or a blank`
379			`if (aligned_line[1208-1:1198] != 8'h40 && aligned_line[1208-1:1198] != 8'h00)`
380			`begin`
381			`$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",`
382			`MAIN_MEM_FILE, main_mem_line_count, aligned_line[1188-1:1178]);
383			`TB_ERROR_MESSAGE
384			`end`
385
386			`if (aligned_line[1208-1:1198] != 8'h00)`
387			`begin`
388			`main_mem_file_address = hex_chars_to_32bits (aligned_line[1198-1:1118]);`
389			`main_mem_file_data = hex_chars_to_32bits (aligned_line[1108-1:1028]);`
390
391			`ifdef XILINX_FPGA
392			`mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};`
393
394	11	csantifort	`main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];`
395			`tb.u_ddr3_model.memory [mm_ddr3_addr] =`
396	2	csantifort	`insert_32_into_128 ( main_mem_file_address[3:2],`
397			`main_mem_file_data_128,`
398			`main_mem_file_data );`
399
400			`ifdef AMBER_LOAD_MEM_DEBUG
401	11	csantifort	`main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];`
402	2	csantifort	`$display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",`
403			`main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);`
404			`endif
405
406			`else
407			`// Fast simulation model of main memory`
408
409			`// U_RAM - Can either point to simple or Xilinx DDR3 model.`
410			`// Set in hierarchy_defines.v`
411
412			main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
413			`U_RAM [main_mem_file_address[31:4]] =
414			`insert_32_into_128 ( main_mem_file_address[3:2],`
415			`main_mem_file_data_128,`
416			`main_mem_file_data );`
417
418			`ifdef AMBER_LOAD_MEM_DEBUG
419			`$display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",`
420			`main_mem_file_address, main_mem_file_data);`
421			`endif
422
423			`endif
424
425			`end`
426			`end`
427			`end`
428
429			`$display("Read in %1d lines", main_mem_line_count);`
430			`end`
431			`end`
432			`endif
433
434
435			`dumpvcd u_dumpvcd();`
436
437			`// ======================================`
438			`// Terminate Test`
439			`// ======================================`
440			`include "amber_localparams.v"
441			`include "amber_functions.v"
442
443			`reg testfail;`
444			`wire test_status_set;`
445			`wire [31:0] test_status_reg;`
446
447			`initial`
448			`testfail = 1'd0;`
449
450			assign test_status_set = `U_TEST_MODULE.test_status_set;
451			assign test_status_reg = `U_TEST_MODULE.test_status_reg;
452
453			`always @*`
454			`begin`
455			`if ( test_status_set \|\| testfail )`
456			`begin`
457			`if ( test_status_reg == 32'd17 && !testfail )`
458			`begin`
459			`display_registers;`
460			`$display("++++++++++++++++++++");`
461			$write("Passed %s\n", `AMBER_TEST_NAME);
462			`$display("++++++++++++++++++++");`
463			$fwrite(`U_TB.log_file,"Passed %s\n", `AMBER_TEST_NAME);
464			`$finish;`
465			`end`
466			`else`
467			`begin`
468			`display_registers;`
469			`if ( testfail )`
470			`begin`
471			`$display("++++++++++++++++++++");`
472			$write("Failed %s - assertion error\n", `AMBER_TEST_NAME);
473			`$display("++++++++++++++++++++");`
474			$fwrite(`U_TB.log_file,"Failed %s - assertion error\n", `AMBER_TEST_NAME);
475			`$finish;`
476			`end`
477			`else`
478			`begin`
479			`$display("++++++++++++++++++++");`
480			`if (test_status_reg >= 32'h8000)`
481			$write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
482			`else`
483			$write("Failed %s - with error %1d\n", `AMBER_TEST_NAME, test_status_reg);
484			`$display("++++++++++++++++++++");`
485			`if (test_status_reg >= 32'h8000)`
486			$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
487			`else`
488			$fwrite(`U_TB.log_file,"Failed %s - with error %1d\n", `AMBER_TEST_NAME, test_status_reg);
489			`$finish;`
490			`end`
491			`end`
492			`end`
493			`end`
494
495
496
497			`// ======================================`
498			`// Tasks`
499			`// ======================================`
500			`task display_registers;`
501			`begin`
502			`$display("");`
503			`$display("----------------------------------------------------------------------------");`
504			`$display("Amber Core");`
505
506			case (`U_EXECUTE.status_bits_mode)
507			`FIRQ: $display(" User > FIRQ IRQ SVC");`
508			`IRQ: $display(" User FIRQ > IRQ SVC");`
509			`SVC: $display(" User FIRQ IRQ > SVC");`
510			`default: $display(" > User FIRQ IRQ SVC");`
511			`endcase`
512
513			$display("r0 0x%08x", `U_REGISTER_BANK.r0);
514			$display("r1 0x%08x", `U_REGISTER_BANK.r1);
515			$display("r2 0x%08x", `U_REGISTER_BANK.r2);
516			$display("r3 0x%08x", `U_REGISTER_BANK.r3);
517			$display("r4 0x%08x", `U_REGISTER_BANK.r4);
518			$display("r5 0x%08x", `U_REGISTER_BANK.r5);
519			$display("r6 0x%08x", `U_REGISTER_BANK.r6);
520			$display("r7 0x%08x", `U_REGISTER_BANK.r7);
521			$display("r8 0x%08x 0x%08x ", `U_REGISTER_BANK.r8, `U_REGISTER_BANK.r8_firq);
522			$display("r9 0x%08x 0x%08x ", `U_REGISTER_BANK.r9, `U_REGISTER_BANK.r9_firq);
523			$display("r10 0x%08x 0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
524			$display("r11 0x%08x 0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
525			$display("r12 0x%08x 0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
526
527			`$display("r13 0x%08x 0x%08x 0x%08x 0x%08x",`
528			`U_REGISTER_BANK.r13,
529			`U_REGISTER_BANK.r13_firq,
530			`U_REGISTER_BANK.r13_irq,
531			`U_REGISTER_BANK.r13_svc);
532			`$display("r14 (lr) 0x%08x 0x%08x 0x%08x 0x%08x",`
533			`U_REGISTER_BANK.r14,
534			`U_REGISTER_BANK.r14_firq,
535			`U_REGISTER_BANK.r14_irq,
536			`U_REGISTER_BANK.r14_svc);
537
538
539			$display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
540			`$display("");`
541			`$display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",`
542			`U_EXECUTE.status_bits_flags[3],
543			`U_EXECUTE.status_bits_flags[2],
544			`U_EXECUTE.status_bits_flags[1],
545			`U_EXECUTE.status_bits_flags[0],
546			`U_EXECUTE.status_bits_irq_mask,
547			`U_EXECUTE.status_bits_firq_mask,
548			mode_name (`U_EXECUTE.status_bits_mode) );
549			`$display("----------------------------------------------------------------------------");`
550			`$display("");`
551
552			`end`
553			`endtask`
554
555
556			`// ======================================`
557			`// Functions`
558			`// ======================================`
559			`function [127:0] insert_32_into_128;`
560			`input [1:0] pos;`
561			`input [127:0] word128;`
562			`input [31:0] word32;`
563			`begin`
564			`case (pos)`
565			`2'd0: insert_32_into_128 = {word128[127:32], word32};`
566			`2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};`
567			`2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};`
568			`2'd3: insert_32_into_128 = {word32, word128[95:0]};`
569			`endcase`
570			`end`
571			`endfunction`
572
573			`endmodule`
574
575
576
577
578			`module WireDelay # (`
579			`parameter Delay_g = 0,`
580			`parameter Delay_rd = 0`
581			`)`
582			`(`
583			`inout A,`
584			`inout B,`
585			`input reset`
586			`);`
587
588			`reg A_r;`
589			`reg B_r;`
590			`reg line_en;`
591
592			`assign A = A_r;`
593			`assign B = B_r;`
594
595			`always @(*) begin`
596			`if (!reset) begin`
597			`A_r <= 1'bz;`
598			`B_r <= 1'bz;`
599			`line_en <= 1'b0;`
600			`end else begin`
601			`if (line_en) begin`
602			`A_r <= #Delay_rd B;`
603			`B_r <= 1'bz;`
604			`end else begin`
605			`B_r <= #Delay_g A;`
606			`A_r <= 1'bz;`
607			`end`
608			`end`
609			`end`
610
611			`always @(A or B) begin`
612			`if (!reset) begin`
613			`line_en <= 1'b0;`
614			`end else if (A !== A_r) begin`
615			`line_en <= 1'b0;`
616			`end else if (B_r !== B) begin`
617			`line_en <= 1'b1;`
618			`end else begin`
619			`line_en <= line_en;`
620			`end`
621			`end`
622			`endmodule`