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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [tb_uart.v] - Blame information for rev 27

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//////////////////////////////////////////////////////////////////
//                                                              //
//  Testbench UART                                              //
//                                                              //
//  This file is part of the Amber project                      //
//  http://www.opencores.org/project,amber                      //
//                                                              //
//  Description                                                 //
//  Provides a target to test the wishbone UART against.        //
//                                                              //
//  Author(s):                                                  //
//      - Conor Santifort, csantifort.amber@gmail.com           //
//                                                              //
//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
//                                                              //
// This source file may be used and distributed without         //
// restriction provided that this copyright statement is not    //
// removed from the file and that any derivative work contains  //
// the original copyright notice and the associated disclaimer. //
//                                                              //
// This source file is free software; you can redistribute it   //
// and/or modify it under the terms of the GNU Lesser General   //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any   //
// later version.                                               //
//                                                              //
// This source is distributed in the hope that it will be       //
// useful, but WITHOUT ANY WARRANTY; without even the implied   //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
// PURPOSE.  See the GNU Lesser General Public License for more //
// details.                                                     //
//                                                              //
// You should have received a copy of the GNU Lesser General    //
// Public License along with this source; if not, download it   //
// from http://www.opencores.org/lgpl.shtml                     //
//                                                              //
//////////////////////////////////////////////////////////////////
 
`timescale  1 ps / 1 ps
 
module tb_uart (
input                       i_uart_cts_n,          // Clear To Send
output reg                  o_uart_txd,
output                      o_uart_rts_n,          // Request to Send
input                       i_uart_rxd
 
);
 
assign o_uart_rts_n = 1'd0;  // allow the other side to transmit all the time
 
// -------------------------------------------------------------------------
// Baud Rate Configuration
// -------------------------------------------------------------------------
 
// Baud period in nanoseconds
localparam UART_BAUD         = `AMBER_UART_BAUD;            // Hz
localparam UART_BIT_PERIOD   = 1000000000 / UART_BAUD;      // nS
 
// -------------------------------------------------------------------------
 
reg             clk_uart;
reg             clk_uart_rst_n;
 
reg [1:0]       rx_state;
reg [2:0]       rx_bit;
reg [7:0]       rx_byte;
reg [3:0]       rx_tap;
reg [3:0]       rx_bit_count;
wire            rx_bit_start;
wire            rx_start_negedge;
reg             rx_start_negedge_d1;
 
reg [1:0]       tx_state;
reg [2:0]       tx_bit;
reg [7:0]       tx_byte;
reg [3:0]       tx_bit_count;
wire            tx_bit_start;
wire            tx_start;
wire            loopback;
wire            tx_push;
reg             tx_push_r;
wire            tx_push_toggle;
wire [7:0]      txd;
 
wire            txfifo_empty;
wire            txfifo_full;
reg  [7:0]      tx_fifo [15:0];
reg  [4:0]      txfifo_wp;
reg  [4:0]      txfifo_rp;
 
 
// ======================================================
// UART Clock
// ======================================================
 
// runs at 10x baud rate
initial
    begin
    clk_uart        = 1'd0;
    forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;
    end
 
initial
    begin
    // in reset
    clk_uart_rst_n  = 1'd0;
    // out of reset
    #(UART_BIT_PERIOD*1000) clk_uart_rst_n  = 1'd1;
    end
 
 
// ======================================================
// UART Receive
// ======================================================
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        rx_bit_count <= 'd0;
    else if ( rx_bit_count == 4'd9 )
        rx_bit_count <= 'd0;
    // align the bit count to the centre each incoming bit    
    else if ( rx_start_negedge )
        rx_bit_count <= 'd0;
    else
        rx_bit_count <= rx_bit_count + 1'd1;
 
assign rx_bit_start     = rx_bit_count == 4'd0;
assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        rx_state            <= 'd0;
        rx_bit              <= 'd0;
        rx_byte             <= 'd0;
        rx_tap              <= 'd0;
        rx_start_negedge_d1 <= 'd0;
        end
    else
        begin
        rx_tap <= { rx_tap[2:0], i_uart_rxd };
        rx_start_negedge_d1 <= rx_start_negedge;
 
        if ( rx_bit_start )
            begin
            case ( rx_state )
 
                // wait for start bit edge at end of tap
                // then sample bits at start of tap, approx
                // in the center of each bit
                2'd0: if ( rx_start_negedge_d1 )
                        rx_state <= 2'd1;
 
                // 8 bits in a word        
                2'd1: if ( rx_bit == 3'd7 )
                        rx_state <= 2'd2;
 
                // stop bit
                2'd2: rx_state <= 2'd0;
 
            endcase
 
            if ( rx_state == 2'd1 )
                begin
                rx_bit  <= rx_bit + 1'd1;
                // UART sends LSB first
                rx_byte <= {i_uart_rxd, rx_byte[7:1]};
                end
 
            // Ignore carriage returns so don't get a blank line
            // between every printed line in silumations   
            if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )
                $write("%c", rx_byte);
            end
        end
 
 
// ========================================================
// UART Transmit
// ========================================================
 
// Get control bits from the wishbone uart test register
assign tx_start     = `U_TEST_MODULE.tb_uart_control_reg[0];
assign loopback     = `U_TEST_MODULE.tb_uart_control_reg[1];
 
always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
 
assign tx_push      = `U_TEST_MODULE.tb_uart_push;
assign txd          = `U_TEST_MODULE.tb_uart_txd_reg;
 
assign tx_bit_start = tx_bit_count == 4'd0;
assign txfifo_empty = txfifo_wp == txfifo_rp;
assign txfifo_full  = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};
 
 
// Detect when the tx_push signal changes value. It is on a different
// clock domain so this is needed to detect it cleanly
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        tx_push_r <= 'd0;
    else
        tx_push_r <= tx_push;
 
assign tx_push_toggle =  tx_push ^ tx_push_r;
 
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        tx_bit_count <= 'd0;
    else if ( tx_bit_count == 4'd9 )
        tx_bit_count <= 'd0;
    else
        tx_bit_count <= tx_bit_count + 1'd1;
 
 
// Transmit FIFO. 8 entries
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        txfifo_wp               <=    'd0;
        end
    else if ( !loopback && tx_push_toggle && !txfifo_full )
        begin
        tx_fifo[txfifo_wp[3:0]] <=    txd;
        txfifo_wp               <=    txfifo_wp + 1'd1;
        end
    else if ( !loopback && tx_push_toggle && txfifo_full )
        begin
        `TB_WARNING_MESSAGE
        $display("TB UART FIFO overflow");
        end
    // loopback received byte into tx buffer    
    else if ( loopback && rx_state == 2'd2 && rx_bit_start )
        begin
        tx_fifo[txfifo_wp[3:0]] <=    rx_byte;
        txfifo_wp               <=    txfifo_wp + 1'd1;
        end
 
 
always @( posedge clk_uart or negedge clk_uart_rst_n )
    if ( ~clk_uart_rst_n )
        begin
        tx_state            <= 'd0;
        tx_bit              <= 'd0;
        tx_byte             <= 'd0;
        o_uart_txd          <= 1'd1;
        txfifo_rp           <= 'd0;
        end
    else
        begin
        if ( tx_bit_start )
            begin
            case ( tx_state )
 
                // wait for trigger to start transmitting
                2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )
                        begin
                        tx_state    <= 2'd1;
                        tx_byte     <= tx_fifo[txfifo_rp[3:0]];
                        txfifo_rp   <= txfifo_rp + 1'd1;
                        // transmit start bit
                        o_uart_txd  <= 1'd0;
                        end
 
                // 8 bits in a word        
                2'd1: if ( !i_uart_cts_n )
                        begin
                        if ( tx_bit == 3'd7 )
                            tx_state <= 2'd2;
                        tx_bit      <= tx_bit + 1'd1;
                        tx_byte     <= {1'd0, tx_byte[7:1]};
                        // UART sends LSB first
                        o_uart_txd  <= tx_byte[0];
                        end
 
                // stop bit
                2'd2:   begin
                        tx_state    <= 2'd0;
                        o_uart_txd  <= 1'd1;
                        end
            endcase
            end
        end
 
 
endmodule
 

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[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] [tb_uart.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	2	csantifort	`//////////////////////////////////////////////////////////////////`
2			`// //`
3			`// Testbench UART //`
4			`// //`
5			`// This file is part of the Amber project //`
6			`// http://www.opencores.org/project,amber //`
7			`// //`
8			`// Description //`
9			`// Provides a target to test the wishbone UART against. //`
10			`// //`
11			`// Author(s): //`
12			`// - Conor Santifort, csantifort.amber@gmail.com //`
13			`// //`
14			`//////////////////////////////////////////////////////////////////`
15			`// //`
16			`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
17			`// //`
18			`// This source file may be used and distributed without //`
19			`// restriction provided that this copyright statement is not //`
20			`// removed from the file and that any derivative work contains //`
21			`// the original copyright notice and the associated disclaimer. //`
22			`// //`
23			`// This source file is free software; you can redistribute it //`
24			`// and/or modify it under the terms of the GNU Lesser General //`
25			`// Public License as published by the Free Software Foundation; //`
26			`// either version 2.1 of the License, or (at your option) any //`
27			`// later version. //`
28			`// //`
29			`// This source is distributed in the hope that it will be //`
30			`// useful, but WITHOUT ANY WARRANTY; without even the implied //`
31			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //`
32			`// PURPOSE. See the GNU Lesser General Public License for more //`
33			`// details. //`
34			`// //`
35			`// You should have received a copy of the GNU Lesser General //`
36			`// Public License along with this source; if not, download it //`
37			`// from http://www.opencores.org/lgpl.shtml //`
38			`// //`
39			`//////////////////////////////////////////////////////////////////`
40
41	27	csantifort	`timescale 1 ps / 1 ps
42	2	csantifort
43			`module tb_uart (`
44			`input i_uart_cts_n, // Clear To Send`
45			`output reg o_uart_txd,`
46			`output o_uart_rts_n, // Request to Send`
47			`input i_uart_rxd`
48
49			`);`
50
51			`assign o_uart_rts_n = 1'd0; // allow the other side to transmit all the time`
52
53			`// -------------------------------------------------------------------------`
54			`// Baud Rate Configuration`
55			`// -------------------------------------------------------------------------`
56
57			`// Baud period in nanoseconds`
58			localparam UART_BAUD = `AMBER_UART_BAUD; // Hz
59			`localparam UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS`
60
61			`// -------------------------------------------------------------------------`
62
63			`reg clk_uart;`
64			`reg clk_uart_rst_n;`
65
66			`reg [1:0] rx_state;`
67			`reg [2:0] rx_bit;`
68			`reg [7:0] rx_byte;`
69			`reg [3:0] rx_tap;`
70			`reg [3:0] rx_bit_count;`
71			`wire rx_bit_start;`
72			`wire rx_start_negedge;`
73			`reg rx_start_negedge_d1;`
74
75			`reg [1:0] tx_state;`
76			`reg [2:0] tx_bit;`
77			`reg [7:0] tx_byte;`
78			`reg [3:0] tx_bit_count;`
79			`wire tx_bit_start;`
80			`wire tx_start;`
81			`wire loopback;`
82			`wire tx_push;`
83			`reg tx_push_r;`
84			`wire tx_push_toggle;`
85			`wire [7:0] txd;`
86
87			`wire txfifo_empty;`
88			`wire txfifo_full;`
89			`reg [7:0] tx_fifo [15:0];`
90			`reg [4:0] txfifo_wp;`
91			`reg [4:0] txfifo_rp;`
92
93
94			`// ======================================================`
95			`// UART Clock`
96			`// ======================================================`
97
98			`// runs at 10x baud rate`
99			`initial`
100			`begin`
101			`clk_uart = 1'd0;`
102			`forever #(UART_BIT_PERIOD*100/2) clk_uart = ~clk_uart;`
103			`end`
104
105			`initial`
106			`begin`
107			`// in reset`
108			`clk_uart_rst_n = 1'd0;`
109			`// out of reset`
110			`#(UART_BIT_PERIOD*1000) clk_uart_rst_n = 1'd1;`
111			`end`
112
113
114			`// ======================================================`
115			`// UART Receive`
116			`// ======================================================`
117			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
118			`if ( ~clk_uart_rst_n )`
119			`rx_bit_count <= 'd0;`
120			`else if ( rx_bit_count == 4'd9 )`
121			`rx_bit_count <= 'd0;`
122			`// align the bit count to the centre each incoming bit`
123			`else if ( rx_start_negedge )`
124			`rx_bit_count <= 'd0;`
125			`else`
126			`rx_bit_count <= rx_bit_count + 1'd1;`
127
128			`assign rx_bit_start = rx_bit_count == 4'd0;`
129			`assign rx_start_negedge = rx_tap[3] && !rx_tap[2] && rx_state == 2'd0;`
130
131			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
132			`if ( ~clk_uart_rst_n )`
133			`begin`
134			`rx_state <= 'd0;`
135			`rx_bit <= 'd0;`
136			`rx_byte <= 'd0;`
137			`rx_tap <= 'd0;`
138			`rx_start_negedge_d1 <= 'd0;`
139			`end`
140			`else`
141			`begin`
142			`rx_tap <= { rx_tap[2:0], i_uart_rxd };`
143			`rx_start_negedge_d1 <= rx_start_negedge;`
144
145			`if ( rx_bit_start )`
146			`begin`
147			`case ( rx_state )`
148
149			`// wait for start bit edge at end of tap`
150			`// then sample bits at start of tap, approx`
151			`// in the center of each bit`
152			`2'd0: if ( rx_start_negedge_d1 )`
153			`rx_state <= 2'd1;`
154
155			`// 8 bits in a word`
156			`2'd1: if ( rx_bit == 3'd7 )`
157			`rx_state <= 2'd2;`
158
159			`// stop bit`
160			`2'd2: rx_state <= 2'd0;`
161
162			`endcase`
163
164			`if ( rx_state == 2'd1 )`
165			`begin`
166			`rx_bit <= rx_bit + 1'd1;`
167			`// UART sends LSB first`
168			`rx_byte <= {i_uart_rxd, rx_byte[7:1]};`
169			`end`
170
171			`// Ignore carriage returns so don't get a blank line`
172			`// between every printed line in silumations`
173			`if ( rx_state == 2'd2 && rx_byte != 8'h0d && rx_byte != 8'h0c )`
174			`$write("%c", rx_byte);`
175			`end`
176			`end`
177
178
179			`// ========================================================`
180			`// UART Transmit`
181			`// ========================================================`
182
183			`// Get control bits from the wishbone uart test register`
184			assign tx_start = `U_TEST_MODULE.tb_uart_control_reg[0];
185			assign loopback = `U_TEST_MODULE.tb_uart_control_reg[1];
186
187			always @* `U_TEST_MODULE.tb_uart_status_reg[1:0] = {txfifo_full, txfifo_empty};
188
189			assign tx_push = `U_TEST_MODULE.tb_uart_push;
190			assign txd = `U_TEST_MODULE.tb_uart_txd_reg;
191
192			`assign tx_bit_start = tx_bit_count == 4'd0;`
193			`assign txfifo_empty = txfifo_wp == txfifo_rp;`
194			`assign txfifo_full = txfifo_wp == {~txfifo_rp[4], txfifo_rp[3:0]};`
195
196
197			`// Detect when the tx_push signal changes value. It is on a different`
198			`// clock domain so this is needed to detect it cleanly`
199			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
200			`if ( ~clk_uart_rst_n )`
201			`tx_push_r <= 'd0;`
202			`else`
203			`tx_push_r <= tx_push;`
204
205			`assign tx_push_toggle = tx_push ^ tx_push_r;`
206
207
208			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
209			`if ( ~clk_uart_rst_n )`
210			`tx_bit_count <= 'd0;`
211			`else if ( tx_bit_count == 4'd9 )`
212			`tx_bit_count <= 'd0;`
213			`else`
214			`tx_bit_count <= tx_bit_count + 1'd1;`
215
216
217			`// Transmit FIFO. 8 entries`
218			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
219			`if ( ~clk_uart_rst_n )`
220			`begin`
221			`txfifo_wp <= 'd0;`
222			`end`
223			`else if ( !loopback && tx_push_toggle && !txfifo_full )`
224			`begin`
225			`tx_fifo[txfifo_wp[3:0]] <= txd;`
226			`txfifo_wp <= txfifo_wp + 1'd1;`
227			`end`
228			`else if ( !loopback && tx_push_toggle && txfifo_full )`
229			`begin`
230			`TB_WARNING_MESSAGE
231			`$display("TB UART FIFO overflow");`
232			`end`
233			`// loopback received byte into tx buffer`
234			`else if ( loopback && rx_state == 2'd2 && rx_bit_start )`
235			`begin`
236			`tx_fifo[txfifo_wp[3:0]] <= rx_byte;`
237			`txfifo_wp <= txfifo_wp + 1'd1;`
238			`end`
239
240
241			`always @( posedge clk_uart or negedge clk_uart_rst_n )`
242			`if ( ~clk_uart_rst_n )`
243			`begin`
244			`tx_state <= 'd0;`
245			`tx_bit <= 'd0;`
246			`tx_byte <= 'd0;`
247			`o_uart_txd <= 1'd1;`
248			`txfifo_rp <= 'd0;`
249			`end`
250			`else`
251			`begin`
252			`if ( tx_bit_start )`
253			`begin`
254			`case ( tx_state )`
255
256			`// wait for trigger to start transmitting`
257			`2'd0: if ( tx_start && !txfifo_empty && !i_uart_cts_n )`
258			`begin`
259			`tx_state <= 2'd1;`
260			`tx_byte <= tx_fifo[txfifo_rp[3:0]];`
261			`txfifo_rp <= txfifo_rp + 1'd1;`
262			`// transmit start bit`
263			`o_uart_txd <= 1'd0;`
264			`end`
265
266			`// 8 bits in a word`
267			`2'd1: if ( !i_uart_cts_n )`
268			`begin`
269			`if ( tx_bit == 3'd7 )`
270			`tx_state <= 2'd2;`
271			`tx_bit <= tx_bit + 1'd1;`
272			`tx_byte <= {1'd0, tx_byte[7:1]};`
273			`// UART sends LSB first`
274			`o_uart_txd <= tx_byte[0];`
275			`end`
276
277			`// stop bit`
278			`2'd2: begin`
279			`tx_state <= 2'd0;`
280			`o_uart_txd <= 1'd1;`
281			`end`
282			`endcase`
283			`end`
284			`end`
285
286
287			`endmodule`
288