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[/] [amber/] [trunk/] [sw/] [include/] [amber_registers.h] - Blame information for rev 2

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1 2 csantifort
/*----------------------------------------------------------------
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//                                                              //
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//  amber_registers.h                                           //
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//                                                              //
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//  This file is part of the Amber project                      //
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//  http://www.opencores.org/project,amber                      //
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//                                                              //
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//  Description                                                 //
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//  Defines the address of all registers in the Amber system.   //
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//  Must be kept synchronized with the equivalent Verilog       //
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//  file, $AMBER_BASE/hw/vlog/system/register_addresses.v       //
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//  which is considered the master.                             //
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//                                                              //
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//  Author(s):                                                  //
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//      - Conor Santifort, csantifort.amber@gmail.com           //
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//                                                              //
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//////////////////////////////////////////////////////////////////
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//                                                              //
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// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
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//                                                              //
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// This source file may be used and distributed without         //
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// restriction provided that this copyright statement is not    //
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// removed from the file and that any derivative work contains  //
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// the original copyright notice and the associated disclaimer. //
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//                                                              //
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// This source file is free software; you can redistribute it   //
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// and/or modify it under the terms of the GNU Lesser General   //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any   //
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// later version.                                               //
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//                                                              //
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// This source is distributed in the hope that it will be       //
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// useful, but WITHOUT ANY WARRANTY; without even the implied   //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
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// PURPOSE.  See the GNU Lesser General Public License for more //
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// details.                                                     //
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//                                                              //
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// You should have received a copy of the GNU Lesser General    //
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// Public License along with this source; if not, download it   //
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// from http://www.opencores.org/lgpl.shtml                     //
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//                                                              //
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----------------------------------------------------------------*/
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#define ADR_AMBER_TEST_STATUS          0xf0000000
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#define ADR_AMBER_TEST_FIRQ_TIMER      0xf0000004
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#define ADR_AMBER_TEST_IRQ_TIMER       0xf0000008
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#define ADR_AMBER_TEST_UART_CONTROL    0xf0000010
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#define ADR_AMBER_TEST_UART_STATUS     0xf0000014
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#define ADR_AMBER_TEST_UART_TXD        0xf0000018
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#define ADR_AMBER_TEST_SIM_CTRL        0xf000001c
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/* Allow access to the random register over
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   a 16-word address range to load a series
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   of random numbers using lmd instruction. */
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#define ADR_AMBER_TEST_RANDOM_NUM      0xf0000100
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#define ADR_AMBER_TEST_RANDOM_NUM00    0xf0000100
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#define ADR_AMBER_TEST_RANDOM_NUM01    0xf0000104
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#define ADR_AMBER_TEST_RANDOM_NUM02    0xf0000108
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#define ADR_AMBER_TEST_RANDOM_NUM03    0xf000010c
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#define ADR_AMBER_TEST_RANDOM_NUM04    0xf0000110
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#define ADR_AMBER_TEST_RANDOM_NUM05    0xf0000114
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#define ADR_AMBER_TEST_RANDOM_NUM06    0xf0000118
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#define ADR_AMBER_TEST_RANDOM_NUM07    0xf000011c
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#define ADR_AMBER_TEST_RANDOM_NUM08    0xf0000120
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#define ADR_AMBER_TEST_RANDOM_NUM09    0xf0000124
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#define ADR_AMBER_TEST_RANDOM_NUM10    0xf0000128
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#define ADR_AMBER_TEST_RANDOM_NUM11    0xf000012c
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#define ADR_AMBER_TEST_RANDOM_NUM12    0xf0000130
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#define ADR_AMBER_TEST_RANDOM_NUM13    0xf0000134
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#define ADR_AMBER_TEST_RANDOM_NUM14    0xf0000138
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#define ADR_AMBER_TEST_RANDOM_NUM15    0xf000013c
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#define ADR_AMBER_IC_IRQ0_ENABLESET    0x14000008
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#define ADR_AMBER_IC_IRQ1_ENABLESET    0x14000048
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#define ADR_AMBER_IC_INT_SOFTSET_0     0x14000010
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#define ADR_AMBER_IC_INT_SOFTCLEAR_0   0x14000014
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#define ADR_AMBER_IC_INT_SOFTSET_1     0x14000050
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#define ADR_AMBER_IC_INT_SOFTCLEAR_1   0x14000054
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#define ADR_AMBER_CT_TIMER0_LOAD       0x13000000
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#define ADR_AMBER_CT_TIMER1_LOAD       0x13000100
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#define ADR_AMBER_CT_TIMER2_LOAD       0x13000200
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#define ADR_AMBER_UART0_DR             0x16000000
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#define ADR_AMBER_UART0_RSR            0x16000004
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#define ADR_AMBER_UART0_LCRH           0x16000008
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#define ADR_AMBER_UART0_LCRM           0x1600000c
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#define ADR_AMBER_UART0_LCRL           0x16000010
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#define ADR_AMBER_UART0_CR             0x16000014
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#define ADR_AMBER_UART0_FR             0x16000018
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#define ADR_AMBER_UART0_IIR            0x1600001c
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#define ADR_AMBER_UART0_ICR            0x1600001c
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#define ADR_AMBER_UART1_DR             0x17000000
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#define ADR_AMBER_UART1_RSR            0x17000004
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#define ADR_AMBER_UART1_LCRH           0x17000008
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#define ADR_AMBER_UART1_LCRM           0x1700000c
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#define ADR_AMBER_UART1_LCRL           0x17000010
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#define ADR_AMBER_UART1_CR             0x17000014
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#define ADR_AMBER_UART1_FR             0x17000018
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#define ADR_AMBER_UART1_IIR            0x1700001c
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#define ADR_AMBER_UART1_ICR            0x1700001c
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#define ADR_AMBER_CORE_CTRL            0x1300031c
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#define ADR_ETHMAC_MODER               0x20000000
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#define ADR_ETHMAC_MIIMODER            0x20000028
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#define ADR_ETHMAC_MIICOMMAND          0x2000002C
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#define ADR_ETHMAC_MIIADDRESS          0x20000030
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#define ADR_ETHMAC_MIITXDATA           0x20000034
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#define ADR_ETHMAC_MIIRXDATA           0x20000038
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#define ADR_ETHMAC_MIISTATUS           0x2000003C
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#define ADR_ETHMAC_BDBASE              0x20000400

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