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[/] [aor3000/] [trunk/] [rtl/] [model/] [model_mult.v] - Blame information for rev 2

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1 2 alfik
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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module model_mult(
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    input                           clk,
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    input signed    [widtha-1:0]    a,
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    input signed    [widthb-1:0]    b,
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    output          [widthp-1:0]    out
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);
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//------------------------------------------------------------------------------
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parameter widtha = 1;
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parameter widthb = 1;
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parameter widthp = 2;
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//------------------------------------------------------------------------------
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reg signed [widtha-1:0] a_reg;
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reg signed [widthb-1:0] b_reg;
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reg signed [widthp-1:0] out_1;
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assign out = out_1;
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wire signed [widthp-1:0] mult_out;
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assign mult_out = a_reg * b_reg;
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always @ (posedge clk)
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begin
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    a_reg   <= a;
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    b_reg   <= b;
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    out_1   <= mult_out;
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end
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//------------------------------------------------------------------------------
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endmodule

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