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[/] [aor3000/] [trunk/] [syn/] [soc/] [soc.sdc] - Blame information for rev 2

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1 2 alfik
#************************************************************
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# THIS IS A WIZARD-GENERATED FILE.
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#
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# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
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#
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#************************************************************
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# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, the Altera Quartus II License Agreement,
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# the Altera MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Altera and sold by Altera or its
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# authorized distributors.  Please refer to the applicable
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# agreement for further details.
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# Clock constraints
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create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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# tsu/th constraints
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# tco constraints
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# tpd constraints
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