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[/] [apb2spi/] [trunk/] [tb/] [env/] [apb_agent/] [tb.v] - Blame information for rev 15

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Line No. Rev Author Line
1 15 vlnaran
`include "apb_slave.v"
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module tb();
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                reg pclk_i;
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                reg presetn_i;
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                reg [3:0] paddr_i;
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                reg pwrite_i;
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                reg [1:0] psel_i; // For future implementations using multiple SPIs
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                reg penable_i;
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                reg [7:0] pwdata_i;
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                wire pready_o;
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                wire [7:0] prdata_o;
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                reg [7:0] spi_data_i;
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                wire [7:0] spi_data_o;
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                reg spi_txn_cmpl_i;
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        apb_slave a1(
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                pclk_i,
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                presetn_i,
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                paddr_i,
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                pwrite_i,
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                psel_i, // For future implementations using multiple SPIs
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                penable_i,
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                pwdata_i,
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                pready_o,
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                prdata_o,
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                spi_data_i,
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                spi_data_o,
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                spi_txn_cmpl_i);
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initial
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begin
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        presetn_i = 1'b0;
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        pclk_i = 1'b0;
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        spi_data_i = 'hab;
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        #100 presetn_i = 1'b1;
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        $dumpfile("rcc.vcd");
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        $dumpvars(0,tb);
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        write();
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        read();
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        #100 $finish;
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end
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initial
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        forever #10 pclk_i = ~pclk_i;
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task write();
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begin
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        paddr_i = 'h0;
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        @(posedge pclk_i);
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        psel_i = 2'b01;
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        pwrite_i = 1'b1;
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        pwdata_i = $random;
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        @(posedge pclk_i);
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        penable_i = 1'b1;
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        spi_txn_cmpl_i = 1'b0;
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        @(posedge pclk_i);
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        spi_txn_cmpl_i = 1'b1;
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        @(posedge pclk_i);
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        penable_i = 1'b0;
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end
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endtask
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task read();
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begin
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        paddr_i = 'h0;
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        @(posedge pclk_i);
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        psel_i = 2'b11;
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        pwrite_i = 1'b0;
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        spi_data_i= $random;
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        @(posedge pclk_i);
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        penable_i = 1'b1;
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        spi_txn_cmpl_i = 1'b0;
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        @(posedge pclk_i);
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        spi_txn_cmpl_i = 1'b1;
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end
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endtask
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endmodule

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