OpenCores
URL https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk

Subversion Repositories artificial_neural_network

[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [adder_tree.vhd] - Blame information for rev 9

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 ojosynariz
----------------------------------------------------------------------------------
2
-- Company:
3
-- Engineer:
4
--
5
-- Create Date:    15:27:42 06/20/2013
6
-- Design Name:    Configurable ANN
7
-- Module Name:    adder_tree - Behavioral
8
-- Project Name:
9
-- Target Devices:
10
-- Tool versions:
11
-- Description: Recursive adder tree
12
--
13
-- Dependencies:
14
--
15
-- Revision:
16
-- Revision 0.01 - File Created
17
-- Additional Comments:
18
--
19
----------------------------------------------------------------------------------
20
 
21
library IEEE;
22
use IEEE.STD_LOGIC_1164.ALL;
23
use ieee.numeric_std.all;
24
 
25
 
26
entity adder_tree is
27
   generic
28
   (
29
      NumIn   : integer := 9;  -- Number of inputs
30
      Nbit    : integer := 12  -- Bit width of the input data
31
   );
32
 
33
   port
34
   (
35
      -- Input ports
36
      reset    : in  std_logic;
37
      clk      : in  std_logic;
38
      en       : in  std_logic; -- Enable
39
      inputs   : in  std_logic_vector((Nbit*NumIn)-1 downto 0); -- Input data
40
 
41
      -- Output ports
42
      en_out   : out std_logic; -- Output enable (output data validation)
43
      output   : out std_logic_vector(Nbit-1 downto 0) -- Output of the tree adder
44
   );
45
end adder_tree;
46
 
47
architecture Behavioral of adder_tree is
48
 
49
   constant NumIn2 : integer := NumIn/2; -- Number of imputs of the next adder tree layer
50
 
51
   signal next_en : std_logic := '0'; -- Next adder tree layer enable
52
   signal res : std_logic_vector((Nbit*((NumIn2)+(NumIn mod 2)))-1 downto 0); -- Partial results
53
 
54
   signal resL_reg : std_logic_vector((Nbit*NumIn2)-1 downto 0);
55
   signal resH_reg : std_logic_vector(Nbit-1 downto 0);
56
begin
57
 
58
-- Additions:
59
add_proc:
60
   process (clk) -- Synchronous to allow pipeline
61
   begin
62
      if (clk'event and clk = '1') then
63
         if (reset = '1') then
64
            resL_reg <= (others => '0');
65
         else
66
            if (en = '1') then
67
               -- Addition of inputs (2*i y 2*i+1), resulting in NumIn/2 outputs of this layer of the adder tree:
68
               for i in ((NumIn2)-1) downto 0 loop
69
                  resL_reg((Nbit*(i+1))-1 downto Nbit*i) <= std_logic_vector( signed(inputs((Nbit*((2*i)+1))-1 downto Nbit*2*i)) + signed(inputs((Nbit*((2*i)+2))-1 downto Nbit*((2*i)+1))) );
70
               end loop;
71
            end if;
72
         end if;
73
      end if;
74
   end process;
75
 
76
   res((Nbit*NumIn2)-1 downto 0) <= resL_reg;
77
 
78
-- Register the uneven input (if needed):
79
uneven_register:
80
   if (NumIn mod 2 = 1) generate
81
      process (clk)
82
      begin
83
         if (clk'event and clk = '1') then
84
            if (reset = '1') then
85
               resH_reg <= (others => '0');
86
            else
87
               if (en = '1') then
88
                  resH_reg <= inputs((Nbit*NumIn)-1 downto Nbit*(NumIn-1));
89
               end if;
90
            end if;
91
         end if;
92
      end process;
93
      res((Nbit*((NumIn2)+1))-1 downto Nbit*(NumIn2)) <= resH_reg;
94
   end generate;
95
 
96
   process (clk)
97
   begin
98
      if (clk'event and clk = '1') then
99
         if reset = '1' then
100
            next_en <= '0';
101
         else
102
            next_en <= en; -- Enable is delayed 1 cycle for the next layer of the adder tree
103
         end if;
104
      end if;
105
   end process;
106
 
107
recursion:
108
   if (NumIn > 2) generate
109
 
110 9 jstefanowi
      sub_adder_tree: entity work.adder_tree
111 3 ojosynariz
         generic map
112
         (
113
            NumIn => (NumIn2)+(NumIn mod 2),
114
            Nbit  => Nbit
115
         )
116
         port map
117
         (
118
            clk    => clk,
119
            reset  => reset,
120
            en     => next_en,
121
            inputs => res,
122
            en_out => en_out,
123
            output => output -- Solution is passed from the sub-adder trees to the top adder tree
124
         );
125
   end generate;
126
 
127
trivial_solution:
128
   if (NumIn = 2) generate
129
      en_out <= next_en;
130
      output <= res; -- Assign the final result to the adder tree output
131
   end generate;
132
 
133
end Behavioral;
134
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.