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ojosynariz |
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-- Company: CEI - UPM
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-- Engineer: David Aledo
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--
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-- Create Date: 01.10.2015 15:15:28
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-- Design Name: Configurable ANN
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-- Module Name: ann - config_structural
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description: generates the structure of an ANN with the given parameters.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.layers_pkg.all;
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entity ann is
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generic
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(
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Nlayer : integer := 2; ---- Number of layers
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NbitW : natural := 16; ---- Bit width of weights and biases
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NumIn : natural := 64; ---- Number of inputs to the network
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NbitIn : natural := 8; ---- Bit width of the inputs
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NumN : int_vector; ------ Number of neurons in each layer
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l_type : string; ---------- Layer type of each layer
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f_type : string; ---------- Activation function type of each layer
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LSbit : int_vector; ------ LSB of the output of each layer
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NbitO : int_vector; ------ Bit width of the outputs of each layer
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NbitOut : natural := 8 ----- Bit width of the network output
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);
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port
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(
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-- Input ports
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reset : in std_logic;
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clk : in std_logic;
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run_in : in std_logic; -- Start and input data validation
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m_en : in std_logic; -- Weight and bias memory enable (external interface)
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m_we : in std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
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inputs : in std_logic_vector(NbitIn-1 downto 0); -- Input data
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wdata : in std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory write data
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addr : in std_logic_vector((calculate_lra_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
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-- Output ports
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run_out : out std_logic; -- Output data validation
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rdata : out std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory read data
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outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data
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);
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end ann;
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architecture config_structural of ann is
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-- Arrays of configuration constants, generated from string generics:
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constant ltype_v : ltype_vector(Nlayer-1 downto 0) := assign_ltype(l_type,Nlayer);
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constant ftype_v : ftype_vector(Nlayer-1 downto 0) := assign_ftype(f_type,Nlayer);
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constant lra_l : int_vector(Nlayer-1 downto 0) := assign_addrl(NumIn,NumN,Nlayer); -- Layer RAM address length of each layer
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constant NumIn_v : int_vector(Nlayer-1 downto 0) := NumN(Nlayer-2 downto 0) & NumIn;
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constant wra_l : int_vector(Nlayer-1 downto 0) := log2(NumIn_v, Nlayer); -- Weight RAM address length of each layer
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constant bra_l : int_vector(Nlayer-1 downto 0) := log2(NumN, Nlayer); -- Bias ram address length of each layer
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-- Internal signals:
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signal lm_en : std_logic_vector(Nlayer-1 downto 0); -- Weight and bias memory enable of each layer
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type lrd_type is array (Nlayer-1 downto 0) of std_logic_vector(NbitW-1 downto 0);
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signal lrdata : lrd_type; -- Weight and bias memory read data of each layer
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type lodata_t is array (Nlayer-1 downto 0) of std_logic_vector(calculate_max_mul(NbitO,NumN)-1 downto 0); -- Parallel or serial data
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type ladata_t is array (Nlayer-1 downto 0) of std_logic_vector(calculate_max(NbitO)-1 downto 0); -- Always serial data
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signal runO : std_logic_vector(Nlayer-1 downto 0); -- Output data validation of each layer (before activation function)
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signal runI : std_logic_vector(Nlayer-1 downto 0); -- Input data validation of each layer
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signal runA : std_logic_vector(Nlayer-1 downto 0); -- Auxiliar serial data validation of each layer
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signal lodata : lodata_t; -- Output data of each layer (before activation function)
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signal lidata : lodata_t; -- Input data of each layer
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signal ladata : ladata_t; -- Auxiliar serial data of each layer
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begin
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-- Weight and bias memory layer selection (combinational mux):
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process (addr(addr'length-1 downto addr'length-log2(Nlayer)), m_en, lrdata)
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begin
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for i in 0 to Nlayer-1 loop
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if to_integer(unsigned(addr(addr'length-1 downto addr'length-log2(Nlayer)))) = i then
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lm_en(i) <= m_en;
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rdata <= lrdata(i);
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else
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lm_en(i) <= '0';
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end if;
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end loop;
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-- Note: Attention with addresses greater than Nlayer when it is not a power of two
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end process;
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-- ATTENTION: without the following if generate, the first layer must have serial input ('S')
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parallelize_inputs:
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if ltype_v(0)(1) = 'P' generate
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-- TODO: instantiate shift register with parallel output.
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-- synthesis translate_off
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assert ltype_v(0)(1) /= 'P'
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report "Current version does not accept parallel inputs."
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severity failure;
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-- synthesis translate_on
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-- TODO: delete above lines when instantiate shift register with parallel output.
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end generate;
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first_layer_SP:
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if ltype_v(0) = "SP" generate
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first_layerSP_top_inst: entity work.layerSP_top
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generic map
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(
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NumN => NumN(0), -- Number of neurons in the first layer
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NumIn => NumIn, ---- Number of inputs of the first layer
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NbitIn => NbitIn, --- Bit width of the input data
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NbitW => NbitW, ---- Bit width of weights and biases
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NbitOut => NbitO(0), -- Bit width of the first layer output
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lra_l => lra_l(0), -- Layer RAM address length of the first layer
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wra_l => wra_l(0), -- Weight RAM address length of the first layer
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bra_l => bra_l(0), -- Bias RAM address length of the first layer
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LSbit => LSbit(0) -- Less significant bit of the first layer outputs
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)
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port map
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(
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-- Input ports
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reset => reset,
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clk => clk,
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run_in => run_in, --- Input data validation of the first layer
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m_en => lm_en(0), -- Weight and bias memory enable of the first layer
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b_sel => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
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m_we => m_we, ----- Weight and bias memory write enable
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inputs => inputs, --- Inputs of the first layer (serial data)
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wdata => wdata, ---- Weight and bias memory write data
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addr => addr(lra_l(0)-1 downto 0), -- Weight and bias memory address of the first layer
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-- Output ports
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run_out => runO(0), -- Output data validation of the first layer
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rdata => lrdata(0), -- Weight and bias memory read data of the first layer
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outputs => lodata(0)((NumN(0)*NbitO(0))-1 downto 0) -- Outputs of the first layer (parallel data)
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);
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end generate;
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layers_insts:
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for i in 1 to Nlayer-1 generate
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-- If the previous layer (i-1) has parallel outputs and actual layer (i) has serial inputs, a serializer
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-- is inserted before the activation function (i-1). So, parallel activations functions are avoided.
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serializer:
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if (ltype_v(i-1)(2) = 'P') and (ltype_v(i)(1) = 'S') generate
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-- Instantiate shift-register with parallel load:
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shiftreg_parallel_load: entity work.shiftreg_pl
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generic map
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(
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Nreg => NumN(i-1), --- Number of registers in the shift-register corresponds with the number of neurons in the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the registers corresponds with the bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runO(i-1), -- Input data validation of the shift-register comes from the output data validation of the previous layer (i-1)
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inputs => lodata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0), -- Parallel input data to the shift-register come from the previous layer (i-1)
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run_out => runA(i-1), -- Output data validation goes to the activation function of the previous layer (i-1)
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outputs => ladata(i-1)(NbitO(i-1)-1 downto 0) -- Output serial data go to the activation function of the previous layer (i-1)
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);
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-- Instantiate single activation function of the previous layer (i-1):
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activation_function_inst: entity work.activation_function
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generic map
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(
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f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runA(i-1), -- Input data validation comes from the shift-register
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inputs => ladata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data come from the shift-register
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run_out => runI(i-1), -- Output data validation goes to the input data validation of this layer
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outputs => lidata(i-1)(NbitO(i-1)-1 downto 0) -- Serial output data go to the inputs of this layer
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);
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end generate; -- serializer
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-- If the previous layer (i-1) has serial outputs and actual layer (i) has serial inputs,
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-- a single activation function is instantiated:
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single_activation_function:
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if (ltype_v(i-1)(2) = 'S') and (ltype_v(i)(1) = 'S') generate
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-- Instantiate single activation function of the previous layer (i-1):
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activation_function_inst: entity work.activation_function
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generic map
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(
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f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runO(i-1), -- Input data validation comes from the previous layer (i-1)
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inputs => lodata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data come from the previous layer (i-1)
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run_out => runI(i-1), -- Output data validation goes to the input data validation of this layer
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outputs => lidata(i-1)(NbitO(i-1)-1 downto 0) -- Serial output data go to the inputs of this layer
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);
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end generate; -- single_activation_function
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-- If the previous layer (i-1) has parallel outputs and actual layer (i) has parallel inputs,
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-- multiple parallel activation functions are instantiated:
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multiple_activation_functions:
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if (ltype_v(i-1)(2) = 'P') and (ltype_v(i)(1) = 'P') generate
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-- First of the parallel activation functions. This is the one which generates the output data validation
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act_function_inst_0: entity work.activation_function
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generic map
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(
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f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runO(i-1), -- Input data validation comes from the previous layer (i-1)
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inputs => lodata(i-1)(NbitO(i-1)-1 downto 0), -- First of the parallel input data wich comes from the previous layer (i-1)
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run_out => runI(i-1), -- Output data validation goes to the input data validation of this layer
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outputs => lidata(i-1)(NbitO(i-1)-1 downto 0) -- First of the parallel inputs of this layer
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);
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-- Rest of the parallel activation functions of the previous layer (i-1)
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multiple_activation_function_insts:
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for j in 1 to NumN(i-1)-1 generate
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activation_function_inst: entity work.activation_function
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generic map
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(
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f_type => ftype_v(i-1), -- Activation function type of the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runO(i-1), -- Input data validation comes from the previous layer (i-1)
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inputs => lodata(i-1)((NbitO(i-1)*(j+1))-1 downto NbitO(i-1)*j), -- Rest of the parallel input data which come from the previous layer (i-1)
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run_out => open, ------- As only one output data validation is needed, the rest ones are left unconnected
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outputs => lidata(i-1)((NbitO(i-1)*(j+1))-1 downto NbitO(i-1)*j) -- Rest of the parallel inputs of this layer
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);
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end generate;
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end generate; -- multiple_activation_functions
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-- If the previous layer (i-1) has serial outputs and actual layer (i) has parallel inputs, a parallelizer
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-- is insested after the activation function (i-1):
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parallelizer:
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if (ltype_v(i-1)(2) = 'S') and (ltype_v(i)(1) = 'P') generate
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-- Instantiate single activation function of the previous layer (i-1):
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activation_function_inst: entity work.activation_function
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generic map
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(
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f_type => ftype_v(i-1),
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Nbit => NbitO(i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runO(i-1),
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inputs => lodata(i-1)(NbitO(i-1)-1 downto 0),
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run_out => runA(i-1),
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outputs => ladata(i-1)(NbitO(i-1)-1 downto 0)
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);
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-- Instantiate shift-register with parallel unload:
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shiftreg_parallel_unload: entity work.shiftreg_pu
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generic map
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(
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Nreg => NumN(i-1), --- Number of registers in the shift-register corresponds with the number of neurons in the previous layer (i-1)
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Nbit => NbitO(i-1) --- Bit width of the registers corresponds with the bit width of the outputs of the previous layer (i-1)
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)
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port map
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(
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reset => reset,
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clk => clk,
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run_in => runA(i-1), -- Input data validation comes from the activation function of the previous layer (i-1)
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inputs => ladata(i-1)(NbitO(i-1)-1 downto 0), -- Serial input data
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run_out => runO(i-1), -- Output data validation goes to the input data validation of this layer
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outputs => lodata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0) -- Parallel output data
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);
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end generate; -- parallelizer
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-- Instance the layer (i), cases SP, PS or PP:
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-- Serial-input parallel-output layer:
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SP_case:
|
308 |
|
|
if ltype_v(i) = "SP" generate
|
309 |
|
|
layerSP_top_inst: entity work.layerSP_top
|
310 |
|
|
generic map
|
311 |
|
|
(
|
312 |
|
|
NumN => NumN(i), --- Number of neurons in layer (i)
|
313 |
|
|
NumIn => NumN(i-1), -- Number of inputs, is the number of neurons in previous layer (i-1)
|
314 |
|
|
NbitIn => NbitO(i-1), -- Bit width of the input data, is the bit width of output data of layer (i-1)
|
315 |
|
|
NbitW => NbitW, ----- Bit width of weights and biases
|
316 |
|
|
NbitOut => NbitO(i), -- Bit width of layer (i) output
|
317 |
|
|
lra_l => lra_l(i), -- Layer RAM address length of layer (i)
|
318 |
|
|
wra_l => wra_l(i), -- Weight RAM address length of layer (i)
|
319 |
|
|
bra_l => bra_l(i), -- Bias RAM address length of layer (i)
|
320 |
|
|
LSbit => LSbit(i) --- Less significant bit of layer (i) outputs
|
321 |
|
|
)
|
322 |
|
|
port map
|
323 |
|
|
(
|
324 |
|
|
-- Input ports
|
325 |
|
|
reset => reset,
|
326 |
|
|
clk => clk,
|
327 |
|
|
run_in => runI(i-1), -- Input data validation of this layer
|
328 |
|
|
m_en => lm_en(i), -- Weight and bias memory enable of this layer
|
329 |
|
|
b_sel => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
|
330 |
|
|
m_we => m_we, ------ Weight and bias memory write enable
|
331 |
|
|
inputs => lidata(i-1)(NbitO(i-1)-1 downto 0), -- Inputs of this layer (serial data)
|
332 |
|
|
wdata => wdata, ----- Weight and bias memory write data
|
333 |
|
|
addr => addr(lra_l(i)-1 downto 0), -- Weight and bias memory address of this layer
|
334 |
|
|
|
335 |
|
|
-- Output ports
|
336 |
|
|
run_out => runO(i), -- Output data validation of this layer
|
337 |
|
|
rdata => lrdata(i), -- Weight and bias memory read data of this layer
|
338 |
|
|
outputs => lodata(i)((NumN(i)*NbitO(i))-1 downto 0) -- Outputs of this layer (parallel data)
|
339 |
|
|
);
|
340 |
|
|
end generate;
|
341 |
|
|
|
342 |
|
|
-- Parallel-input serial-output layer:
|
343 |
|
|
PS_case:
|
344 |
|
|
if ltype_v(i) = "PS" generate
|
345 |
|
|
layerPS_top_inst: entity work.layerPS_top
|
346 |
|
|
generic map
|
347 |
|
|
(
|
348 |
|
|
NumN => NumN(i), --- Number of neurons in layer (i)
|
349 |
|
|
NumIn => NumN(i-1), -- Number of inputs, is the number of neurons in previous layer (i-1)
|
350 |
|
|
NbitIn => NbitO(i-1), -- Bit width of the input data, is the bit width of output data of layer (i-1)
|
351 |
|
|
NbitW => NbitW, ----- Bit width of weights and biases
|
352 |
|
|
NbitOut => NbitO(i), -- Bit width of layer (i) output
|
353 |
|
|
lra_l => lra_l(i), -- Layer RAM address length of layer (i)
|
354 |
|
|
wra_l => wra_l(i), -- Weight RAM address length of layer (i)
|
355 |
|
|
bra_l => bra_l(i), -- Bias ram address length of layer (i)
|
356 |
|
|
LSbit => LSbit(i) --- Less significant bit of layer (i) outputs
|
357 |
|
|
)
|
358 |
|
|
port map
|
359 |
|
|
(
|
360 |
|
|
-- Input ports
|
361 |
|
|
reset => reset,
|
362 |
|
|
clk => clk,
|
363 |
|
|
run_in => runI(i-1), -- Input data validation of this layer
|
364 |
|
|
m_en => lm_en(i), -- Weight and bias memory enable of this layer
|
365 |
|
|
b_sel => addr((addr'length-log2(Nlayer))-1), -- Bias select. Selects between layer or bias memories
|
366 |
|
|
m_we => m_we, ------ Weight and bias memory write enable
|
367 |
|
|
inputs => lidata(i-1)((NumN(i-1)*NbitO(i-1))-1 downto 0), -- Inputs of this layer (parallel data)
|
368 |
|
|
wdata => wdata, ----- Weight and bias memory write data
|
369 |
|
|
addr => addr(lra_l(i)-1 downto 0), -- Weight and bias memory address of this layer
|
370 |
|
|
|
371 |
|
|
-- Output ports
|
372 |
|
|
run_out => runO(i), -- Output data validation of this layer
|
373 |
|
|
rdata => lrdata(i), -- Weight and bias memory read data of this layer
|
374 |
|
|
outputs => lodata(i)(NbitO(i)-1 downto 0) -- Outputs of this layer (serial data)
|
375 |
|
|
);
|
376 |
|
|
end generate;
|
377 |
|
|
|
378 |
|
|
-- Parallel-input parallel-output layer:
|
379 |
|
|
PP_case:
|
380 |
|
|
if ltype_v(i) = "PP" generate
|
381 |
|
|
-- TODO: instance a full parallel layer. At current version this layer type has not been developed.
|
382 |
|
|
-- synthesis translate_off
|
383 |
|
|
assert l_type(i) /= "PP"
|
384 |
|
|
report "Current version does not accept parallel-input parallel-output (PP) layer type."
|
385 |
|
|
severity failure;
|
386 |
|
|
-- synthesis translate_on
|
387 |
|
|
-- TODO: delete above lines when instantiate the parallel-input parallel-output layer.
|
388 |
|
|
end generate;
|
389 |
|
|
|
390 |
|
|
end generate; -- layers_insts
|
391 |
|
|
|
392 |
|
|
-- If the last layer (Nlayer-1) has parallel outputs, a serializer is inserted before the activation function:
|
393 |
|
|
last_serializer:
|
394 |
|
|
if (ltype_v(Nlayer-1)(2) = 'P') generate
|
395 |
|
|
|
396 |
|
|
-- Instantiate shift-register with parallel load:
|
397 |
|
|
last_shiftreg_parallel_load: entity work.shiftreg_pl
|
398 |
|
|
generic map
|
399 |
|
|
(
|
400 |
|
|
Nreg => NumN(Nlayer-1), --- Number of registers corresponds with the number of neurons in the last layer (Nlayer-1)
|
401 |
|
|
Nbit => NbitO(Nlayer-1) --- Bit width of the registers corresponds with the bit width of the outputs of the last layer (Nlayer-1)
|
402 |
|
|
)
|
403 |
|
|
port map
|
404 |
|
|
(
|
405 |
|
|
reset => reset,
|
406 |
|
|
clk => clk,
|
407 |
|
|
run_in => runO(Nlayer-1), -- Input data validation comes from the output data validation of the last layer (Nlayer-1)
|
408 |
|
|
inputs => lodata(Nlayer-1)((NumN(Nlayer-1)*NbitO(Nlayer-1))-1 downto 0), -- Parallel input data come from the last layer
|
409 |
|
|
run_out => runA(Nlayer-1), -- Output data validation goes to the last activation function (Nlayer-1)
|
410 |
|
|
outputs => ladata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0) -- Serial output data go to the last activation function
|
411 |
|
|
);
|
412 |
|
|
|
413 |
|
|
last_activation_function_inst: entity work.activation_function
|
414 |
|
|
generic map
|
415 |
|
|
(
|
416 |
|
|
f_type => ftype_v(Nlayer-1), -- Activation function type of the last layer (Nlayer-1)
|
417 |
|
|
Nbit => NbitO(Nlayer-1) --- Bit width of the outputs of the last layer (Nlayer-1)
|
418 |
|
|
)
|
419 |
|
|
port map
|
420 |
|
|
(
|
421 |
|
|
reset => reset,
|
422 |
|
|
clk => clk,
|
423 |
|
|
run_in => runA(Nlayer-1), -- Input data validation comes from the shift-register output validation
|
424 |
|
|
inputs => ladata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0), -- Serial input data come from the shift-register
|
425 |
|
|
run_out => run_out, --------- Output data validation of the network
|
426 |
|
|
outputs => outputs ---------- Outputs of the network (serial data)
|
427 |
|
|
);
|
428 |
|
|
|
429 |
|
|
end generate; -- last_serializer
|
430 |
|
|
|
431 |
|
|
-- If the las layer has serial outputs:
|
432 |
|
|
last_simple_activation_function:
|
433 |
|
|
if (ltype_v(Nlayer-1)(2) = 'S') generate
|
434 |
|
|
last_activation_function_inst: entity work.activation_function
|
435 |
|
|
generic map
|
436 |
|
|
(
|
437 |
|
|
f_type => ftype_v(Nlayer-1), -- Activation function type of the last layer (Nlayer-1)
|
438 |
|
|
Nbit => NbitO(Nlayer-1) --- Bit width of the outputs of the last layer (Nlayer-1)
|
439 |
|
|
)
|
440 |
|
|
port map
|
441 |
|
|
(
|
442 |
|
|
reset => reset,
|
443 |
|
|
clk => clk,
|
444 |
|
|
run_in => runO(Nlayer-1), -- Input data validation comes from the last layer (Nlayer-1) output validation
|
445 |
|
|
inputs => lodata(Nlayer-1)(NbitO(Nlayer-1)-1 downto 0), -- Inputs come from the outputs of the last layer (serial data)
|
446 |
|
|
run_out => run_out, --------- Output data validation of the network
|
447 |
|
|
outputs => outputs ---------- Outputs of the network (serial data)
|
448 |
|
|
);
|
449 |
|
|
end generate;
|
450 |
|
|
|
451 |
|
|
end config_structural;
|