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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [CacheSystem2.vhd] - Blame information for rev 2

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity CacheSystem2 is
  generic (
        DATA_WIDTH : integer := 8;
        WINDOW_SIZE : integer := 3;
        ROW_BITS : integer := 9;
        COL_BITS : integer := 10;
        NO_OF_ROWS : integer := 480;
        NO_OF_COLS : integer := 640
        );
  port(
        clk : in std_logic;
        fsync_in : in std_logic;
        Xdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
        Ydata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
        --fsync_out : out std_logic;
        pdata_out1x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out2x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out3x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out4x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out5x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out6x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out7x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out8x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out9x : out std_logic_vector(DATA_WIDTH -1 downto 0);
        --
        pdata_out1y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out2y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out3y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out4y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out5y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out6y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out7y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out8y : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out9y : out std_logic_vector(DATA_WIDTH -1 downto 0)
        );
  end CacheSystem2;
 
 
architecture CacheSystem2 of CacheSystem2 is
 
--COMPONENT Counter is
--  generic (
--    n : POSITIVE
--      );
--  port ( 
--    clk : in STD_LOGIC;
--      en : in STD_LOGIC;
--      reset : in STD_LOGIC; -- Active Low
--      output : out STD_LOGIC_VECTOR(n-1 downto 0)
--      );
--end COMPONENT;
 
COMPONENT nineFiFOLineBuffer is
  generic (
        DATA_WIDTH : integer := DATA_WIDTH;
        NO_OF_COLS : integer := 640
        );
  port(
        clk : in std_logic;
        fsync : in std_logic;
        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
        pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
        );
end COMPONENT;
 
--COMPONENT SyncSignalsDelayer
--  generic (
--      ROW_BITS : integer := 9;
--      COL_BITS : integer := 10;
--      NO_OF_ROWS : integer := 480;
--      NO_OF_COLS : integer := 640
--      );
--  port(
--      clk : IN std_logic;
--      fsync_in : IN std_logic;
--      fsync_out : OUT std_logic
--      );
--end COMPONENT;
 
--signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);
--signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);
--
signal dout1x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout2x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout3x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout4x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout5x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout6x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout7x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout8x : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout9x : std_logic_vector(DATA_WIDTH -1 downto 0);
--
signal dout1y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout2y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout3y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout4y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout5y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout6y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout7y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout8y : std_logic_vector(DATA_WIDTH -1 downto 0);
signal dout9y : std_logic_vector(DATA_WIDTH -1 downto 0);
--
--signal fsync_temp : std_logic;
--
--constant LATENCY : integer := NO_OF_COLS*4;
--signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency
 
 
begin
 
  --fsync_out <= fsync_temp;
 
--  fsync_delayer : FIFOLineBuffer
--      generic map (
--        DATA_WIDTH => 1,
--        NO_OF_COLS => NO_OF_COLS*4
--        )
--      port map(
--        clk => clk,
--        fsync => fsync_buffer,
--        pdata_in(0) => fsync_in,
--      pdata_out(0) => fsync_temp
--        );
 
--  fsync_delayer : process (clk)
--  begin
--      if rising_edge(clk) then
--        fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
--        fsync_temp <= fsync_store(LATENCY-1);
--      end if;
--  end process fsync_delayer;
--  
--  fsync_buffer <= fsync_in OR fsync_temp;
 
  nineLineBufferX: nineFiFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map (
          clk => clk,
          fsync => fsync_in,
          pdata_in => xdata_in,
          pdata_out1 => dout1x,
          pdata_out2 => dout2x,
          pdata_out3 => dout3x,
          pdata_out4 => dout4x,
          pdata_out5 => dout5x,
          pdata_out6 => dout6x,
          pdata_out7 => dout7x,
          pdata_out8 => dout8x,
          pdata_out9 => dout9x
          );
 
  nineLineBufferY: nineFiFOLineBuffer
        generic map (
          DATA_WIDTH => DATA_WIDTH,
          NO_OF_COLS => NO_OF_COLS
          )
        port map (
          clk => clk,
          fsync => fsync_in,
          pdata_in => ydata_in,
          pdata_out1 => dout1y,
          pdata_out2 => dout2y,
          pdata_out3 => dout3y,
          pdata_out4 => dout4y,
          pdata_out5 => dout5y,
          pdata_out6 => dout6y,
          pdata_out7 => dout7y,
          pdata_out8 => dout8y,
          pdata_out9 => dout9y
          );
 
--  update_reg : process (clk)
--  begin 
--    if rising_edge(clk) then
--        RowsCounter_r <= RowsCounter_x;
--      ColsCounter_r <= ColsCounter_x;
--      end if;
--  end process update_reg;
--  
--  counter : process (clk, fsync_temp)
--  begin
--    --RowsCounter_x <= RowsCounter_r;
--    --ColsCounter_x <= ColsCounter_r;
--      if(clk'event and clk = '1') then
--        if(fsync_temp = '0') then
--          RowsCounter_x <= (others => '0');
--          ColsCounter_x <= (others => '0');
--        elsif ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
--          ColsCounter_x <= ColsCounter_r + 1;
--        else
--          RowsCounter_x <= RowsCounter_r + 1;
--              ColsCounter_x <= (others => '0');
--        end if;
--    end if;
--  end process counter;
 
 
  EmittingProcess : process (clk)
  begin
 
    if rising_edge(clk) then
        if fsync_in = '1' then
 
 
--        if RowsCounter_r = "0000000000" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-1, ROW_BITS)) then 
--          pdata_out1x <= dout5x;
--              pdata_out2x <= dout5x;
--              pdata_out3x <= dout5x;
--        pdata_out4x <= dout5x;
--              pdata_out5x <= dout5x;
--              pdata_out6x <= dout4x;
--              pdata_out7x <= dout3x;
--              pdata_out8x <= dout2x;
--              pdata_out9x <= dout1x;    
--          --
--          pdata_out1y <= dout5y;
--              pdata_out2y <= dout5y;
--              pdata_out3y <= dout5y;
--        pdata_out4y <= dout5y;
--              pdata_out5y <= dout5y;
--              pdata_out6y <= dout4y;
--              pdata_out7y <= dout3y;
--              pdata_out8y <= dout2y;
--              pdata_out9y <= dout1y;  
--              
--        elsif RowsCounter_r = "0000000001" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-2, ROW_BITS)) then 
--          pdata_out1x <= dout6x;
--              pdata_out2x <= dout6x;
--              pdata_out3x <= dout6x;
--        pdata_out4x <= dout6x;
--              pdata_out5x <= dout5x;
--              pdata_out6x <= dout4x;
--              pdata_out7x <= dout3x;
--              pdata_out8x <= dout2x;
--              pdata_out9x <= dout1x;    
--          --
--          pdata_out1y <= dout6y;
--              pdata_out2y <= dout6y;
--              pdata_out3y <= dout6y;
--        pdata_out4y <= dout6y;
--              pdata_out5y <= dout5y;
--              pdata_out6y <= dout4y;
--              pdata_out7y <= dout3y;
--              pdata_out8y <= dout2y;
--              pdata_out9y <= dout1y;  
--              
--        elsif RowsCounter_r = "0000000010" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-3, ROW_BITS)) then 
--          pdata_out1x <= dout7x;
--              pdata_out2x <= dout7x;
--              pdata_out3x <= dout7x;
--        pdata_out4x <= dout6x;
--              pdata_out5x <= dout5x;
--              pdata_out6x <= dout4x;
--              pdata_out7x <= dout3x;
--              pdata_out8x <= dout2x;
--              pdata_out9x <= dout1x;    
--          --
--          pdata_out1y <= dout7y;
--              pdata_out2y <= dout7y;
--              pdata_out3y <= dout7y;
--        pdata_out4y <= dout6y;
--              pdata_out5y <= dout5y;
--              pdata_out6y <= dout4y;
--              pdata_out7y <= dout3y;
--              pdata_out8y <= dout2y;
--              pdata_out9y <= dout1y;  
--              
--        elsif RowsCounter_r = "0000000011" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-4, ROW_BITS)) then 
--          pdata_out1x <= dout8x;
--              pdata_out2x <= dout8x;
--              pdata_out3x <= dout7x;
--        pdata_out4x <= dout6x;
--              pdata_out5x <= dout5x;
--              pdata_out6x <= dout4x;
--              pdata_out7x <= dout3x;
--              pdata_out8x <= dout2x;
--              pdata_out9x <= dout1x;    
--          --
--          pdata_out1y <= dout8y;
--              pdata_out2y <= dout8y;
--              pdata_out3y <= dout7y;
--        pdata_out4y <= dout6y;
--              pdata_out5y <= dout5y;
--              pdata_out6y <= dout4y;
--              pdata_out7y <= dout3y;
--              pdata_out8y <= dout2y;
--              pdata_out9y <= dout1y;
--        
--        else
           pdata_out1x <= dout9x;
                pdata_out2x <= dout8x;
                pdata_out3x <= dout7x;
      pdata_out4x <= dout6x;
                pdata_out5x <= dout5x;
                pdata_out6x <= dout4x;
                pdata_out7x <= dout3x;
                pdata_out8x <= dout2x;
                pdata_out9x <= dout1x;
            --
           pdata_out1y <= dout9y;
                pdata_out2y <= dout8y;
                pdata_out3y <= dout7y;
      pdata_out4y <= dout6y;
                pdata_out5y <= dout5y;
                pdata_out6y <= dout4y;
                pdata_out7y <= dout3y;
                pdata_out8y <= dout2y;
                pdata_out9y <= dout1y;
 
        end if;
 
        --else
 
--        pdata_out1x <= (others =>'0');
--        pdata_out2x <= (others =>'0');
--        pdata_out3x <= (others =>'0');
--        pdata_out4x <= (others =>'0');
--        pdata_out5x <= (others =>'0');
--        pdata_out6x <= (others =>'0');
--        pdata_out7x <= (others =>'0');
--        pdata_out8x <= (others =>'0');
--        pdata_out9x <= (others =>'0');
--        --
--        pdata_out1y <= (others =>'0');
--        pdata_out2y <= (others =>'0');
--        pdata_out3y <= (others =>'0');
--        pdata_out4y <= (others =>'0');
--        pdata_out5y <= (others =>'0');
--        pdata_out6y <= (others =>'0');
--        pdata_out7y <= (others =>'0');
--        pdata_out8y <= (others =>'0');
--        pdata_out9y <= (others =>'0');
        end if; --clk   
        --end if; --rsync_temp
  end process EmittingProcess;
end CacheSystem2;
 

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Subversion Repositories canny_edge_detector

[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [CacheSystem2.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	angelobacc	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`USE ieee.numeric_std.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6
7			`entity CacheSystem2 is`
8			`generic (`
9			`DATA_WIDTH : integer := 8;`
10			`WINDOW_SIZE : integer := 3;`
11			`ROW_BITS : integer := 9;`
12			`COL_BITS : integer := 10;`
13			`NO_OF_ROWS : integer := 480;`
14			`NO_OF_COLS : integer := 640`
15			`);`
16			`port(`
17			`clk : in std_logic;`
18			`fsync_in : in std_logic;`
19			`Xdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);`
20			`Ydata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);`
21			`--fsync_out : out std_logic;`
22			`pdata_out1x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
23			`pdata_out2x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
24			`pdata_out3x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
25			`pdata_out4x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
26			`pdata_out5x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
27			`pdata_out6x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
28			`pdata_out7x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
29			`pdata_out8x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
30			`pdata_out9x : out std_logic_vector(DATA_WIDTH -1 downto 0);`
31			`--`
32			`pdata_out1y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
33			`pdata_out2y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
34			`pdata_out3y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
35			`pdata_out4y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
36			`pdata_out5y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
37			`pdata_out6y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
38			`pdata_out7y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
39			`pdata_out8y : out std_logic_vector(DATA_WIDTH -1 downto 0);`
40			`pdata_out9y : out std_logic_vector(DATA_WIDTH -1 downto 0)`
41			`);`
42			`end CacheSystem2;`
43
44
45			`architecture CacheSystem2 of CacheSystem2 is`
46
47			`--COMPONENT Counter is`
48			`-- generic (`
49			`-- n : POSITIVE`
50			`-- );`
51			`-- port (`
52			`-- clk : in STD_LOGIC;`
53			`-- en : in STD_LOGIC;`
54			`-- reset : in STD_LOGIC; -- Active Low`
55			`-- output : out STD_LOGIC_VECTOR(n-1 downto 0)`
56			`-- );`
57			`--end COMPONENT;`
58
59			`COMPONENT nineFiFOLineBuffer is`
60			`generic (`
61			`DATA_WIDTH : integer := DATA_WIDTH;`
62			`NO_OF_COLS : integer := 640`
63			`);`
64			`port(`
65			`clk : in std_logic;`
66			`fsync : in std_logic;`
67			`pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);`
68			`pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);`
69			`pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
70			`pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
71			`pdata_out4 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
72			`pdata_out5 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
73			`pdata_out6 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
74			`pdata_out7 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
75			`pdata_out8 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);`
76			`pdata_out9 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)`
77			`);`
78			`end COMPONENT;`
79
80			`--COMPONENT SyncSignalsDelayer`
81			`-- generic (`
82			`-- ROW_BITS : integer := 9;`
83			`-- COL_BITS : integer := 10;`
84			`-- NO_OF_ROWS : integer := 480;`
85			`-- NO_OF_COLS : integer := 640`
86			`-- );`
87			`-- port(`
88			`-- clk : IN std_logic;`
89			`-- fsync_in : IN std_logic;`
90			`-- fsync_out : OUT std_logic`
91			`-- );`
92			`--end COMPONENT;`
93
94			`--signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);`
95			`--signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);`
96			`--`
97			`signal dout1x : std_logic_vector(DATA_WIDTH -1 downto 0);`
98			`signal dout2x : std_logic_vector(DATA_WIDTH -1 downto 0);`
99			`signal dout3x : std_logic_vector(DATA_WIDTH -1 downto 0);`
100			`signal dout4x : std_logic_vector(DATA_WIDTH -1 downto 0);`
101			`signal dout5x : std_logic_vector(DATA_WIDTH -1 downto 0);`
102			`signal dout6x : std_logic_vector(DATA_WIDTH -1 downto 0);`
103			`signal dout7x : std_logic_vector(DATA_WIDTH -1 downto 0);`
104			`signal dout8x : std_logic_vector(DATA_WIDTH -1 downto 0);`
105			`signal dout9x : std_logic_vector(DATA_WIDTH -1 downto 0);`
106			`--`
107			`signal dout1y : std_logic_vector(DATA_WIDTH -1 downto 0);`
108			`signal dout2y : std_logic_vector(DATA_WIDTH -1 downto 0);`
109			`signal dout3y : std_logic_vector(DATA_WIDTH -1 downto 0);`
110			`signal dout4y : std_logic_vector(DATA_WIDTH -1 downto 0);`
111			`signal dout5y : std_logic_vector(DATA_WIDTH -1 downto 0);`
112			`signal dout6y : std_logic_vector(DATA_WIDTH -1 downto 0);`
113			`signal dout7y : std_logic_vector(DATA_WIDTH -1 downto 0);`
114			`signal dout8y : std_logic_vector(DATA_WIDTH -1 downto 0);`
115			`signal dout9y : std_logic_vector(DATA_WIDTH -1 downto 0);`
116			`--`
117			`--signal fsync_temp : std_logic;`
118			`--`
119			`--constant LATENCY : integer := NO_OF_COLS*4;`
120			`--signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency`
121
122
123			`begin`
124
125			`--fsync_out <= fsync_temp;`
126
127			`-- fsync_delayer : FIFOLineBuffer`
128			`-- generic map (`
129			`-- DATA_WIDTH => 1,`
130			`-- NO_OF_COLS => NO_OF_COLS*4`
131			`-- )`
132			`-- port map(`
133			`-- clk => clk,`
134			`-- fsync => fsync_buffer,`
135			`-- pdata_in(0) => fsync_in,`
136			`-- pdata_out(0) => fsync_temp`
137			`-- );`
138
139			`-- fsync_delayer : process (clk)`
140			`-- begin`
141			`-- if rising_edge(clk) then`
142			`-- fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;`
143			`-- fsync_temp <= fsync_store(LATENCY-1);`
144			`-- end if;`
145			`-- end process fsync_delayer;`
146			`--`
147			`-- fsync_buffer <= fsync_in OR fsync_temp;`
148
149			`nineLineBufferX: nineFiFOLineBuffer`
150			`generic map (`
151			`DATA_WIDTH => DATA_WIDTH,`
152			`NO_OF_COLS => NO_OF_COLS`
153			`)`
154			`port map (`
155			`clk => clk,`
156			`fsync => fsync_in,`
157			`pdata_in => xdata_in,`
158			`pdata_out1 => dout1x,`
159			`pdata_out2 => dout2x,`
160			`pdata_out3 => dout3x,`
161			`pdata_out4 => dout4x,`
162			`pdata_out5 => dout5x,`
163			`pdata_out6 => dout6x,`
164			`pdata_out7 => dout7x,`
165			`pdata_out8 => dout8x,`
166			`pdata_out9 => dout9x`
167			`);`
168
169			`nineLineBufferY: nineFiFOLineBuffer`
170			`generic map (`
171			`DATA_WIDTH => DATA_WIDTH,`
172			`NO_OF_COLS => NO_OF_COLS`
173			`)`
174			`port map (`
175			`clk => clk,`
176			`fsync => fsync_in,`
177			`pdata_in => ydata_in,`
178			`pdata_out1 => dout1y,`
179			`pdata_out2 => dout2y,`
180			`pdata_out3 => dout3y,`
181			`pdata_out4 => dout4y,`
182			`pdata_out5 => dout5y,`
183			`pdata_out6 => dout6y,`
184			`pdata_out7 => dout7y,`
185			`pdata_out8 => dout8y,`
186			`pdata_out9 => dout9y`
187			`);`
188
189			`-- update_reg : process (clk)`
190			`-- begin`
191			`-- if rising_edge(clk) then`
192			`-- RowsCounter_r <= RowsCounter_x;`
193			`-- ColsCounter_r <= ColsCounter_x;`
194			`-- end if;`
195			`-- end process update_reg;`
196			`--`
197			`-- counter : process (clk, fsync_temp)`
198			`-- begin`
199			`-- --RowsCounter_x <= RowsCounter_r;`
200			`-- --ColsCounter_x <= ColsCounter_r;`
201			`-- if(clk'event and clk = '1') then`
202			`-- if(fsync_temp = '0') then`
203			`-- RowsCounter_x <= (others => '0');`
204			`-- ColsCounter_x <= (others => '0');`
205			`-- elsif ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then`
206			`-- ColsCounter_x <= ColsCounter_r + 1;`
207			`-- else`
208			`-- RowsCounter_x <= RowsCounter_r + 1;`
209			`-- ColsCounter_x <= (others => '0');`
210			`-- end if;`
211			`-- end if;`
212			`-- end process counter;`
213
214
215			`EmittingProcess : process (clk)`
216			`begin`
217
218			`if rising_edge(clk) then`
219			`if fsync_in = '1' then`
220
221
222			`-- if RowsCounter_r = "0000000000" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-1, ROW_BITS)) then`
223			`-- pdata_out1x <= dout5x;`
224			`-- pdata_out2x <= dout5x;`
225			`-- pdata_out3x <= dout5x;`
226			`-- pdata_out4x <= dout5x;`
227			`-- pdata_out5x <= dout5x;`
228			`-- pdata_out6x <= dout4x;`
229			`-- pdata_out7x <= dout3x;`
230			`-- pdata_out8x <= dout2x;`
231			`-- pdata_out9x <= dout1x;`
232			`-- --`
233			`-- pdata_out1y <= dout5y;`
234			`-- pdata_out2y <= dout5y;`
235			`-- pdata_out3y <= dout5y;`
236			`-- pdata_out4y <= dout5y;`
237			`-- pdata_out5y <= dout5y;`
238			`-- pdata_out6y <= dout4y;`
239			`-- pdata_out7y <= dout3y;`
240			`-- pdata_out8y <= dout2y;`
241			`-- pdata_out9y <= dout1y;`
242			`--`
243			`-- elsif RowsCounter_r = "0000000001" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-2, ROW_BITS)) then`
244			`-- pdata_out1x <= dout6x;`
245			`-- pdata_out2x <= dout6x;`
246			`-- pdata_out3x <= dout6x;`
247			`-- pdata_out4x <= dout6x;`
248			`-- pdata_out5x <= dout5x;`
249			`-- pdata_out6x <= dout4x;`
250			`-- pdata_out7x <= dout3x;`
251			`-- pdata_out8x <= dout2x;`
252			`-- pdata_out9x <= dout1x;`
253			`-- --`
254			`-- pdata_out1y <= dout6y;`
255			`-- pdata_out2y <= dout6y;`
256			`-- pdata_out3y <= dout6y;`
257			`-- pdata_out4y <= dout6y;`
258			`-- pdata_out5y <= dout5y;`
259			`-- pdata_out6y <= dout4y;`
260			`-- pdata_out7y <= dout3y;`
261			`-- pdata_out8y <= dout2y;`
262			`-- pdata_out9y <= dout1y;`
263			`--`
264			`-- elsif RowsCounter_r = "0000000010" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-3, ROW_BITS)) then`
265			`-- pdata_out1x <= dout7x;`
266			`-- pdata_out2x <= dout7x;`
267			`-- pdata_out3x <= dout7x;`
268			`-- pdata_out4x <= dout6x;`
269			`-- pdata_out5x <= dout5x;`
270			`-- pdata_out6x <= dout4x;`
271			`-- pdata_out7x <= dout3x;`
272			`-- pdata_out8x <= dout2x;`
273			`-- pdata_out9x <= dout1x;`
274			`-- --`
275			`-- pdata_out1y <= dout7y;`
276			`-- pdata_out2y <= dout7y;`
277			`-- pdata_out3y <= dout7y;`
278			`-- pdata_out4y <= dout6y;`
279			`-- pdata_out5y <= dout5y;`
280			`-- pdata_out6y <= dout4y;`
281			`-- pdata_out7y <= dout3y;`
282			`-- pdata_out8y <= dout2y;`
283			`-- pdata_out9y <= dout1y;`
284			`--`
285			`-- elsif RowsCounter_r = "0000000011" OR RowsCounter_r = std_logic_vector(to_unsigned(NO_OF_ROWS-4, ROW_BITS)) then`
286			`-- pdata_out1x <= dout8x;`
287			`-- pdata_out2x <= dout8x;`
288			`-- pdata_out3x <= dout7x;`
289			`-- pdata_out4x <= dout6x;`
290			`-- pdata_out5x <= dout5x;`
291			`-- pdata_out6x <= dout4x;`
292			`-- pdata_out7x <= dout3x;`
293			`-- pdata_out8x <= dout2x;`
294			`-- pdata_out9x <= dout1x;`
295			`-- --`
296			`-- pdata_out1y <= dout8y;`
297			`-- pdata_out2y <= dout8y;`
298			`-- pdata_out3y <= dout7y;`
299			`-- pdata_out4y <= dout6y;`
300			`-- pdata_out5y <= dout5y;`
301			`-- pdata_out6y <= dout4y;`
302			`-- pdata_out7y <= dout3y;`
303			`-- pdata_out8y <= dout2y;`
304			`-- pdata_out9y <= dout1y;`
305			`--`
306			`-- else`
307			`pdata_out1x <= dout9x;`
308			`pdata_out2x <= dout8x;`
309			`pdata_out3x <= dout7x;`
310			`pdata_out4x <= dout6x;`
311			`pdata_out5x <= dout5x;`
312			`pdata_out6x <= dout4x;`
313			`pdata_out7x <= dout3x;`
314			`pdata_out8x <= dout2x;`
315			`pdata_out9x <= dout1x;`
316			`--`
317			`pdata_out1y <= dout9y;`
318			`pdata_out2y <= dout8y;`
319			`pdata_out3y <= dout7y;`
320			`pdata_out4y <= dout6y;`
321			`pdata_out5y <= dout5y;`
322			`pdata_out6y <= dout4y;`
323			`pdata_out7y <= dout3y;`
324			`pdata_out8y <= dout2y;`
325			`pdata_out9y <= dout1y;`
326
327			`end if;`
328
329			`--else`
330
331			`-- pdata_out1x <= (others =>'0');`
332			`-- pdata_out2x <= (others =>'0');`
333			`-- pdata_out3x <= (others =>'0');`
334			`-- pdata_out4x <= (others =>'0');`
335			`-- pdata_out5x <= (others =>'0');`
336			`-- pdata_out6x <= (others =>'0');`
337			`-- pdata_out7x <= (others =>'0');`
338			`-- pdata_out8x <= (others =>'0');`
339			`-- pdata_out9x <= (others =>'0');`
340			`-- --`
341			`-- pdata_out1y <= (others =>'0');`
342			`-- pdata_out2y <= (others =>'0');`
343			`-- pdata_out3y <= (others =>'0');`
344			`-- pdata_out4y <= (others =>'0');`
345			`-- pdata_out5y <= (others =>'0');`
346			`-- pdata_out6y <= (others =>'0');`
347			`-- pdata_out7y <= (others =>'0');`
348			`-- pdata_out8y <= (others =>'0');`
349			`-- pdata_out9y <= (others =>'0');`
350			`end if; --clk`
351			`--end if; --rsync_temp`
352			`end process EmittingProcess;`
353			`end CacheSystem2;`
354