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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [CacheSystem3.vhd] - Blame information for rev 2

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1 2 angelobacc 
library IEEE;
2 
use IEEE.STD_LOGIC_1164.ALL;
3 
USE ieee.numeric_std.ALL;
4 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5 
 
6 
 
7 
entity CacheSystem3 is
8 
  generic (
9 
        DATA_WIDTH : integer := 8;
10 
        WINDOW_SIZE : integer := 3;
11 
        ROW_BITS : integer := 9;
12 
        COL_BITS : integer := 10;
13 
        NO_OF_ROWS : integer := 480;
14 
        NO_OF_COLS : integer := 640
15 
        );
16 
  port(
17 
        clk : in std_logic;
18 
        fsync_in : in std_logic;
19 
        mData_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
20 
        dData_in : in std_logic_vector(1 downto 0);
21 
        --fsync_out : out std_logic;
22 
        pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
23 
        pdata_out2 : out std_logic_vector(DATA_WIDTH -1 downto 0);
24 
        pdata_out3 : out std_logic_vector(DATA_WIDTH -1 downto 0);
25 
        pdata_out4 : out std_logic_vector(DATA_WIDTH -1 downto 0);
26 
        pdata_out5 : out std_logic_vector(DATA_WIDTH -1 downto 0);
27 
        pdata_out6 : out std_logic_vector(DATA_WIDTH -1 downto 0);
28 
        pdata_out7 : out std_logic_vector(DATA_WIDTH -1 downto 0);
29 
        pdata_out8 : out std_logic_vector(DATA_WIDTH -1 downto 0);
30 
        pdata_out9 : out std_logic_vector(DATA_WIDTH -1 downto 0);
31 
        dData_out  : out std_logic_vector(1 downto 0)
32 
        );
33 
  end CacheSystem3;
34 
 
35 
 
36 
architecture CacheSystem3 of CacheSystem3 is
37 
 
38 
 
39 
COMPONENT DoubleFiFOLineBuffer is
40 
  generic (
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        DATA_WIDTH : integer := 8;
42 
        NO_OF_COLS : integer := 640
43 
        );
44 
  port(
45 
        clk : in std_logic;
46 
        fsync : in std_logic;
47 
        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
48 
        pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0);
49 
        pdata_out2 : buffer std_logic_vector(DATA_WIDTH -1 downto 0);
50 
        pdata_out3 : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
51 
        );
52 
end COMPONENT;
53 
 
54 
component FIFOLineBuffer is
55 
  generic (
56 
        DATA_WIDTH : integer := 8;
57 
        NO_OF_COLS : integer := 640
58 
        );
59 
  port(
60 
        clk : in std_logic;
61 
        fsync : in std_logic;
62 
        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
63 
        pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0));
64 
  end component;
65 
 
66 
--signal RowsCounter_r, RowsCounter_x : STD_LOGIC_VECTOR(ROW_BITS-1 downto 0);
67 
--signal ColsCounter_r, ColsCounter_x : STD_LOGIC_VECTOR(COL_BITS-1 downto 0);
68 
 
69 
signal dout1 : std_logic_vector(DATA_WIDTH -1 downto 0);
70 
signal dout2 : std_logic_vector(DATA_WIDTH -1 downto 0);
71 
signal dout3 : std_logic_vector(DATA_WIDTH -1 downto 0);
72 
 
73 
signal dData_temp : std_logic_vector(1 downto 0);
74 
 
75 
 
76 
signal cache1 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
77 
signal cache2 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
78 
signal cache3 : std_logic_vector((WINDOW_SIZE*DATA_WIDTH) -1 downto 0);
79 
 
80 
--constant LATENCY : integer := NO_OF_COLS+2;
81 
--signal fsync_store : std_logic_vector(LATENCY - 1 downto 0); -- clock cycles delay to compensate for latency
82 
 
83 
begin
84 
 
85 
 
86 
--
87 
--  fsync_out <= fsync_temp;
88 
--  --fsync_buffer <= fsync_in OR fsync_temp;
89 
--
90 
--  fsync_delayer : process (clk)
91 
--  begin
92 
--      if rising_edge(clk) then
93 
--        fsync_store <= fsync_store(LATENCY-2 downto 0) & fsync_in;
94 
--        fsync_temp <= fsync_store(LATENCY-1);
95 
--      end if;
96 
--  end process fsync_delayer;
97 
 
98 
  DoubleLineBufferMag: DoubleFiFOLineBuffer
99 
        generic map (
100 
          DATA_WIDTH => DATA_WIDTH,
101 
          NO_OF_COLS => NO_OF_COLS
102 
          )
103 
        port map (
104 
          clk => clk,
105 
          fsync => fsync_in,--fsync_buffer,
106 
          pdata_in => mdata_in,
107 
          pdata_out1 => dout1,
108 
          pdata_out2 => dout2,
109 
          pdata_out3 => dout3
110 
          );
111 
 
112 
  dDataBuffer1 : FIFOLineBuffer
113 
        generic map (
114 
          DATA_WIDTH => 2,
115 
          NO_OF_COLS => NO_OF_COLS+2+1
116 
          )
117 
        port map(clk, fsync_in, dData_in, dData_temp);
118 
 
119 
 
120 
--  update_reg : process (clk)
121 
--  begin
122 
--    if(clk'event and clk = '1') then
123 
--        RowsCounter_r <= RowsCounter_x;
124 
--      ColsCounter_r <= ColsCounter_x;
125 
--      end if;
126 
--  end process update_reg;
127 
--
128 
--  counter : process (clk, fsync_temp)
129 
--  begin
130 
--    --RowsCounter_x <= RowsCounter_r;
131 
--    --ColsCounter_x <= ColsCounter_r;
132 
--      if(clk'event and clk = '1') then
133 
--        if(fsync_temp = '0') then
134 
--          RowsCounter_x <= (others => '0');
135 
--          ColsCounter_x <= (others => '0');
136 
--        elsif ColsCounter_r /= std_logic_vector(to_unsigned(NO_OF_COLS-1, COL_BITS)) then
137 
--          ColsCounter_x <= ColsCounter_r + 1;
138 
--        else
139 
--          RowsCounter_x <= RowsCounter_r + 1;
140 
--              ColsCounter_x <= (others => '0');
141 
--        end if;
142 
--    end if;
143 
--  end process counter;
144 
 
145 
 
146 
 
147 
  --fsync_out <= fsync_temp;
148 
 
149 
  ShiftingProcess : process (clk, fsync_in)
150 
  begin
151 
 
152 
        if rising_edge(clk) then
153 
            if fsync_in = '1' then
154 
          -- the pixel in the middle part is copied into the low part
155 
          cache1(DATA_WIDTH-1 downto 0) <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
156 
          cache2(DATA_WIDTH-1 downto 0) <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
157 
          cache3(DATA_WIDTH-1 downto 0) <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
158 
          -- the pixel in the high part is copied into the middle part
159 
          cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache1((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
160 
          cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache2((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
161 
          cache3(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH) ) <= cache3((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH));
162 
          -- the output of the ram is put in the high part of the variable
163 
          cache1((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout1;
164 
          cache2((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout2;
165 
          cache3((WINDOW_SIZE*DATA_WIDTH)-1 downto ((WINDOW_SIZE-1)*DATA_WIDTH)) <= dout3;
166 
        end if; -- clk
167 
        end if;
168 
  end process ShiftingProcess;
169 
 
170 
  EmittingProcess : process (clk)
171 
  begin
172 
 
173 
 
174 
        if rising_edge(clk) then
175 
    if fsync_in = '1' then
176 
      dData_out <= dData_temp;
177 
          -- 1 top left
178 
--        if RowsCounter_r = "000000000" and ColsCounter_r = "0000000000" then
179 
--              pdata_out1 <= (others => '0');
180 
--              pdata_out2 <= (others => '0');
181 
--              pdata_out3 <= (others => '0');
182 
--              pdata_out4 <= (others => '0');
183 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
184 
--              pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
185 
--              pdata_out7 <= (others => '0');
186 
--              pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
187 
--              pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
188 
--
189 
--        -- counter2>0 and counter2<639 (2) top
190 
--        elsif RowsCounter_r = "000000000" and ColsCounter_r > "0000000000" and ColsCounter_r < "1001111111" then
191 
--              pdata_out1 <= (others => '0');
192 
--              pdata_out2 <= (others => '0');
193 
--              pdata_out3 <= (others => '0');
194 
--              pdata_out4 <= cache2((DATA_WIDTH-1) downto 0);
195 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
196 
--              pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
197 
--              pdata_out7 <= cache1((DATA_WIDTH-1) downto 0);
198 
--              pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
199 
--              pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
200 
--              -- counter2=639
201 
--
202 
--        --3 top right
203 
--        elsif RowsCounter_r = "000000000" and ColsCounter_r = "1001111111" then
204 
--              pdata_out1 <= (others => '0');
205 
--              pdata_out2 <= (others => '0');
206 
--              pdata_out3 <= (others => '0');
207 
--              pdata_out4 <= cache2((DATA_WIDTH-1) downto 0 );
208 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto DATA_WIDTH);
209 
--              pdata_out6 <= (others => '0');
210 
--              pdata_out7 <= cache1((DATA_WIDTH-1) downto 0 );
211 
--              pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto DATA_WIDTH);
212 
--              pdata_out9 <= (others => '0');
213 
--
214 
--        -- row>0 and row<479 (4)left
215 
--        elsif RowsCounter_r > "000000000" and RowsCounter_r < "111011111" and ColsCounter_r = "0000000000" then
216 
--              pdata_out1 <= (others => '0');
217 
--              pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
218 
--              pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
219 
--              pdata_out4 <= (others => '0');
220 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
221 
--              pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
222 
--              pdata_out7 <= (others => '0');
223 
--              pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
224 
--              pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
225 
--
226 
--        -- row>0 and row<479 and counter2>0 and counter2=639 (6) right
227 
--        elsif RowsCounter_r > "000000000" and RowsCounter_r < "111011111" and ColsCounter_r = "1001111111" then
228 
--              pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
229 
--              pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
230 
--              pdata_out3 <= (others => '0');
231 
--              pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
232 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
233 
--              pdata_out6 <= (others => '0');
234 
--              pdata_out7 <= cache1((DATA_WIDTH - 1) downto 0 );
235 
--              pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
236 
--              pdata_out9 <= (others => '0');
237 
--
238 
--        -- row=479 and counter2=0 (7) bottom left
239 
--        elsif RowsCounter_r="111011111" and ColsCounter_r="0000000000" then
240 
--              pdata_out1 <= (others => '0');
241 
--              pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
242 
--              pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
243 
--              pdata_out4 <= (others => '0');
244 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
245 
--              pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
246 
--              pdata_out7 <= (others => '0');
247 
--              pdata_out8 <= (others => '0');
248 
--              pdata_out9 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) ); -- 6
249 
--
250 
--        -- row=479 and counter2>0 and counter2<639 (8) bottom
251 
--        elsif RowsCounter_r = "111011111" and ColsCounter_r > "0000000000" and ColsCounter_r < "1001111111" then
252 
--              pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
253 
--              pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
254 
--              pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
255 
--              pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
256 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
257 
--              pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
258 
--              pdata_out7 <= (others => '0');
259 
--              pdata_out8 <= (others => '0');
260 
--              pdata_out9 <= (others => '0');
261 
--
262 
--        -- row=479 and counter2=639 (9) bottom right
263 
--        elsif RowsCounter_r = "111011111" and ColsCounter_r = "1001111111" then
264 
--              pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
265 
--              pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
266 
--              pdata_out3 <= (others => '0');
267 
--              pdata_out4 <= cache2((DATA_WIDTH - 1) downto 0 );
268 
--              pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto DATA_WIDTH );
269 
--              pdata_out6 <= (others => '0');
270 
--              pdata_out7 <= cache2((DATA_WIDTH - 1) downto 0 ); -- 4
271 
--              pdata_out8 <= (others => '0');
272 
--              pdata_out9 <= (others => '0');
273 
 
274 
          -- 5
275 
--        else
276 
            pdata_out1 <= cache3((DATA_WIDTH - 1) downto 0 );
277 
                pdata_out2 <= cache3(((WINDOW_SIZE-1)*DATA_WIDTH - 1) downto (WINDOW_SIZE-2)*DATA_WIDTH );
278 
                pdata_out3 <= cache3(((WINDOW_SIZE)*DATA_WIDTH - 1) downto ((WINDOW_SIZE-1)*DATA_WIDTH) );
279 
        pdata_out4 <= cache2((DATA_WIDTH-1) downto 0);
280 
                pdata_out5 <= cache2(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
281 
                pdata_out6 <= cache2(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
282 
                pdata_out7 <= cache1((DATA_WIDTH-1) downto 0);
283 
                pdata_out8 <= cache1(((WINDOW_SIZE-1)*DATA_WIDTH-1) downto ((WINDOW_SIZE-2)*DATA_WIDTH));
284 
                pdata_out9 <= cache1(((WINDOW_SIZE)*DATA_WIDTH-1) downto ((WINDOW_SIZE-1)*DATA_WIDTH));
285 
 
286 
 
287 
--        end if; -- RowsCounter_r and ColsCounter_r
288 
        --else
289 
--        dData_out  <= (others =>'0');
290 
--        pdata_out1 <= (others =>'0');
291 
--        pdata_out2 <= (others =>'0');
292 
--        pdata_out3 <= (others =>'0');
293 
--        pdata_out4 <= (others =>'0');
294 
--        pdata_out5 <= (others =>'0');
295 
--        pdata_out6 <= (others =>'0');
296 
--        pdata_out7 <= (others =>'0');
297 
--        pdata_out8 <= (others =>'0');
298 
--        pdata_out9 <= (others =>'0');
299 
        end if; --rsync_temp
300 
        end if; --clk
301 
  end process EmittingProcess;
302 
end CacheSystem3;
303 
 

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