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[/] [canny_edge_detector/] [trunk/] [vhdl_src/] [FIFOLineBuffer.vhd] - Blame information for rev 2

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1 2 angelobacc
PACKAGE TYPES IS
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subtype SMALL_INTEGER is INTEGER range 0 to 639;
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END PACKAGE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use WORK.TYPES.all;
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entity FIFOLineBuffer is
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  generic (
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        DATA_WIDTH : integer := 8;
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        NO_OF_COLS : integer := 640 );
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  port(
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        clk : in std_logic;
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        fsync : in std_logic;
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        pdata_in : in std_logic_vector(DATA_WIDTH -1 downto 0);
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        pdata_out : buffer std_logic_vector(DATA_WIDTH -1 downto 0)
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        );
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end FIFOLineBuffer;
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architecture Behavioral of FIFOLineBuffer is
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type ram_type is array (NO_OF_COLS downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
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signal ram_array : ram_type; -- := (others => "00000000");
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--signal clk2 : std_logic;
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signal rIndex : SMALL_INTEGER := 1;
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signal wIndex : SMALL_INTEGER := 0;
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begin
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--  clk <= NOT clk;
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  p : process(clk)
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  begin
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  if clk'event and clk='1' then
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    if fsync = '1' then
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          pdata_out <= ram_array(rIndex);
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          if rIndex < NO_OF_COLS-1 then
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            rIndex <= rIndex+1;
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          else
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                rIndex <= 0;
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          end if;
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        end if;
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  end if;
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  end process;
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  -- writing into the memory
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  p2 : process (clk)
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  begin
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  if clk'event and clk='1' then
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        if fsync = '1' then
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      ram_array(wIndex) <= pdata_in;
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          if wIndex < NO_OF_COLS-1 then
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                wIndex <= wIndex+1;
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          else
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                wIndex <= 0;
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          end if;
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        --else
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          --wIndex <= 0;
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    end if; -- fsync
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  end if; -- clk2
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  end process p2;
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end Behavioral;

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