1 |
2 |
zguig52 |
-------------------------------
|
2 |
|
|
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
|
3 |
|
|
---- Design Name: ccsds_rxtx_buffer
|
4 |
|
|
---- Version: 1.0.0
|
5 |
|
|
---- Description:
|
6 |
|
|
---- FIFO circular buffer
|
7 |
|
|
---- Input: 1 clk / [STORE: dat_val_i <= '1' / dat_i <= "STOREDDATA" ] / [READ: nxt_i <= '1']
|
8 |
|
|
---- Timing requirements: 1 clock cycle
|
9 |
|
|
---- Output: [READ: dat_val_o <= "1" / dat_o <= "STOREDDATA"]
|
10 |
|
|
---- Ressources requirements: CCSDS_RXTX_BUFFER_DATA_BUS_SIZE*(CCSDS_RXTX_BUFFER_SIZE+1) + 2*|log(CCSDS_RXTX_BUFFER_SIZE-1)/log(2)| + 2 + 3 + CCSDS_RXTX_BUFFER_DATA_BUS_SIZE registers
|
11 |
|
|
-------------------------------
|
12 |
|
|
---- Author(s):
|
13 |
|
|
---- Guillaume REMBERT
|
14 |
|
|
-------------------------------
|
15 |
|
|
---- Licence:
|
16 |
|
|
---- MIT
|
17 |
|
|
-------------------------------
|
18 |
|
|
---- Changes list:
|
19 |
|
|
---- 2016/02/27: initial release
|
20 |
|
|
---- 2016/10/20: major corrections and optimizations
|
21 |
|
|
-------------------------------
|
22 |
|
|
|
23 |
|
|
-- libraries used
|
24 |
|
|
library ieee;
|
25 |
|
|
use ieee.std_logic_1164.all;
|
26 |
|
|
|
27 |
|
|
--=============================================================================
|
28 |
|
|
-- Entity declaration for ccsds_tx / unitary rxtx buffer inputs and outputs
|
29 |
|
|
--=============================================================================
|
30 |
|
|
entity ccsds_rxtx_buffer is
|
31 |
|
|
generic(
|
32 |
|
|
constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer; -- in bits
|
33 |
|
|
constant CCSDS_RXTX_BUFFER_SIZE : integer
|
34 |
|
|
);
|
35 |
|
|
port(
|
36 |
|
|
-- inputs
|
37 |
|
|
clk_i: in std_logic;
|
38 |
|
|
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
|
39 |
|
|
dat_nxt_i: in std_logic;
|
40 |
|
|
dat_val_i: in std_logic;
|
41 |
|
|
rst_i: in std_logic;
|
42 |
|
|
-- outputs
|
43 |
|
|
buf_emp_o: out std_logic;
|
44 |
|
|
buf_ful_o: out std_logic;
|
45 |
|
|
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
|
46 |
|
|
dat_val_o: out std_logic
|
47 |
|
|
);
|
48 |
|
|
end ccsds_rxtx_buffer;
|
49 |
|
|
|
50 |
|
|
--=============================================================================
|
51 |
|
|
-- architecture declaration / internal components and connections
|
52 |
|
|
--=============================================================================
|
53 |
|
|
architecture rtl of ccsds_rxtx_buffer is
|
54 |
|
|
|
55 |
|
|
-- interconnection signals
|
56 |
|
|
type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
|
57 |
|
|
signal buffer_data: buffer_array := (others => (others => '0'));
|
58 |
|
|
signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
|
59 |
|
|
signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
|
60 |
|
|
|
61 |
|
|
-- components instanciation and mapping
|
62 |
|
|
begin
|
63 |
|
|
|
64 |
|
|
-- internal processing
|
65 |
|
|
|
66 |
|
|
--=============================================================================
|
67 |
|
|
-- Begin of bufferpullp
|
68 |
|
|
-- Read data from buffer
|
69 |
|
|
--=============================================================================
|
70 |
|
|
-- read: nxt_dat_i, rst_i, buffer_write_pos, buffer_data
|
71 |
|
|
-- write: dat_o, dat_val_o, buf_emp_o
|
72 |
|
|
-- r/w: buffer_read_pos
|
73 |
|
|
BUFFERPULLP : process (clk_i)
|
74 |
|
|
begin
|
75 |
|
|
if rising_edge(clk_i) then
|
76 |
|
|
if (rst_i = '1') then
|
77 |
|
|
buf_emp_o <= '1';
|
78 |
|
|
buffer_read_pos <= 0;
|
79 |
|
|
dat_o <= (others => '0');
|
80 |
|
|
dat_val_o <= '0';
|
81 |
|
|
else
|
82 |
|
|
if (buffer_read_pos = buffer_write_pos) then
|
83 |
|
|
buf_emp_o <= '1';
|
84 |
|
|
dat_val_o <= '0';
|
85 |
|
|
else
|
86 |
|
|
buf_emp_o <= '0';
|
87 |
|
|
if (dat_nxt_i = '1') then
|
88 |
|
|
dat_val_o <= '1';
|
89 |
|
|
dat_o <= buffer_data(buffer_read_pos);
|
90 |
|
|
if (buffer_read_pos < CCSDS_RXTX_BUFFER_SIZE) then
|
91 |
|
|
buffer_read_pos <= (buffer_read_pos + 1);
|
92 |
|
|
else
|
93 |
|
|
buffer_read_pos <= 0;
|
94 |
|
|
end if;
|
95 |
|
|
else
|
96 |
|
|
dat_val_o <= '0';
|
97 |
|
|
end if;
|
98 |
|
|
end if;
|
99 |
|
|
end if;
|
100 |
|
|
end if;
|
101 |
|
|
end process;
|
102 |
|
|
--=============================================================================
|
103 |
|
|
-- Begin of bufferpushp
|
104 |
|
|
-- Store valid input data in buffer
|
105 |
|
|
--=============================================================================
|
106 |
|
|
-- read: dat_i, dat_val_i, buffer_read_pos, rst_i
|
107 |
|
|
-- write: buffer_data, buf_ful_o
|
108 |
|
|
-- r/w: buffer_write_pos
|
109 |
|
|
BUFFERPUSH : process (clk_i)
|
110 |
|
|
begin
|
111 |
|
|
if rising_edge(clk_i) then
|
112 |
|
|
if (rst_i = '1') then
|
113 |
|
|
-- buffer_data <= (others => (others => '0'));
|
114 |
|
|
buf_ful_o <= '0';
|
115 |
|
|
buffer_write_pos <= 0;
|
116 |
|
|
else
|
117 |
|
|
if (buffer_write_pos < CCSDS_RXTX_BUFFER_SIZE) then
|
118 |
|
|
if (buffer_read_pos = (buffer_write_pos+1)) then
|
119 |
|
|
buf_ful_o <= '1';
|
120 |
|
|
else
|
121 |
|
|
buf_ful_o <= '0';
|
122 |
|
|
if (dat_val_i = '1') then
|
123 |
|
|
buffer_data(buffer_write_pos) <= dat_i;
|
124 |
|
|
buffer_write_pos <= (buffer_write_pos + 1);
|
125 |
|
|
end if;
|
126 |
|
|
end if;
|
127 |
|
|
else
|
128 |
|
|
if (buffer_read_pos = 0) then
|
129 |
|
|
buf_ful_o <= '1';
|
130 |
|
|
else
|
131 |
|
|
buf_ful_o <= '0';
|
132 |
|
|
if (dat_val_i = '1') then
|
133 |
|
|
buffer_data(buffer_write_pos) <= dat_i;
|
134 |
|
|
buffer_write_pos <= 0;
|
135 |
|
|
end if;
|
136 |
|
|
end if;
|
137 |
|
|
end if;
|
138 |
|
|
end if;
|
139 |
|
|
end if;
|
140 |
|
|
end process;
|
141 |
|
|
end rtl;
|