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[/] [ccsds_rxtxsoc/] [trunk/] [ccsds_rxtx_buffer.vhd] - Blame information for rev 2

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1 2 zguig52
-------------------------------
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_rxtx_buffer
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---- Version: 1.0.0
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---- Description:
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---- FIFO circular buffer
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---- Input: 1 clk / [STORE: dat_val_i <= '1' / dat_i <= "STOREDDATA" ] / [READ: nxt_i <= '1']
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---- Timing requirements: 1 clock cycle
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---- Output: [READ: dat_val_o <= "1" / dat_o <= "STOREDDATA"]
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---- Ressources requirements: CCSDS_RXTX_BUFFER_DATA_BUS_SIZE*(CCSDS_RXTX_BUFFER_SIZE+1) + 2*|log(CCSDS_RXTX_BUFFER_SIZE-1)/log(2)| + 2 + 3 + CCSDS_RXTX_BUFFER_DATA_BUS_SIZE registers
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/02/27: initial release
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---- 2016/10/20: major corrections and optimizations
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary rxtx buffer inputs and outputs
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--=============================================================================
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entity ccsds_rxtx_buffer is
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  generic(
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    constant CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer; -- in bits
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    constant CCSDS_RXTX_BUFFER_SIZE : integer
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  );
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  port(
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    -- inputs
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    clk_i: in std_logic;
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    dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
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    dat_nxt_i: in std_logic;
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    dat_val_i: in std_logic;
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    rst_i: in std_logic;
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    -- outputs
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    buf_emp_o: out std_logic;
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    buf_ful_o: out std_logic;
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    dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
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    dat_val_o: out std_logic
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  );
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end ccsds_rxtx_buffer;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture rtl of ccsds_rxtx_buffer is
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-- interconnection signals
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  type buffer_array is array (CCSDS_RXTX_BUFFER_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
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  signal buffer_data: buffer_array := (others => (others => '0'));
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  signal buffer_read_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
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  signal buffer_write_pos: integer range 0 to CCSDS_RXTX_BUFFER_SIZE := 0;
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-- components instanciation and mapping
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  begin
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-- internal processing
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    --=============================================================================
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    -- Begin of bufferpullp
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    -- Read data from buffer
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    --=============================================================================
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    -- read: nxt_dat_i, rst_i, buffer_write_pos, buffer_data
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    -- write: dat_o, dat_val_o, buf_emp_o
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    -- r/w: buffer_read_pos
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    BUFFERPULLP : process (clk_i)
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    begin
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      if rising_edge(clk_i) then
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        if (rst_i = '1') then
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          buf_emp_o <= '1';
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          buffer_read_pos <= 0;
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          dat_o <= (others => '0');
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          dat_val_o <= '0';
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        else
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          if (buffer_read_pos = buffer_write_pos) then
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            buf_emp_o <= '1';
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            dat_val_o <= '0';
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          else
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            buf_emp_o <= '0';
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            if (dat_nxt_i = '1') then
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              dat_val_o <= '1';
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              dat_o <= buffer_data(buffer_read_pos);
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              if (buffer_read_pos < CCSDS_RXTX_BUFFER_SIZE) then
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                buffer_read_pos <= (buffer_read_pos + 1);
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              else
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                buffer_read_pos <= 0;
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              end if;
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            else
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              dat_val_o <= '0';
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            end if;
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          end if;
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        end if;
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      end if;
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    end process;
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    --=============================================================================
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    -- Begin of bufferpushp
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    -- Store valid input data in buffer
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    --=============================================================================
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    -- read: dat_i, dat_val_i, buffer_read_pos, rst_i
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    -- write:  buffer_data, buf_ful_o
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    -- r/w: buffer_write_pos
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    BUFFERPUSH : process (clk_i)
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    begin
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      if rising_edge(clk_i) then
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        if (rst_i = '1') then
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--          buffer_data <= (others => (others => '0'));
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          buf_ful_o <= '0';
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          buffer_write_pos <= 0;
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        else
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          if (buffer_write_pos < CCSDS_RXTX_BUFFER_SIZE) then
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            if (buffer_read_pos = (buffer_write_pos+1)) then
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              buf_ful_o <= '1';
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            else
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              buf_ful_o <= '0';
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              if (dat_val_i = '1') then
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                buffer_data(buffer_write_pos) <= dat_i;
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                buffer_write_pos <= (buffer_write_pos + 1);
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              end if;
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            end if;
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          else
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            if (buffer_read_pos = 0) then
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              buf_ful_o <= '1';
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            else
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              buf_ful_o <= '0';
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              if (dat_val_i = '1') then
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                buffer_data(buffer_write_pos) <= dat_i;
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                buffer_write_pos <= 0;
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              end if;
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            end if;
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          end if;
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        end if;
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      end if;
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    end process;
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end rtl;

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