OpenCores
URL https://opencores.org/ocsvn/ccsds_rxtxsoc/ccsds_rxtxsoc/trunk

Subversion Repositories ccsds_rxtxsoc

[/] [ccsds_rxtxsoc/] [trunk/] [ccsds_tx_datalink_layer.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 zguig52
-------------------------------
2
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
3
---- Design Name: ccsds_tx_datalink_layer
4
---- Version: 1.0.0
5
---- Description:
6
---- TM (TeleMetry) Space Data Link Protocol
7
-------------------------------
8
---- Author(s):
9
---- Guillaume REMBERT
10
-------------------------------
11
---- Licence:
12
---- MIT
13
-------------------------------
14
---- Changes list:
15
---- 2015/11/17: initial release
16
---- 2016/10/21: rework based on TX final architecture
17
-------------------------------
18
 
19
-- libraries used
20
library ieee;
21
use ieee.std_logic_1164.all;
22
 
23
--=============================================================================
24
-- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
25
--=============================================================================
26
entity ccsds_tx_datalink_layer is
27
  generic (
28
    constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
29
    constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
30
    constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
31
    constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
32
    constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
33
    constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
34
    constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
35
  );
36
  port(
37
    -- inputs
38
    clk_bit_i: in std_logic;
39
    clk_dat_i: in std_logic;
40
    dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
41
    dat_val_i: in std_logic;
42
    rst_i: in std_logic;
43
    -- outputs
44
    dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
45
    dat_nxt_o: out std_logic;
46
    dat_val_o: out std_logic;
47
    idl_o: out std_logic
48
  );
49
end ccsds_tx_datalink_layer;
50
 
51
--=============================================================================
52
-- architecture declaration / internal components and connections
53
--=============================================================================
54
architecture structure of ccsds_tx_datalink_layer is
55
  component ccsds_tx_framer is
56
    generic(
57
      CCSDS_TX_FRAMER_DATA_BUS_SIZE : integer;
58
      CCSDS_TX_FRAMER_DATA_LENGTH : integer;
59
      CCSDS_TX_FRAMER_FOOTER_LENGTH : integer;
60
      CCSDS_TX_FRAMER_HEADER_LENGTH : integer
61
    );
62
    port(
63
      clk_i: in std_logic;
64
      rst_i: in std_logic;
65
      dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
66
      dat_val_i: in std_logic;
67
      dat_o: out std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8-1 downto 0);
68
      dat_val_o: out std_logic;
69
      dat_nxt_o: out std_logic;
70
      idl_o: out std_logic
71
    );
72
  end component;
73
  component ccsds_tx_coder is
74
    generic(
75
      CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
76
      CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
77
      CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
78
      CCSDS_TX_CODER_ASM_LENGTH: integer
79
    );
80
    port(
81
      clk_i: in std_logic;
82
      dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
83
      dat_val_i: in std_logic;
84
      rst_i: in std_logic;
85
      dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
86
      dat_val_o: out std_logic
87
    );
88
  end component;
89
 
90
-- internal constants
91
  constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
92
  constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
93
 
94
-- interconnection signals
95
  signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
96
  signal wire_framer_data_valid: std_logic;
97
  signal wire_coder_data: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0);
98
  signal wire_coder_data_valid: std_logic;
99
 
100
-- components instanciation and mapping
101
  begin
102
 
103
  tx_datalink_framer_0: ccsds_tx_framer
104
    generic map(
105
      CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_TX_DATALINK_HEADER_LENGTH,
106
      CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_TX_DATALINK_DATA_LENGTH,
107
      CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_TX_DATALINK_FOOTER_LENGTH,
108
      CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_TX_DATALINK_DATA_BUS_SIZE
109
    )
110
    port map(
111
      clk_i => clk_dat_i,
112
      rst_i => rst_i,
113
      dat_val_i => dat_val_i,
114
      dat_i => dat_i,
115
      dat_val_o => wire_framer_data_valid,
116
      dat_nxt_o => dat_nxt_o,
117
      dat_o => wire_framer_data,
118
      idl_o => idl_o
119
    );
120
  tx_datalink_coder_0: ccsds_tx_coder
121
    generic map(
122
      CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
123
      CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
124
      CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
125
      CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
126
    )
127
    port map(
128
      clk_i => clk_dat_i,
129
      dat_i => wire_framer_data,
130
      dat_val_i => wire_framer_data_valid,
131
      rst_i => rst_i,
132
      dat_val_o => wire_coder_data_valid,
133
      dat_o => wire_coder_data
134
    );
135
-- presynthesis checks
136
-- internal processing
137
    --=============================================================================
138
    -- Begin of bitsoutputp
139
    -- Generate valid bits output word by word on coder data_valid signal
140
    --=============================================================================
141
    -- read: rst_i, wire_coder_data_valid
142
    -- write: dat_val_o
143
    -- r/w: 
144
    BITSVALIDP: process (clk_dat_i)
145
    begin
146
      -- on each clock rising edge
147
      if rising_edge(clk_dat_i) then
148
        -- reset signal received
149
        if (rst_i = '1') then
150
          dat_val_o <= '0';
151
        else
152
          if (wire_coder_data_valid = '1') then
153
            dat_val_o <= '1';
154
          end if;
155
        end if;
156
      end if;
157
    end process;
158
    --=============================================================================
159
    -- Begin of bitsoutputp
160
    -- Generate bits output word by word based on coder output
161
    --=============================================================================
162
    -- read: rst_i, wire_coder_data
163
    -- write: dat_o
164
    -- r/w: 
165
    BITSOUTPUTP: process (clk_bit_i)
166
    variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
167
    variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
168
    begin
169
      -- on each clock rising edge
170
      if rising_edge(clk_bit_i) then
171
        -- reset signal received
172
        if (rst_i = '1') then
173
          next_word_pointer := FRAME_OUTPUT_WORDS - 1;
174
          dat_o <= (others => '0');
175
        else
176
          -- generating valid bits output words
177
          if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
178
            current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
179
            dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
180
            next_word_pointer := FRAME_OUTPUT_WORDS - 2;
181
          else
182
            dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
183
            if (next_word_pointer = 0) then
184
              next_word_pointer := FRAME_OUTPUT_WORDS - 1;
185
            else
186
              next_word_pointer := next_word_pointer - 1;
187
            end if;
188
          end if;
189
        end if;
190
      end if;
191
    end process;
192
end structure;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.