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zguig52 |
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_tx_datalink_layer
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---- Version: 1.0.0
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---- Description:
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---- TM (TeleMetry) Space Data Link Protocol
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2015/11/17: initial release
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---- 2016/10/21: rework based on TX final architecture
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary tx datalink layer inputs and outputs
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--=============================================================================
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entity ccsds_tx_datalink_layer is
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generic (
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constant CCSDS_TX_DATALINK_ASM_LENGTH: integer := 4; -- Attached Synchronization Marker length / in Bytes
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constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED: boolean := false; -- Enable differential coder
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constant CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer; -- Number of bits per codeword from differential coder
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constant CCSDS_TX_DATALINK_DATA_BUS_SIZE: integer; -- in bits
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constant CCSDS_TX_DATALINK_DATA_LENGTH: integer := 12; -- datagram data size (Bytes) / (has to be a multiple of CCSDS_TX_DATALINK_DATA_BUS_SIZE)
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constant CCSDS_TX_DATALINK_FOOTER_LENGTH: integer := 2; -- datagram footer length (Bytes)
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constant CCSDS_TX_DATALINK_HEADER_LENGTH: integer := 6 -- datagram header length (Bytes)
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);
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port(
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-- inputs
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clk_bit_i: in std_logic;
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clk_dat_i: in std_logic;
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dat_i: in std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
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dat_val_i: in std_logic;
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rst_i: in std_logic;
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-- outputs
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dat_o: out std_logic_vector(CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
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dat_nxt_o: out std_logic;
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dat_val_o: out std_logic;
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idl_o: out std_logic
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);
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end ccsds_tx_datalink_layer;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture structure of ccsds_tx_datalink_layer is
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component ccsds_tx_framer is
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generic(
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CCSDS_TX_FRAMER_DATA_BUS_SIZE : integer;
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CCSDS_TX_FRAMER_DATA_LENGTH : integer;
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CCSDS_TX_FRAMER_FOOTER_LENGTH : integer;
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CCSDS_TX_FRAMER_HEADER_LENGTH : integer
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);
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port(
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clk_i: in std_logic;
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rst_i: in std_logic;
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dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
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dat_val_i: in std_logic;
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dat_o: out std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8-1 downto 0);
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dat_val_o: out std_logic;
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dat_nxt_o: out std_logic;
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idl_o: out std_logic
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);
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end component;
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component ccsds_tx_coder is
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generic(
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CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD: integer;
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CCSDS_TX_CODER_DIFFERENTIAL_ENABLED: boolean;
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CCSDS_TX_CODER_DATA_BUS_SIZE : integer;
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CCSDS_TX_CODER_ASM_LENGTH: integer
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);
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port(
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clk_i: in std_logic;
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dat_i: in std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE-1 downto 0);
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dat_val_i: in std_logic;
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rst_i: in std_logic;
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dat_o: out std_logic_vector(CCSDS_TX_CODER_DATA_BUS_SIZE+CCSDS_TX_CODER_ASM_LENGTH*8-1 downto 0);
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dat_val_o: out std_logic
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);
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end component;
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-- internal constants
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constant FRAME_OUTPUT_SIZE: integer := (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH+CCSDS_TX_DATALINK_ASM_LENGTH)*8;
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constant FRAME_OUTPUT_WORDS: integer := FRAME_OUTPUT_SIZE/CCSDS_TX_DATALINK_DATA_BUS_SIZE;
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-- interconnection signals
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signal wire_framer_data: std_logic_vector((CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8-1 downto 0);
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signal wire_framer_data_valid: std_logic;
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signal wire_coder_data: std_logic_vector(FRAME_OUTPUT_SIZE-1 downto 0);
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signal wire_coder_data_valid: std_logic;
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-- components instanciation and mapping
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begin
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tx_datalink_framer_0: ccsds_tx_framer
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generic map(
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CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_TX_DATALINK_HEADER_LENGTH,
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CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_TX_DATALINK_DATA_LENGTH,
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CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_TX_DATALINK_FOOTER_LENGTH,
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CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_TX_DATALINK_DATA_BUS_SIZE
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)
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port map(
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clk_i => clk_dat_i,
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rst_i => rst_i,
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dat_val_i => dat_val_i,
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dat_i => dat_i,
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dat_val_o => wire_framer_data_valid,
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dat_nxt_o => dat_nxt_o,
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dat_o => wire_framer_data,
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idl_o => idl_o
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);
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tx_datalink_coder_0: ccsds_tx_coder
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generic map(
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CCSDS_TX_CODER_ASM_LENGTH => CCSDS_TX_DATALINK_ASM_LENGTH,
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CCSDS_TX_CODER_DATA_BUS_SIZE => (CCSDS_TX_DATALINK_DATA_LENGTH+CCSDS_TX_DATALINK_HEADER_LENGTH+CCSDS_TX_DATALINK_FOOTER_LENGTH)*8,
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CCSDS_TX_CODER_DIFFERENTIAL_BITS_PER_CODEWORD => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_BITS_PER_CODEWORD,
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CCSDS_TX_CODER_DIFFERENTIAL_ENABLED => CCSDS_TX_DATALINK_CODER_DIFFERENTIAL_ENABLED
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)
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port map(
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clk_i => clk_dat_i,
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dat_i => wire_framer_data,
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dat_val_i => wire_framer_data_valid,
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rst_i => rst_i,
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dat_val_o => wire_coder_data_valid,
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dat_o => wire_coder_data
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);
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-- presynthesis checks
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-- internal processing
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--=============================================================================
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-- Begin of bitsoutputp
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-- Generate valid bits output word by word on coder data_valid signal
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--=============================================================================
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-- read: rst_i, wire_coder_data_valid
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-- write: dat_val_o
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-- r/w:
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BITSVALIDP: process (clk_dat_i)
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begin
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-- on each clock rising edge
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if rising_edge(clk_dat_i) then
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-- reset signal received
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if (rst_i = '1') then
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dat_val_o <= '0';
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else
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if (wire_coder_data_valid = '1') then
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dat_val_o <= '1';
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end if;
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end if;
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end if;
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end process;
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--=============================================================================
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-- Begin of bitsoutputp
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-- Generate bits output word by word based on coder output
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--=============================================================================
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-- read: rst_i, wire_coder_data
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-- write: dat_o
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-- r/w:
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BITSOUTPUTP: process (clk_bit_i)
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variable next_word_pointer : integer range 0 to FRAME_OUTPUT_WORDS := FRAME_OUTPUT_WORDS - 1;
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variable current_frame: std_logic_vector(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0) := (others => '0');
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begin
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-- on each clock rising edge
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if rising_edge(clk_bit_i) then
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-- reset signal received
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if (rst_i = '1') then
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next_word_pointer := FRAME_OUTPUT_WORDS - 1;
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dat_o <= (others => '0');
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else
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-- generating valid bits output words
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if (next_word_pointer = FRAME_OUTPUT_WORDS - 1) then
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current_frame := wire_coder_data(FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto 0);
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dat_o <= wire_coder_data(FRAME_OUTPUT_SIZE-1 downto FRAME_OUTPUT_SIZE-CCSDS_TX_DATALINK_DATA_BUS_SIZE);
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next_word_pointer := FRAME_OUTPUT_WORDS - 2;
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else
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dat_o <= current_frame((next_word_pointer+1)*CCSDS_TX_DATALINK_DATA_BUS_SIZE-1 downto next_word_pointer*CCSDS_TX_DATALINK_DATA_BUS_SIZE);
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if (next_word_pointer = 0) then
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next_word_pointer := FRAME_OUTPUT_WORDS - 1;
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else
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next_word_pointer := next_word_pointer - 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end structure;
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