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[/] [ccsds_rxtxsoc/] [trunk/] [ccsds_tx_filter.vhd] - Blame information for rev 2

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1 2 zguig52 
-------------------------------
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---- Project: EurySPACE CCSDS RX/TX with wishbone interface
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---- Design Name: ccsds_tx_filter
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---- Version: 1.0.0
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---- Description:
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---- Transform symbols to samples, oversample signal and filter it with SRRC filter
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-------------------------------
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---- Author(s):
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---- Guillaume REMBERT
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-------------------------------
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---- Licence:
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---- MIT
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-------------------------------
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---- Changes list:
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---- 2016/11/06: initial release
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-------------------------------
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-- libraries used
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library ieee;
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use ieee.std_logic_1164.all;
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--=============================================================================
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-- Entity declaration for ccsds_tx / unitary tx filter inputs and outputs
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--=============================================================================
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entity ccsds_tx_filter is
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  generic(
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    constant CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer; -- in bits
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    constant CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
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    constant CCSDS_TX_FILTER_OFFSET_IQ: boolean := true;
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    constant CCSDS_TX_FILTER_MODULATION_TYPE: integer;
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    constant CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
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    constant CCSDS_TX_FILTER_TARGET_SNR: real := 40.0
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  );
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  port(
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    -- inputs
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    clk_i: in std_logic;
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    rst_i: in std_logic;
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    sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
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    sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
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    sym_val_i: in std_logic;
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    -- outputs
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    sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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    sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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    sam_val_o: out std_logic
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  );
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end ccsds_tx_filter;
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--=============================================================================
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-- architecture declaration / internal components and connections
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--=============================================================================
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architecture structure of ccsds_tx_filter is
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  component ccsds_tx_mapper_symbols_samples is
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    generic(
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      constant CCSDS_TX_MAPPER_TARGET_SNR: real;
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      constant CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer;
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      constant CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer
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    );
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    port(
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      clk_i: in std_logic;
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      rst_i: in std_logic;
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      sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
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      sym_val_i: in std_logic;
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      sam_val_o: out std_logic;
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      sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
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    );
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  end component;
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  component ccsds_rxtx_oversampler is
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    generic(
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      CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO: integer;
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      CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING: boolean;
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      CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH: integer
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    );
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    port(
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      clk_i: in std_logic;
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      sam_i: in std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
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      sam_val_i: in std_logic;
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      rst_i: in std_logic;
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      sam_o: out std_logic_vector(CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH-1 downto 0);
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      sam_val_o: out std_logic
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    );
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  end component;
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  component ccsds_rxtx_srrc is
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    generic(
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      CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
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      CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
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    );
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    port(
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      clk_i: in std_logic;
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      rst_i: in std_logic;
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      sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
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      sam_val_i: in std_logic;
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      sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
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      sam_val_o: out std_logic
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    );
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  end component;
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-- internal constants
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-- internal variable signals
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  signal wire_sam_i: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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  signal wire_sam_q: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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  signal wire_sam_i_val: std_logic := '0';
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  signal wire_sam_q_val: std_logic := '0';
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  signal wire_sam_i_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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  signal wire_sam_q_osr: std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
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  signal wire_sam_i_osr_val: std_logic;
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  signal wire_sam_q_osr_val: std_logic;
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  signal wire_sam_i_srrc_val: std_logic;
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  signal wire_sam_q_srrc_val: std_logic;
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-- components instanciation and mapping
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  begin
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  tx_mapper_symbols_samples_i_0: ccsds_tx_mapper_symbols_samples
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    generic map(
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      CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
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      CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
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      CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
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    )
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    port map(
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      clk_i => clk_i,
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      sym_i => sym_i_i,
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      sym_val_i => sym_val_i,
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      rst_i => rst_i,
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      sam_o => wire_sam_i,
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      sam_val_o => wire_sam_i_val
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    );
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  tx_oversampler_i_0: ccsds_rxtx_oversampler
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    generic map(
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      CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
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      CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => CCSDS_TX_FILTER_OFFSET_IQ,
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      CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
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    )
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    port map(
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      clk_i => clk_i,
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      sam_i => wire_sam_i,
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      sam_val_i => wire_sam_i_val,
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      rst_i => rst_i,
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      sam_val_o => wire_sam_i_osr_val,
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      sam_o => wire_sam_i_osr
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    );
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  tx_srrc_i_0: ccsds_rxtx_srrc
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    generic map(
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      CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
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      CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
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    )
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    port map(
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      clk_i => clk_i,
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      sam_i => wire_sam_i_osr,
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      sam_val_i => wire_sam_i_osr_val,
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      rst_i => rst_i,
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      sam_o => sam_i_o,
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      sam_val_o => wire_sam_i_srrc_val
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    );
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  -- BPSK
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  BPSK_GENERATION: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL = 1) and (CCSDS_TX_FILTER_MODULATION_TYPE = 2) generate
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    sam_q_o <= (others => '0');
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    wire_sam_q_srrc_val <= '1';
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  end generate BPSK_GENERATION;
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  -- nPSK
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  NPSK_GENERATION: if (CCSDS_TX_FILTER_MODULATION_TYPE /= 2) or (CCSDS_TX_FILTER_BITS_PER_SYMBOL /= 1) generate
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    tx_mapper_symbols_samples_q_0: ccsds_tx_mapper_symbols_samples
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      generic map(
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        CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH,
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        CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_TX_FILTER_TARGET_SNR,
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        CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_TX_FILTER_BITS_PER_SYMBOL
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      )
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      port map(
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        clk_i => clk_i,
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        sym_i => sym_q_i,
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        sym_val_i => sym_val_i,
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        rst_i => rst_i,
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        sam_o => wire_sam_q,
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        sam_val_o => wire_sam_q_val
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      );
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    tx_oversampler_q_0: ccsds_rxtx_oversampler
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      generic map(
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        CCSDS_RXTX_OVERSAMPLER_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
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        CCSDS_RXTX_OVERSAMPLER_SYMBOL_DEPHASING => false,
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        CCSDS_RXTX_OVERSAMPLER_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
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      )
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      port map(
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        clk_i => clk_i,
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        sam_i => wire_sam_q,
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        sam_val_i => wire_sam_q_val,
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        rst_i => rst_i,
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        sam_val_o => wire_sam_q_osr_val,
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        sam_o => wire_sam_q_osr
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      );
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    tx_srrc_q_0: ccsds_rxtx_srrc
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      generic map(
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        CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_TX_FILTER_OVERSAMPLING_RATIO,
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        CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_TX_FILTER_SIG_QUANT_DEPTH
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      )
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      port map(
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        clk_i => clk_i,
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        sam_i => wire_sam_q_osr,
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        sam_val_i => wire_sam_q_osr_val,
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        rst_i => rst_i,
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        sam_o => sam_q_o,
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        sam_val_o => wire_sam_q_srrc_val
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      );
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    end generate NPSK_GENERATION;
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    --Valid samples indicator
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    sam_val_o <= wire_sam_i_srrc_val and wire_sam_q_srrc_val;
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-- presynthesis checks
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          CHKFILTERP0: if (CCSDS_TX_FILTER_BITS_PER_SYMBOL > 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)) generate
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                  process
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                  begin
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                          report "ERROR: BITS PER SYMBOL CANNOT BE HIGHER THAN 2*(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1)" severity failure;
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                          wait;
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                  end process;
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          end generate CHKFILTERP0;
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end structure;

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