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[/] [claw/] [trunk/] [or1200_cpu/] [Compile_Script] - Blame information for rev 4

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1 2 conte
# This compile script will compile the entire files of   *
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#  the OpenRISC along with my files that I put into the  *
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#  System                                                *
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# Written by: Balaji V. Iyer, bviyer@ncsu.edu            *
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# Advisor: Dr. Tom Conte
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##########################################################
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################################################################
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#                                                              #
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# Copyright (C) 2000 Authors and OPENCORES.ORG                 #
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#                                                              #
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# This source file may be used and distributed without         #
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# restriction provided that this copyright statement is not    #
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# removed from the file and that any derivative work contains  #
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# the original copyright notice and the associated disclaimer. #
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#                                                              #
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# This source file is free software; you can redistribute it   #
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# and/or modify it under the terms of the GNU Lesser General   #
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# Public License as published by the Free Software Foundation; #
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# either version 2.1 of the License, or (at your option) any   #
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# later version.                                               #
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#                                                              #
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# This source is distributed in the hope that it will be       #
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# useful, but WITHOUT ANY WARRANTY; without even the implied   #
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# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      #
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# PURPOSE.  See the GNU Lesser General Public License for more #
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# details.                                                     #
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#                                                              #
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# You should have received a copy of the GNU Lesser General    #
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# Public License along with this source; if not, download it   #
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# from http://www.opencores.org/lgpl.shtml                     #
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#                                                              #
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################################################################
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add cadence
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verilog or1200_defines.v or1200_alu.v or1200_tpram_32x32.v or1200_spram_256x21.v or1200_spram_1024x32.v or1200_spram_1024x32_bw.v or1200_spram_64x14.v or1200_spram_64x22.v or1200_spram_64x24.v or1200_dc_fsm.v or1200_dc_tag.v or1200_dc_ram.v or1200_dc_top.v or1200_ic_fsm.v or1200_ic_tag.v or1200_ic_ram.v or1200_ic_top.v or1200_immu_tlb.v or1200_immu_top.v  or1200_rfram_generic.v or1200_spram_2048x32.v or1200_qmem_top.v or1200_dpram_32x32.v or1200_rf.v or1200_rf_top.v or1200_sprs.v or1200_mem2reg.v or1200_reg2mem.v or1200_lsu.v or1200_genpc.v or1200_if.v or1200_ctrl.v or1200_gmultp2_32x32.v or1200_mult_mac.v or1200_du.v or1200_wbmux.v or1200_except.v or1200_freeze.v or1200_operandmuxes.v or1200_cfgr.v or1200_sb_fifo.v or1200_tt.v or1200_wb_biu.v or1200_cpu.v

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