OpenCores
URL https://opencores.org/ocsvn/claw/claw/trunk

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [Wave_Forms_For_The_Whole_Thing/] [ctrl1_module.ps] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 conte 
%!PS-Adobe-3.0
2 
%%Creator: Model Technology ModelSim SE vsim 5.7e Simulator 2003.07 Jul  8 2003
3 
%%Title: /afs/eos.ncsu.edu/service/ece/research/tinker/bviyer/vol1/OR_1200_Multithreading_Implementation/verilog_with_my_changes/or1200_cpu/Wave_Forms_For_The_Whole_Thing/ctrl1_module.ps
4 
%%CreationDate: 2004-08-14 12:23:51 AM
5 
%%DocumentData: Clean8Bit
6 
%%DocumentNeededResources: font Helvetica
7 
%%Orientation: Landscape
8 
%%PageOrder: ascend
9 
%%Pages: 8
10 
%%EndComments
11 
%%Page: 1 1
12 
gsave
13 
90 rotate 0.12 dup neg scale
14 
% dump string table
15 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
16 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
17 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
18 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
19 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
20 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
21 
/ARC {5 -2 roll SX 5 2 roll arc} def
22 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
23 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
24 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
25 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
26 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
27 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
28 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
29 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
30 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
31 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
32 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
33 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
34 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
35 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
36 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
37 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
38 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
39 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
40 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
41 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
42 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
43 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
44 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
45 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
46 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
47 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
48 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
49 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
50 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
51 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
52 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
53 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
54 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
55 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
56 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
57 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
58 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
59 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
60 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
61 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
62 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
63 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
64 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
65 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
66 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
67 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
68 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
69 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
70 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
71 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
72 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
73 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
74 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
75 
% draw waveform shading
76 
[] 0 SD
77 
2.995 setlinewidth
78 
 
79 
 
80 
 
81 
3045 370 MT 3261 370 LS
82 
3261 370 MT 3261 370 LT 3268 329 LT 6298 329 LT ST
83 
3261 370 MT 3261 370 LT 3268 410 LT 6298 410 LT ST
84 
(4) 3275 370 WT pop 0 originOffset 37 add RSS
85 
3045 514 MT 3261 514 LS
86 
3261 514 MT 3261 514 LT 3268 473 LT 4556 473 LT 4563 514 LT ST
87 
3261 514 MT 3261 514 LT 3268 554 LT 4556 554 LT 4563 514 LT ST
88 
(00410000) 3275 514 WT pop 0 originOffset 37 add RSS
89 
4563 514 MT 4563 514 LT 4570 473 LT 6298 473 LT ST
90 
4563 514 MT 4563 514 LT 4570 554 LT 6298 554 LT ST
91 
(00610000) 4577 514 WT pop 0 originOffset 37 add RSS
92 
3045 658 MT 3261 658 LS
93 
3261 658 MT 3261 658 LT 3268 617 LT 6298 617 LT ST
94 
3261 658 MT 3261 658 LT 3268 698 LT 6298 698 LT ST
95 
(0) 3275 658 WT pop 0 originOffset 37 add RSS
96 
3045 802 MT 3045 842 LS
97 
3045 842 MT 6298 842 LS
98 
3045 946 MT 3045 986 LS
99 
3045 986 MT 3261 986 LS
100 
3261 986 MT 3261 906 LS
101 
3261 906 MT 3478 906 LS
102 
3478 906 MT 3478 986 LS
103 
3478 986 MT 3695 986 LS
104 
3695 986 MT 3695 906 LS
105 
3695 906 MT 3912 906 LS
106 
3912 906 MT 3912 986 LS
107 
3912 986 MT 4129 986 LS
108 
4129 986 MT 4129 906 LS
109 
4129 906 MT 4346 906 LS
110 
4346 906 MT 4346 986 LS
111 
4346 986 MT 4563 986 LS
112 
4563 986 MT 4563 906 LS
113 
4563 906 MT 4779 906 LS
114 
4779 906 MT 4779 986 LS
115 
4779 986 MT 4996 986 LS
116 
4996 986 MT 4996 906 LS
117 
4996 906 MT 5213 906 LS
118 
5213 906 MT 5213 986 LS
119 
5213 986 MT 5430 986 LS
120 
5430 986 MT 5430 906 LS
121 
5430 906 MT 5647 906 LS
122 
5647 906 MT 5647 986 LS
123 
5647 986 MT 5864 986 LS
124 
5864 986 MT 5864 906 LS
125 
5864 906 MT 6081 906 LS
126 
6081 906 MT 6081 986 LS
127 
6081 986 MT 6298 986 LS
128 
3045 1090 MT 3261 1090 LS
129 
3261 1090 MT 3261 1090 LT 3268 1049 LT 4122 1049 LT 4129 1090 LT ST
130 
3261 1090 MT 3261 1090 LT 3268 1130 LT 4122 1130 LT 4129 1090 LT ST
131 
(0) 3275 1090 WT pop 0 originOffset 37 add RSS
132 
4129 1090 MT 4129 1090 LT 4136 1049 LT 4556 1049 LT 4563 1090 LT ST
133 
4129 1090 MT 4129 1090 LT 4136 1130 LT 4556 1130 LT 4563 1090 LT ST
134 
(2) 4143 1090 WT pop 0 originOffset 37 add RSS
135 
4563 1090 MT 4563 1090 LT 4570 1049 LT 6298 1049 LT ST
136 
4563 1090 MT 4563 1090 LT 4570 1130 LT 6298 1130 LT ST
137 
(3) 4577 1090 WT pop 0 originOffset 37 add RSS
138 
3045 1193 MT 3045 1193 LT 3254 1193 LT 3261 1234 LT ST
139 
3045 1274 MT 3045 1274 LT 3254 1274 LT 3261 1234 LT ST
140 
(Xx) 3059 1234 WT pop 0 originOffset 37 add RSS
141 
3261 1234 MT 3261 1234 LT 3268 1193 LT 6298 1193 LT ST
142 
3261 1234 MT 3261 1234 LT 3268 1274 LT 6298 1274 LT ST
143 
(00) 3275 1234 WT pop 0 originOffset 37 add RSS
144 
3045 1378 MT 3261 1378 LS
145 
3261 1378 MT 3261 1378 LT 3268 1337 LT 6298 1337 LT ST
146 
3261 1378 MT 3261 1378 LT 3268 1418 LT 6298 1418 LT ST
147 
(00) 3275 1378 WT pop 0 originOffset 37 add RSS
148 
3045 1522 MT 6298 1522 LS
149 
3045 1666 MT 3912 1666 LS
150 
3912 1666 MT 3912 1706 LS
151 
3912 1706 MT 6298 1706 LS
152 
3045 1810 MT 3261 1810 LS
153 
3261 1810 MT 3261 1810 LT 3268 1769 LT 4556 1769 LT 4563 1810 LT ST
154 
3261 1810 MT 3261 1810 LT 3268 1850 LT 4556 1850 LT 4563 1810 LT ST
155 
(14410000) 3275 1810 WT pop 0 originOffset 37 add RSS
156 
4563 1810 MT 4563 1810 LT 4570 1769 LT 6298 1769 LT ST
157 
4563 1810 MT 4563 1810 LT 4570 1850 LT 6298 1850 LT ST
158 
(14610000) 4577 1810 WT pop 0 originOffset 37 add RSS
159 
3045 1954 MT 3261 1954 LS
160 
3261 1954 MT 3261 1994 LS
161 
3261 1994 MT 6298 1994 LS
162 
3045 2098 MT 3261 2098 LS
163 
3261 2098 MT 3261 2058 LS
164 
3261 2058 MT 6298 2058 LS
165 
3045 2242 MT 3261 2242 LS
166 
3261 2242 MT 3261 2282 LS
167 
3261 2282 MT 6298 2282 LS
168 
3045 2386 MT 3912 2386 LS
169 
3912 2386 MT 3912 2426 LS
170 
3912 2426 MT 4129 2426 LS
171 
4129 2426 MT 4129 2386 LS
172 
4129 2386 MT 6298 2386 LS
173 
3045 2530 MT 3045 2570 LS
174 
3045 2570 MT 6298 2570 LS
175 
3045 2674 MT 3912 2674 LS
176 
3912 2674 MT 3912 2714 LS
177 
3912 2714 MT 6298 2714 LS
178 
3045 2818 MT 3261 2818 LS
179 
3261 2818 MT 3261 2818 LT 3268 2777 LT 4122 2777 LT 4129 2818 LT ST
180 
3261 2818 MT 3261 2818 LT 3268 2858 LT 4122 2858 LT 4129 2818 LT ST
181 
(14410000) 3275 2818 WT pop 0 originOffset 37 add RSS
182 
4129 2818 MT 4129 2818 LT 4136 2777 LT 6298 2777 LT ST
183 
4129 2818 MT 4129 2818 LT 4136 2858 LT 6298 2858 LT ST
184 
(14610000) 4143 2818 WT pop 0 originOffset 37 add RSS
185 
3045 2962 MT 3261 2962 LS
186 
3261 2962 MT 3261 3002 LS
187 
3261 3002 MT 6298 3002 LS
188 
3045 3106 MT 3261 3106 LS
189 
3261 3106 MT 3261 3066 LS
190 
3261 3066 MT 6298 3066 LS
191 
3045 3250 MT 3912 3250 LS
192 
3912 3250 MT 3912 3250 LT 3919 3209 LT 6298 3209 LT ST
193 
3912 3250 MT 3912 3250 LT 3919 3290 LT 6298 3290 LT ST
194 
(14610000) 3926 3250 WT pop 0 originOffset 37 add RSS
195 
3045 3394 MT 3261 3394 LS
196 
3261 3394 MT 3261 3434 LS
197 
3261 3434 MT 6298 3434 LS
198 
3045 3538 MT 3261 3538 LS
199 
3261 3538 MT 3261 3538 LT 3268 3497 LT 6298 3497 LT ST
200 
3261 3538 MT 3261 3538 LT 3268 3578 LT 6298 3578 LT ST
201 
(00000000) 3275 3538 WT pop 0 originOffset 37 add RSS
202 
3045 3682 MT 3261 3682 LS
203 
3261 3682 MT 3261 3682 LT 3268 3641 LT 6298 3641 LT ST
204 
3261 3682 MT 3261 3682 LT 3268 3722 LT 6298 3722 LT ST
205 
(0) 3275 3682 WT pop 0 originOffset 37 add RSS
206 
3045 3826 MT 3261 3826 LS
207 
3261 3826 MT 3261 3826 LT 3268 3785 LT 6298 3785 LT ST
208 
3261 3826 MT 3261 3826 LT 3268 3866 LT 6298 3866 LT ST
209 
(0) 3275 3826 WT pop 0 originOffset 37 add RSS
210 
3045 3970 MT 3261 3970 LS
211 
3261 3970 MT 3261 3970 LT 3268 3929 LT 6298 3929 LT ST
212 
3261 3970 MT 3261 3970 LT 3268 4010 LT 6298 4010 LT ST
213 
(0) 3275 3970 WT pop 0 originOffset 37 add RSS
214 
3045 4114 MT 3261 4114 LS
215 
3261 4114 MT 3261 4154 LS
216 
3261 4154 MT 6298 4154 LS
217 
3045 4258 MT 3261 4258 LS
218 
3261 4258 MT 3261 4258 LT 3268 4217 LT 6298 4217 LT ST
219 
3261 4258 MT 3261 4258 LT 3268 4298 LT 6298 4298 LT ST
220 
(0) 3275 4258 WT pop 0 originOffset 37 add RSS
221 
3045 4402 MT 3912 4402 LS
222 
3912 4402 MT 3912 4402 LT 3919 4361 LT 6298 4361 LT ST
223 
3912 4402 MT 3912 4402 LT 3919 4442 LT 6298 4442 LT ST
224 
(01) 3926 4402 WT pop 0 originOffset 37 add RSS
225 
% draw timeline
226 
3088 4533 MT 3088 4570 LS
227 
3132 4533 MT 3132 4570 LS
228 
3175 4533 MT 3175 4570 LS
229 
3218 4533 MT 3218 4570 LS
230 
3262 4533 MT 3262 4570 LS
231 
3305 4533 MT 3305 4570 LS
232 
3349 4533 MT 3349 4570 LS
233 
3392 4533 MT 3392 4570 LS
234 
3435 4533 MT 3435 4570 LS
235 
(0) 3045 4649 WT TS RSS
236 
3521 4533 MT 3521 4570 LS
237 
3565 4533 MT 3565 4570 LS
238 
3608 4533 MT 3608 4570 LS
239 
3651 4533 MT 3651 4570 LS
240 
3695 4533 MT 3695 4570 LS
241 
3738 4533 MT 3738 4570 LS
242 
3782 4533 MT 3782 4570 LS
243 
3825 4533 MT 3825 4570 LS
244 
3868 4533 MT 3868 4570 LS
245 
3478 4506 MT 3478 4570 LS
246 
3955 4533 MT 3955 4570 LS
247 
3999 4533 MT 3999 4570 LS
248 
4042 4533 MT 4042 4570 LS
249 
4085 4533 MT 4085 4570 LS
250 
4129 4533 MT 4129 4570 LS
251 
4172 4533 MT 4172 4570 LS
252 
4216 4533 MT 4216 4570 LS
253 
4259 4533 MT 4259 4570 LS
254 
4302 4533 MT 4302 4570 LS
255 
3912 4506 MT 3912 4570 LS
256 
(20) 3912 4649 WT TS RSS
257 
4389 4533 MT 4389 4570 LS
258 
4433 4533 MT 4433 4570 LS
259 
4476 4533 MT 4476 4570 LS
260 
4519 4533 MT 4519 4570 LS
261 
4563 4533 MT 4563 4570 LS
262 
4606 4533 MT 4606 4570 LS
263 
4650 4533 MT 4650 4570 LS
264 
4693 4533 MT 4693 4570 LS
265 
4736 4533 MT 4736 4570 LS
266 
4346 4506 MT 4346 4570 LS
267 
4822 4533 MT 4822 4570 LS
268 
4866 4533 MT 4866 4570 LS
269 
4909 4533 MT 4909 4570 LS
270 
4952 4533 MT 4952 4570 LS
271 
4996 4533 MT 4996 4570 LS
272 
5039 4533 MT 5039 4570 LS
273 
5083 4533 MT 5083 4570 LS
274 
5126 4533 MT 5126 4570 LS
275 
5169 4533 MT 5169 4570 LS
276 
4779 4506 MT 4779 4570 LS
277 
(40) 4779 4649 WT TS RSS
278 
5256 4533 MT 5256 4570 LS
279 
5300 4533 MT 5300 4570 LS
280 
5343 4533 MT 5343 4570 LS
281 
5386 4533 MT 5386 4570 LS
282 
5430 4533 MT 5430 4570 LS
283 
5473 4533 MT 5473 4570 LS
284 
5517 4533 MT 5517 4570 LS
285 
5560 4533 MT 5560 4570 LS
286 
5603 4533 MT 5603 4570 LS
287 
5213 4506 MT 5213 4570 LS
288 
5690 4533 MT 5690 4570 LS
289 
5734 4533 MT 5734 4570 LS
290 
5777 4533 MT 5777 4570 LS
291 
5820 4533 MT 5820 4570 LS
292 
5864 4533 MT 5864 4570 LS
293 
5907 4533 MT 5907 4570 LS
294 
5951 4533 MT 5951 4570 LS
295 
5994 4533 MT 5994 4570 LS
296 
6037 4533 MT 6037 4570 LS
297 
5647 4506 MT 5647 4570 LS
298 
(60) 5647 4649 WT TS RSS
299 
6124 4533 MT 6124 4570 LS
300 
6168 4533 MT 6168 4570 LS
301 
6211 4533 MT 6211 4570 LS
302 
6254 4533 MT 6254 4570 LS
303 
6298 4533 MT 6298 4570 LS
304 
6341 4533 MT 6341 4570 LS
305 
6385 4533 MT 6385 4570 LS
306 
6428 4533 MT 6428 4570 LS
307 
6471 4533 MT 6471 4570 LS
308 
6081 4506 MT 6081 4570 LS
309 
% draw grid
310 
3478 300 MT 3478 4506 LS
311 
3912 300 MT 3912 4506 LS
312 
4346 300 MT 4346 4506 LS
313 
4779 300 MT 4779 4506 LS
314 
5213 300 MT 5213 4506 LS
315 
5647 300 MT 5647 4506 LS
316 
6081 300 MT 6081 4506 LS
317 
% draw waveforms
318 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) 3008 409 WT TSE RSS
319 
3471 300 MT 3485 300 LS
320 
3905 300 MT 3919 300 LS
321 
4339 300 MT 4353 300 LS
322 
4772 300 MT 4786 300 LS
323 
5206 300 MT 5220 300 LS
324 
5640 300 MT 5654 300 LS
325 
6074 300 MT 6088 300 LS
326 
3045 370 MT 3261 370 LS
327 
3261 370 MT 3261 370 LT 3268 329 LT 6298 329 LT ST
328 
3261 370 MT 3261 370 LT 3268 410 LT 6298 410 LT ST
329 
(4) 3275 370 WT pop 0 originOffset 37 add RSS
330 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) 3008 553 WT TSE RSS
331 
3471 444 MT 3485 444 LS
332 
3905 444 MT 3919 444 LS
333 
4339 444 MT 4353 444 LS
334 
4772 444 MT 4786 444 LS
335 
5206 444 MT 5220 444 LS
336 
5640 444 MT 5654 444 LS
337 
6074 444 MT 6088 444 LS
338 
3045 514 MT 3261 514 LS
339 
3261 514 MT 3261 514 LT 3268 473 LT 4556 473 LT 4563 514 LT ST
340 
3261 514 MT 3261 514 LT 3268 554 LT 4556 554 LT 4563 514 LT ST
341 
(00410000) 3275 514 WT pop 0 originOffset 37 add RSS
342 
4563 514 MT 4563 514 LT 4570 473 LT 6298 473 LT ST
343 
4563 514 MT 4563 514 LT 4570 554 LT 6298 554 LT ST
344 
(00610000) 4577 514 WT pop 0 originOffset 37 add RSS
345 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) 3008 697 WT TSE RSS
346 
3471 588 MT 3485 588 LS
347 
3905 588 MT 3919 588 LS
348 
4339 588 MT 4353 588 LS
349 
4772 588 MT 4786 588 LS
350 
5206 588 MT 5220 588 LS
351 
5640 588 MT 5654 588 LS
352 
6074 588 MT 6088 588 LS
353 
3045 658 MT 3261 658 LS
354 
3261 658 MT 3261 658 LT 3268 617 LT 6298 617 LT ST
355 
3261 658 MT 3261 658 LT 3268 698 LT 6298 698 LT ST
356 
(0) 3275 658 WT pop 0 originOffset 37 add RSS
357 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) 3008 841 WT TSE RSS
358 
3471 732 MT 3485 732 LS
359 
3905 732 MT 3919 732 LS
360 
4339 732 MT 4353 732 LS
361 
4772 732 MT 4786 732 LS
362 
5206 732 MT 5220 732 LS
363 
5640 732 MT 5654 732 LS
364 
6074 732 MT 6088 732 LS
365 
3045 802 MT 3045 842 LS
366 
3045 842 MT 6298 842 LS
367 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) 3008 985 WT TSE RSS
368 
3471 876 MT 3485 876 LS
369 
3905 876 MT 3919 876 LS
370 
4339 876 MT 4353 876 LS
371 
4772 876 MT 4786 876 LS
372 
5206 876 MT 5220 876 LS
373 
5640 876 MT 5654 876 LS
374 
6074 876 MT 6088 876 LS
375 
3045 946 MT 3045 986 LS
376 
3045 986 MT 3261 986 LS
377 
3261 986 MT 3261 906 LS
378 
3261 906 MT 3478 906 LS
379 
3478 906 MT 3478 986 LS
380 
3478 986 MT 3695 986 LS
381 
3695 986 MT 3695 906 LS
382 
3695 906 MT 3912 906 LS
383 
3912 906 MT 3912 986 LS
384 
3912 986 MT 4129 986 LS
385 
4129 986 MT 4129 906 LS
386 
4129 906 MT 4346 906 LS
387 
4346 906 MT 4346 986 LS
388 
4346 986 MT 4563 986 LS
389 
4563 986 MT 4563 906 LS
390 
4563 906 MT 4779 906 LS
391 
4779 906 MT 4779 986 LS
392 
4779 986 MT 4996 986 LS
393 
4996 986 MT 4996 906 LS
394 
4996 906 MT 5213 906 LS
395 
5213 906 MT 5213 986 LS
396 
5213 986 MT 5430 986 LS
397 
5430 986 MT 5430 906 LS
398 
5430 906 MT 5647 906 LS
399 
5647 906 MT 5647 986 LS
400 
5647 986 MT 5864 986 LS
401 
5864 986 MT 5864 906 LS
402 
5864 906 MT 6081 906 LS
403 
6081 906 MT 6081 986 LS
404 
6081 986 MT 6298 986 LS
405 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) 3008 1129 WT TSE RSS
406 
3471 1020 MT 3485 1020 LS
407 
3905 1020 MT 3919 1020 LS
408 
4339 1020 MT 4353 1020 LS
409 
4772 1020 MT 4786 1020 LS
410 
5206 1020 MT 5220 1020 LS
411 
5640 1020 MT 5654 1020 LS
412 
6074 1020 MT 6088 1020 LS
413 
3045 1090 MT 3261 1090 LS
414 
3261 1090 MT 3261 1090 LT 3268 1049 LT 4122 1049 LT 4129 1090 LT ST
415 
3261 1090 MT 3261 1090 LT 3268 1130 LT 4122 1130 LT 4129 1090 LT ST
416 
(0) 3275 1090 WT pop 0 originOffset 37 add RSS
417 
4129 1090 MT 4129 1090 LT 4136 1049 LT 4556 1049 LT 4563 1090 LT ST
418 
4129 1090 MT 4129 1090 LT 4136 1130 LT 4556 1130 LT 4563 1090 LT ST
419 
(2) 4143 1090 WT pop 0 originOffset 37 add RSS
420 
4563 1090 MT 4563 1090 LT 4570 1049 LT 6298 1049 LT ST
421 
4563 1090 MT 4563 1090 LT 4570 1130 LT 6298 1130 LT ST
422 
(3) 4577 1090 WT pop 0 originOffset 37 add RSS
423 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) 3008 1273 WT TSE RSS
424 
3471 1164 MT 3485 1164 LS
425 
3905 1164 MT 3919 1164 LS
426 
4339 1164 MT 4353 1164 LS
427 
4772 1164 MT 4786 1164 LS
428 
5206 1164 MT 5220 1164 LS
429 
5640 1164 MT 5654 1164 LS
430 
6074 1164 MT 6088 1164 LS
431 
3045 1193 MT 3045 1193 LT 3254 1193 LT 3261 1234 LT ST
432 
3045 1274 MT 3045 1274 LT 3254 1274 LT 3261 1234 LT ST
433 
(Xx) 3059 1234 WT pop 0 originOffset 37 add RSS
434 
3261 1234 MT 3261 1234 LT 3268 1193 LT 6298 1193 LT ST
435 
3261 1234 MT 3261 1234 LT 3268 1274 LT 6298 1274 LT ST
436 
(00) 3275 1234 WT pop 0 originOffset 37 add RSS
437 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) 3008 1417 WT TSE RSS
438 
3471 1308 MT 3485 1308 LS
439 
3905 1308 MT 3919 1308 LS
440 
4339 1308 MT 4353 1308 LS
441 
4772 1308 MT 4786 1308 LS
442 
5206 1308 MT 5220 1308 LS
443 
5640 1308 MT 5654 1308 LS
444 
6074 1308 MT 6088 1308 LS
445 
3045 1378 MT 3261 1378 LS
446 
3261 1378 MT 3261 1378 LT 3268 1337 LT 6298 1337 LT ST
447 
3261 1378 MT 3261 1378 LT 3268 1418 LT 6298 1418 LT ST
448 
(00) 3275 1378 WT pop 0 originOffset 37 add RSS
449 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) 3008 1561 WT TSE RSS
450 
3471 1452 MT 3485 1452 LS
451 
3905 1452 MT 3919 1452 LS
452 
4339 1452 MT 4353 1452 LS
453 
4772 1452 MT 4786 1452 LS
454 
5206 1452 MT 5220 1452 LS
455 
5640 1452 MT 5654 1452 LS
456 
6074 1452 MT 6088 1452 LS
457 
3045 1522 MT 6298 1522 LS
458 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) 3008 1705 WT TSE RSS
459 
3471 1596 MT 3485 1596 LS
460 
3905 1596 MT 3919 1596 LS
461 
4339 1596 MT 4353 1596 LS
462 
4772 1596 MT 4786 1596 LS
463 
5206 1596 MT 5220 1596 LS
464 
5640 1596 MT 5654 1596 LS
465 
6074 1596 MT 6088 1596 LS
466 
3045 1666 MT 3912 1666 LS
467 
3912 1666 MT 3912 1706 LS
468 
3912 1706 MT 6298 1706 LS
469 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) 3008 1849 WT TSE RSS
470 
3471 1740 MT 3485 1740 LS
471 
3905 1740 MT 3919 1740 LS
472 
4339 1740 MT 4353 1740 LS
473 
4772 1740 MT 4786 1740 LS
474 
5206 1740 MT 5220 1740 LS
475 
5640 1740 MT 5654 1740 LS
476 
6074 1740 MT 6088 1740 LS
477 
3045 1810 MT 3261 1810 LS
478 
3261 1810 MT 3261 1810 LT 3268 1769 LT 4556 1769 LT 4563 1810 LT ST
479 
3261 1810 MT 3261 1810 LT 3268 1850 LT 4556 1850 LT 4563 1810 LT ST
480 
(14410000) 3275 1810 WT pop 0 originOffset 37 add RSS
481 
4563 1810 MT 4563 1810 LT 4570 1769 LT 6298 1769 LT ST
482 
4563 1810 MT 4563 1810 LT 4570 1850 LT 6298 1850 LT ST
483 
(14610000) 4577 1810 WT pop 0 originOffset 37 add RSS
484 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) 3008 1993 WT TSE RSS
485 
3471 1884 MT 3485 1884 LS
486 
3905 1884 MT 3919 1884 LS
487 
4339 1884 MT 4353 1884 LS
488 
4772 1884 MT 4786 1884 LS
489 
5206 1884 MT 5220 1884 LS
490 
5640 1884 MT 5654 1884 LS
491 
6074 1884 MT 6088 1884 LS
492 
3045 1954 MT 3261 1954 LS
493 
3261 1954 MT 3261 1994 LS
494 
3261 1994 MT 6298 1994 LS
495 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) 3008 2137 WT TSE RSS
496 
3471 2028 MT 3485 2028 LS
497 
3905 2028 MT 3919 2028 LS
498 
4339 2028 MT 4353 2028 LS
499 
4772 2028 MT 4786 2028 LS
500 
5206 2028 MT 5220 2028 LS
501 
5640 2028 MT 5654 2028 LS
502 
6074 2028 MT 6088 2028 LS
503 
3045 2098 MT 3261 2098 LS
504 
3261 2098 MT 3261 2058 LS
505 
3261 2058 MT 6298 2058 LS
506 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) 3008 2281 WT TSE RSS
507 
3471 2172 MT 3485 2172 LS
508 
3905 2172 MT 3919 2172 LS
509 
4339 2172 MT 4353 2172 LS
510 
4772 2172 MT 4786 2172 LS
511 
5206 2172 MT 5220 2172 LS
512 
5640 2172 MT 5654 2172 LS
513 
6074 2172 MT 6088 2172 LS
514 
3045 2242 MT 3261 2242 LS
515 
3261 2242 MT 3261 2282 LS
516 
3261 2282 MT 6298 2282 LS
517 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) 3008 2425 WT TSE RSS
518 
3471 2316 MT 3485 2316 LS
519 
3905 2316 MT 3919 2316 LS
520 
4339 2316 MT 4353 2316 LS
521 
4772 2316 MT 4786 2316 LS
522 
5206 2316 MT 5220 2316 LS
523 
5640 2316 MT 5654 2316 LS
524 
6074 2316 MT 6088 2316 LS
525 
3045 2386 MT 3912 2386 LS
526 
3912 2386 MT 3912 2426 LS
527 
3912 2426 MT 4129 2426 LS
528 
4129 2426 MT 4129 2386 LS
529 
4129 2386 MT 6298 2386 LS
530 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) 3008 2569 WT TSE RSS
531 
3471 2460 MT 3485 2460 LS
532 
3905 2460 MT 3919 2460 LS
533 
4339 2460 MT 4353 2460 LS
534 
4772 2460 MT 4786 2460 LS
535 
5206 2460 MT 5220 2460 LS
536 
5640 2460 MT 5654 2460 LS
537 
6074 2460 MT 6088 2460 LS
538 
3045 2530 MT 3045 2570 LS
539 
3045 2570 MT 6298 2570 LS
540 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) 3008 2713 WT TSE RSS
541 
3471 2604 MT 3485 2604 LS
542 
3905 2604 MT 3919 2604 LS
543 
4339 2604 MT 4353 2604 LS
544 
4772 2604 MT 4786 2604 LS
545 
5206 2604 MT 5220 2604 LS
546 
5640 2604 MT 5654 2604 LS
547 
6074 2604 MT 6088 2604 LS
548 
3045 2674 MT 3912 2674 LS
549 
3912 2674 MT 3912 2714 LS
550 
3912 2714 MT 6298 2714 LS
551 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) 3008 2857 WT TSE RSS
552 
3471 2748 MT 3485 2748 LS
553 
3905 2748 MT 3919 2748 LS
554 
4339 2748 MT 4353 2748 LS
555 
4772 2748 MT 4786 2748 LS
556 
5206 2748 MT 5220 2748 LS
557 
5640 2748 MT 5654 2748 LS
558 
6074 2748 MT 6088 2748 LS
559 
3045 2818 MT 3261 2818 LS
560 
3261 2818 MT 3261 2818 LT 3268 2777 LT 4122 2777 LT 4129 2818 LT ST
561 
3261 2818 MT 3261 2818 LT 3268 2858 LT 4122 2858 LT 4129 2818 LT ST
562 
(14410000) 3275 2818 WT pop 0 originOffset 37 add RSS
563 
4129 2818 MT 4129 2818 LT 4136 2777 LT 6298 2777 LT ST
564 
4129 2818 MT 4129 2818 LT 4136 2858 LT 6298 2858 LT ST
565 
(14610000) 4143 2818 WT pop 0 originOffset 37 add RSS
566 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) 3008 3001 WT TSE RSS
567 
3471 2892 MT 3485 2892 LS
568 
3905 2892 MT 3919 2892 LS
569 
4339 2892 MT 4353 2892 LS
570 
4772 2892 MT 4786 2892 LS
571 
5206 2892 MT 5220 2892 LS
572 
5640 2892 MT 5654 2892 LS
573 
6074 2892 MT 6088 2892 LS
574 
3045 2962 MT 3261 2962 LS
575 
3261 2962 MT 3261 3002 LS
576 
3261 3002 MT 6298 3002 LS
577 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) 3008 3145 WT TSE RSS
578 
3471 3036 MT 3485 3036 LS
579 
3905 3036 MT 3919 3036 LS
580 
4339 3036 MT 4353 3036 LS
581 
4772 3036 MT 4786 3036 LS
582 
5206 3036 MT 5220 3036 LS
583 
5640 3036 MT 5654 3036 LS
584 
6074 3036 MT 6088 3036 LS
585 
3045 3106 MT 3261 3106 LS
586 
3261 3106 MT 3261 3066 LS
587 
3261 3066 MT 6298 3066 LS
588 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) 3008 3289 WT TSE RSS
589 
3471 3180 MT 3485 3180 LS
590 
3905 3180 MT 3919 3180 LS
591 
4339 3180 MT 4353 3180 LS
592 
4772 3180 MT 4786 3180 LS
593 
5206 3180 MT 5220 3180 LS
594 
5640 3180 MT 5654 3180 LS
595 
6074 3180 MT 6088 3180 LS
596 
3045 3250 MT 3912 3250 LS
597 
3912 3250 MT 3912 3250 LT 3919 3209 LT 6298 3209 LT ST
598 
3912 3250 MT 3912 3250 LT 3919 3290 LT 6298 3290 LT ST
599 
(14610000) 3926 3250 WT pop 0 originOffset 37 add RSS
600 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) 3008 3433 WT TSE RSS
601 
3471 3324 MT 3485 3324 LS
602 
3905 3324 MT 3919 3324 LS
603 
4339 3324 MT 4353 3324 LS
604 
4772 3324 MT 4786 3324 LS
605 
5206 3324 MT 5220 3324 LS
606 
5640 3324 MT 5654 3324 LS
607 
6074 3324 MT 6088 3324 LS
608 
3045 3394 MT 3261 3394 LS
609 
3261 3394 MT 3261 3434 LS
610 
3261 3434 MT 6298 3434 LS
611 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) 3008 3577 WT TSE RSS
612 
3471 3468 MT 3485 3468 LS
613 
3905 3468 MT 3919 3468 LS
614 
4339 3468 MT 4353 3468 LS
615 
4772 3468 MT 4786 3468 LS
616 
5206 3468 MT 5220 3468 LS
617 
5640 3468 MT 5654 3468 LS
618 
6074 3468 MT 6088 3468 LS
619 
3045 3538 MT 3261 3538 LS
620 
3261 3538 MT 3261 3538 LT 3268 3497 LT 6298 3497 LT ST
621 
3261 3538 MT 3261 3538 LT 3268 3578 LT 6298 3578 LT ST
622 
(00000000) 3275 3538 WT pop 0 originOffset 37 add RSS
623 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) 3008 3721 WT TSE RSS
624 
3471 3612 MT 3485 3612 LS
625 
3905 3612 MT 3919 3612 LS
626 
4339 3612 MT 4353 3612 LS
627 
4772 3612 MT 4786 3612 LS
628 
5206 3612 MT 5220 3612 LS
629 
5640 3612 MT 5654 3612 LS
630 
6074 3612 MT 6088 3612 LS
631 
3045 3682 MT 3261 3682 LS
632 
3261 3682 MT 3261 3682 LT 3268 3641 LT 6298 3641 LT ST
633 
3261 3682 MT 3261 3682 LT 3268 3722 LT 6298 3722 LT ST
634 
(0) 3275 3682 WT pop 0 originOffset 37 add RSS
635 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) 3008 3865 WT TSE RSS
636 
3471 3756 MT 3485 3756 LS
637 
3905 3756 MT 3919 3756 LS
638 
4339 3756 MT 4353 3756 LS
639 
4772 3756 MT 4786 3756 LS
640 
5206 3756 MT 5220 3756 LS
641 
5640 3756 MT 5654 3756 LS
642 
6074 3756 MT 6088 3756 LS
643 
3045 3826 MT 3261 3826 LS
644 
3261 3826 MT 3261 3826 LT 3268 3785 LT 6298 3785 LT ST
645 
3261 3826 MT 3261 3826 LT 3268 3866 LT 6298 3866 LT ST
646 
(0) 3275 3826 WT pop 0 originOffset 37 add RSS
647 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) 3008 4009 WT TSE RSS
648 
3471 3900 MT 3485 3900 LS
649 
3905 3900 MT 3919 3900 LS
650 
4339 3900 MT 4353 3900 LS
651 
4772 3900 MT 4786 3900 LS
652 
5206 3900 MT 5220 3900 LS
653 
5640 3900 MT 5654 3900 LS
654 
6074 3900 MT 6088 3900 LS
655 
3045 3970 MT 3261 3970 LS
656 
3261 3970 MT 3261 3970 LT 3268 3929 LT 6298 3929 LT ST
657 
3261 3970 MT 3261 3970 LT 3268 4010 LT 6298 4010 LT ST
658 
(0) 3275 3970 WT pop 0 originOffset 37 add RSS
659 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) 3008 4153 WT TSE RSS
660 
3471 4044 MT 3485 4044 LS
661 
3905 4044 MT 3919 4044 LS
662 
4339 4044 MT 4353 4044 LS
663 
4772 4044 MT 4786 4044 LS
664 
5206 4044 MT 5220 4044 LS
665 
5640 4044 MT 5654 4044 LS
666 
6074 4044 MT 6088 4044 LS
667 
3045 4114 MT 3261 4114 LS
668 
3261 4114 MT 3261 4154 LS
669 
3261 4154 MT 6298 4154 LS
670 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) 3008 4297 WT TSE RSS
671 
3471 4188 MT 3485 4188 LS
672 
3905 4188 MT 3919 4188 LS
673 
4339 4188 MT 4353 4188 LS
674 
4772 4188 MT 4786 4188 LS
675 
5206 4188 MT 5220 4188 LS
676 
5640 4188 MT 5654 4188 LS
677 
6074 4188 MT 6088 4188 LS
678 
3045 4258 MT 3261 4258 LS
679 
3261 4258 MT 3261 4258 LT 3268 4217 LT 6298 4217 LT ST
680 
3261 4258 MT 3261 4258 LT 3268 4298 LT 6298 4298 LT ST
681 
(0) 3275 4258 WT pop 0 originOffset 37 add RSS
682 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) 3008 4441 WT TSE RSS
683 
3471 4332 MT 3485 4332 LS
684 
3905 4332 MT 3919 4332 LS
685 
4339 4332 MT 4353 4332 LS
686 
4772 4332 MT 4786 4332 LS
687 
5206 4332 MT 5220 4332 LS
688 
5640 4332 MT 5654 4332 LS
689 
6074 4332 MT 6088 4332 LS
690 
3045 4402 MT 3912 4402 LS
691 
3912 4402 MT 3912 4402 LT 3919 4361 LT 6298 4361 LT ST
692 
3912 4402 MT 3912 4402 LT 3919 4442 LT 6298 4442 LT ST
693 
(01) 3926 4402 WT pop 0 originOffset 37 add RSS
694 
% draw footer
695 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 1 Page: 1) 300 4799 WT TSW RSS
696 
grestore
697 
showpage
698 
%%Page: 2 2
699 
gsave
700 
90 rotate 0.12 dup neg scale
701 
% dump string table
702 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
703 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
704 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
705 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
706 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
707 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
708 
/ARC {5 -2 roll SX 5 2 roll arc} def
709 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
710 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
711 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
712 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
713 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
714 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
715 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
716 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
717 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
718 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
719 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
720 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
721 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
722 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
723 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
724 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
725 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
726 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
727 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
728 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
729 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
730 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
731 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
732 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
733 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
734 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
735 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
736 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
737 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
738 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
739 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
740 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
741 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
742 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
743 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
744 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
745 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
746 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
747 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
748 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
749 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
750 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
751 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
752 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
753 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
754 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
755 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
756 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
757 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
758 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
759 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
760 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
761 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
762 
% draw waveform shading
763 
[] 0 SD
764 
2.995 setlinewidth
765 
 
766 
 
767 
 
768 
3045 370 MT 3912 370 LS
769 
3912 370 MT 3912 370 LT 3919 329 LT 6298 329 LT ST
770 
3912 370 MT 3912 370 LT 3919 410 LT 6298 410 LT ST
771 
(00) 3926 370 WT pop 0 originOffset 37 add RSS
772 
3045 514 MT 3261 514 LS
773 
3261 514 MT 3261 514 LT 3268 473 LT 4122 473 LT 4129 514 LT ST
774 
3261 514 MT 3261 514 LT 3268 554 LT 4122 554 LT 4129 514 LT ST
775 
(00) 3275 514 WT pop 0 originOffset 37 add RSS
776 
4129 514 MT 4129 514 LT 4136 473 LT 4556 473 LT 4563 514 LT ST
777 
4129 514 MT 4129 514 LT 4136 554 LT 4556 554 LT 4563 514 LT ST
778 
(02) 4143 514 WT pop 0 originOffset 37 add RSS
779 
4563 514 MT 4563 514 LT 4570 473 LT 6298 473 LT ST
780 
4563 514 MT 4563 514 LT 4570 554 LT 6298 554 LT ST
781 
(03) 4577 514 WT pop 0 originOffset 37 add RSS
782 
3045 658 MT 3912 658 LS
783 
3912 658 MT 3912 698 LS
784 
3912 698 MT 6298 698 LS
785 
3045 802 MT 3912 802 LS
786 
3912 802 MT 3912 842 LS
787 
3912 842 MT 6298 842 LS
788 
3045 946 MT 3261 946 LS
789 
3261 946 MT 3261 986 LS
790 
3261 986 MT 6298 986 LS
791 
3045 1090 MT 3261 1090 LS
792 
3261 1090 MT 3261 1090 LT 3268 1049 LT 6298 1049 LT ST
793 
3261 1090 MT 3261 1090 LT 3268 1130 LT 6298 1130 LT ST
794 
(0) 3275 1090 WT pop 0 originOffset 37 add RSS
795 
3045 1234 MT 3045 1274 LS
796 
3045 1274 MT 3261 1274 LS
797 
3261 1274 MT 3261 1194 LS
798 
3261 1194 MT 3478 1194 LS
799 
3478 1194 MT 3478 1274 LS
800 
3478 1274 MT 6298 1274 LS
801 
3045 1378 MT 3261 1378 LS
802 
3261 1378 MT 3261 1378 LT 3268 1337 LT 6298 1337 LT ST
803 
3261 1378 MT 3261 1378 LT 3268 1418 LT 6298 1418 LT ST
804 
(0) 3275 1378 WT pop 0 originOffset 37 add RSS
805 
3045 1522 MT 3261 1522 LS
806 
3261 1522 MT 3261 1522 LT 3268 1481 LT 6298 1481 LT ST
807 
3261 1522 MT 3261 1522 LT 3268 1562 LT 6298 1562 LT ST
808 
(0) 3275 1522 WT pop 0 originOffset 37 add RSS
809 
3045 1666 MT 3261 1666 LS
810 
3261 1666 MT 3261 1706 LS
811 
3261 1706 MT 6298 1706 LS
812 
3045 1810 MT 3261 1810 LS
813 
3261 1810 MT 3261 1810 LT 3268 1769 LT 6298 1769 LT ST
814 
3261 1810 MT 3261 1810 LT 3268 1850 LT 6298 1850 LT ST
815 
(0) 3275 1810 WT pop 0 originOffset 37 add RSS
816 
3045 1954 MT 3261 1954 LS
817 
3261 1954 MT 3261 1994 LS
818 
3261 1994 MT 6298 1994 LS
819 
3045 2098 MT 3261 2098 LS
820 
3261 2098 MT 3261 2138 LS
821 
3261 2138 MT 4129 2138 LS
822 
4129 2138 MT 4129 2098 LS
823 
4129 2098 MT 6298 2098 LS
824 
3045 2242 MT 3261 2242 LS
825 
3261 2242 MT 3261 2242 LT 3268 2201 LT 6298 2201 LT ST
826 
3261 2242 MT 3261 2242 LT 3268 2282 LT 6298 2282 LT ST
827 
(00000000) 3275 2242 WT pop 0 originOffset 37 add RSS
828 
3045 2386 MT 3261 2386 LS
829 
3261 2386 MT 3261 2386 LT 3268 2345 LT 4122 2345 LT 4129 2386 LT ST
830 
3261 2386 MT 3261 2386 LT 3268 2426 LT 4122 2426 LT 4129 2386 LT ST
831 
(0000) 3275 2386 WT pop 0 originOffset 37 add RSS
832 
4129 2386 MT 4129 2386 LT 4136 2345 LT 4556 2345 LT 4563 2386 LT ST
833 
4129 2386 MT 4129 2386 LT 4136 2426 LT 4556 2426 LT 4563 2386 LT ST
834 
(1000) 4143 2386 WT pop 0 originOffset 37 add RSS
835 
4563 2386 MT 4563 2386 LT 4570 2345 LT 6298 2345 LT ST
836 
4563 2386 MT 4563 2386 LT 4570 2426 LT 6298 2426 LT ST
837 
(1800) 4577 2386 WT pop 0 originOffset 37 add RSS
838 
3045 2530 MT 3261 2530 LS
839 
3261 2530 MT 3261 2530 LT 3268 2489 LT 4556 2489 LT 4563 2530 LT ST
840 
3261 2530 MT 3261 2530 LT 3268 2570 LT 4556 2570 LT 4563 2530 LT ST
841 
(0) 3275 2530 WT pop 0 originOffset 37 add RSS
842 
4563 2530 MT 4563 2530 LT 4570 2489 LT 4989 2489 LT 4996 2530 LT ST
843 
4563 2530 MT 4563 2530 LT 4570 2570 LT 4989 2570 LT 4996 2530 LT ST
844 
(1) 4577 2530 WT pop 0 originOffset 37 add RSS
845 
4996 2530 MT 4996 2530 LT 5003 2489 LT 5423 2489 LT 5430 2530 LT ST
846 
4996 2530 MT 4996 2530 LT 5003 2570 LT 5423 2570 LT 5430 2530 LT ST
847 
(2) 5010 2530 WT pop 0 originOffset 37 add RSS
848 
5430 2530 MT 5430 2530 LT 5437 2489 LT 5857 2489 LT 5864 2530 LT ST
849 
5430 2530 MT 5430 2530 LT 5437 2570 LT 5857 2570 LT 5864 2530 LT ST
850 
(3) 5444 2530 WT pop 0 originOffset 37 add RSS
851 
5864 2530 MT 5864 2530 LT 5871 2489 LT 6298 2489 LT ST
852 
5864 2530 MT 5864 2530 LT 5871 2570 LT 6298 2570 LT ST
853 
(4) 5878 2530 WT pop 0 originOffset 37 add RSS
854 
3045 2674 MT 3261 2674 LS
855 
3261 2674 MT 3261 2674 LT 3268 2633 LT 4989 2633 LT 4996 2674 LT ST
856 
3261 2674 MT 3261 2674 LT 3268 2714 LT 4989 2714 LT 4996 2674 LT ST
857 
(0) 3275 2674 WT pop 0 originOffset 37 add RSS
858 
4996 2674 MT 4996 2674 LT 5003 2633 LT 5423 2633 LT 5430 2674 LT ST
859 
4996 2674 MT 4996 2674 LT 5003 2714 LT 5423 2714 LT 5430 2674 LT ST
860 
(1) 5010 2674 WT pop 0 originOffset 37 add RSS
861 
5430 2674 MT 5430 2674 LT 5437 2633 LT 5857 2633 LT 5864 2674 LT ST
862 
5430 2674 MT 5430 2674 LT 5437 2714 LT 5857 2714 LT 5864 2674 LT ST
863 
(2) 5444 2674 WT pop 0 originOffset 37 add RSS
864 
5864 2674 MT 5864 2674 LT 5871 2633 LT 6298 2633 LT ST
865 
5864 2674 MT 5864 2674 LT 5871 2714 LT 6298 2714 LT ST
866 
(3) 5878 2674 WT pop 0 originOffset 37 add RSS
867 
3045 2818 MT 3912 2818 LS
868 
3912 2818 MT 3912 2858 LS
869 
3912 2858 MT 6298 2858 LS
870 
3045 2962 MT 3261 2962 LS
871 
3261 2962 MT 3261 2962 LT 3268 2921 LT 4989 2921 LT 4996 2962 LT ST
872 
3261 2962 MT 3261 2962 LT 3268 3002 LT 4989 3002 LT 4996 2962 LT ST
873 
(14410000) 3275 2962 WT pop 0 originOffset 37 add RSS
874 
4996 2962 MT 4996 2962 LT 5003 2921 LT 6298 2921 LT ST
875 
4996 2962 MT 4996 2962 LT 5003 3002 LT 6298 3002 LT ST
876 
(14610000) 5010 2962 WT pop 0 originOffset 37 add RSS
877 
3045 3106 MT 3261 3106 LS
878 
3261 3106 MT 3261 3106 LT 3268 3065 LT 4556 3065 LT 4563 3106 LT ST
879 
3261 3106 MT 3261 3106 LT 3268 3146 LT 4556 3146 LT 4563 3106 LT ST
880 
(00) 3275 3106 WT pop 0 originOffset 37 add RSS
881 
4563 3106 MT 4563 3106 LT 4570 3065 LT 4989 3065 LT 4996 3106 LT ST
882 
4563 3106 MT 4563 3106 LT 4570 3146 LT 4989 3146 LT 4996 3106 LT ST
883 
(02) 4577 3106 WT pop 0 originOffset 37 add RSS
884 
4996 3106 MT 4996 3106 LT 5003 3065 LT 6298 3065 LT ST
885 
4996 3106 MT 4996 3106 LT 5003 3146 LT 6298 3146 LT ST
886 
(03) 5010 3106 WT pop 0 originOffset 37 add RSS
887 
3045 3250 MT 3261 3250 LS
888 
3261 3250 MT 3261 3290 LS
889 
3261 3290 MT 6298 3290 LS
890 
% draw timeline
891 
3088 4533 MT 3088 4570 LS
892 
3132 4533 MT 3132 4570 LS
893 
3175 4533 MT 3175 4570 LS
894 
3218 4533 MT 3218 4570 LS
895 
3262 4533 MT 3262 4570 LS
896 
3305 4533 MT 3305 4570 LS
897 
3349 4533 MT 3349 4570 LS
898 
3392 4533 MT 3392 4570 LS
899 
3435 4533 MT 3435 4570 LS
900 
(0) 3045 4649 WT TS RSS
901 
3521 4533 MT 3521 4570 LS
902 
3565 4533 MT 3565 4570 LS
903 
3608 4533 MT 3608 4570 LS
904 
3651 4533 MT 3651 4570 LS
905 
3695 4533 MT 3695 4570 LS
906 
3738 4533 MT 3738 4570 LS
907 
3782 4533 MT 3782 4570 LS
908 
3825 4533 MT 3825 4570 LS
909 
3868 4533 MT 3868 4570 LS
910 
3478 4506 MT 3478 4570 LS
911 
3955 4533 MT 3955 4570 LS
912 
3999 4533 MT 3999 4570 LS
913 
4042 4533 MT 4042 4570 LS
914 
4085 4533 MT 4085 4570 LS
915 
4129 4533 MT 4129 4570 LS
916 
4172 4533 MT 4172 4570 LS
917 
4216 4533 MT 4216 4570 LS
918 
4259 4533 MT 4259 4570 LS
919 
4302 4533 MT 4302 4570 LS
920 
3912 4506 MT 3912 4570 LS
921 
(20) 3912 4649 WT TS RSS
922 
4389 4533 MT 4389 4570 LS
923 
4433 4533 MT 4433 4570 LS
924 
4476 4533 MT 4476 4570 LS
925 
4519 4533 MT 4519 4570 LS
926 
4563 4533 MT 4563 4570 LS
927 
4606 4533 MT 4606 4570 LS
928 
4650 4533 MT 4650 4570 LS
929 
4693 4533 MT 4693 4570 LS
930 
4736 4533 MT 4736 4570 LS
931 
4346 4506 MT 4346 4570 LS
932 
4822 4533 MT 4822 4570 LS
933 
4866 4533 MT 4866 4570 LS
934 
4909 4533 MT 4909 4570 LS
935 
4952 4533 MT 4952 4570 LS
936 
4996 4533 MT 4996 4570 LS
937 
5039 4533 MT 5039 4570 LS
938 
5083 4533 MT 5083 4570 LS
939 
5126 4533 MT 5126 4570 LS
940 
5169 4533 MT 5169 4570 LS
941 
4779 4506 MT 4779 4570 LS
942 
(40) 4779 4649 WT TS RSS
943 
5256 4533 MT 5256 4570 LS
944 
5300 4533 MT 5300 4570 LS
945 
5343 4533 MT 5343 4570 LS
946 
5386 4533 MT 5386 4570 LS
947 
5430 4533 MT 5430 4570 LS
948 
5473 4533 MT 5473 4570 LS
949 
5517 4533 MT 5517 4570 LS
950 
5560 4533 MT 5560 4570 LS
951 
5603 4533 MT 5603 4570 LS
952 
5213 4506 MT 5213 4570 LS
953 
5690 4533 MT 5690 4570 LS
954 
5734 4533 MT 5734 4570 LS
955 
5777 4533 MT 5777 4570 LS
956 
5820 4533 MT 5820 4570 LS
957 
5864 4533 MT 5864 4570 LS
958 
5907 4533 MT 5907 4570 LS
959 
5951 4533 MT 5951 4570 LS
960 
5994 4533 MT 5994 4570 LS
961 
6037 4533 MT 6037 4570 LS
962 
5647 4506 MT 5647 4570 LS
963 
(60) 5647 4649 WT TS RSS
964 
6124 4533 MT 6124 4570 LS
965 
6168 4533 MT 6168 4570 LS
966 
6211 4533 MT 6211 4570 LS
967 
6254 4533 MT 6254 4570 LS
968 
6298 4533 MT 6298 4570 LS
969 
6341 4533 MT 6341 4570 LS
970 
6385 4533 MT 6385 4570 LS
971 
6428 4533 MT 6428 4570 LS
972 
6471 4533 MT 6471 4570 LS
973 
6081 4506 MT 6081 4570 LS
974 
% draw grid
975 
3478 300 MT 3478 4506 LS
976 
3912 300 MT 3912 4506 LS
977 
4346 300 MT 4346 4506 LS
978 
4779 300 MT 4779 4506 LS
979 
5213 300 MT 5213 4506 LS
980 
5647 300 MT 5647 4506 LS
981 
6081 300 MT 6081 4506 LS
982 
% draw waveforms
983 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) 3008 409 WT TSE RSS
984 
3471 300 MT 3485 300 LS
985 
3905 300 MT 3919 300 LS
986 
4339 300 MT 4353 300 LS
987 
4772 300 MT 4786 300 LS
988 
5206 300 MT 5220 300 LS
989 
5640 300 MT 5654 300 LS
990 
6074 300 MT 6088 300 LS
991 
3045 370 MT 3912 370 LS
992 
3912 370 MT 3912 370 LT 3919 329 LT 6298 329 LT ST
993 
3912 370 MT 3912 370 LT 3919 410 LT 6298 410 LT ST
994 
(00) 3926 370 WT pop 0 originOffset 37 add RSS
995 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) 3008 553 WT TSE RSS
996 
3471 444 MT 3485 444 LS
997 
3905 444 MT 3919 444 LS
998 
4339 444 MT 4353 444 LS
999 
4772 444 MT 4786 444 LS
1000 
5206 444 MT 5220 444 LS
1001 
5640 444 MT 5654 444 LS
1002 
6074 444 MT 6088 444 LS
1003 
3045 514 MT 3261 514 LS
1004 
3261 514 MT 3261 514 LT 3268 473 LT 4122 473 LT 4129 514 LT ST
1005 
3261 514 MT 3261 514 LT 3268 554 LT 4122 554 LT 4129 514 LT ST
1006 
(00) 3275 514 WT pop 0 originOffset 37 add RSS
1007 
4129 514 MT 4129 514 LT 4136 473 LT 4556 473 LT 4563 514 LT ST
1008 
4129 514 MT 4129 514 LT 4136 554 LT 4556 554 LT 4563 514 LT ST
1009 
(02) 4143 514 WT pop 0 originOffset 37 add RSS
1010 
4563 514 MT 4563 514 LT 4570 473 LT 6298 473 LT ST
1011 
4563 514 MT 4563 514 LT 4570 554 LT 6298 554 LT ST
1012 
(03) 4577 514 WT pop 0 originOffset 37 add RSS
1013 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) 3008 697 WT TSE RSS
1014 
3471 588 MT 3485 588 LS
1015 
3905 588 MT 3919 588 LS
1016 
4339 588 MT 4353 588 LS
1017 
4772 588 MT 4786 588 LS
1018 
5206 588 MT 5220 588 LS
1019 
5640 588 MT 5654 588 LS
1020 
6074 588 MT 6088 588 LS
1021 
3045 658 MT 3912 658 LS
1022 
3912 658 MT 3912 698 LS
1023 
3912 698 MT 6298 698 LS
1024 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) 3008 841 WT TSE RSS
1025 
3471 732 MT 3485 732 LS
1026 
3905 732 MT 3919 732 LS
1027 
4339 732 MT 4353 732 LS
1028 
4772 732 MT 4786 732 LS
1029 
5206 732 MT 5220 732 LS
1030 
5640 732 MT 5654 732 LS
1031 
6074 732 MT 6088 732 LS
1032 
3045 802 MT 3912 802 LS
1033 
3912 802 MT 3912 842 LS
1034 
3912 842 MT 6298 842 LS
1035 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) 3008 985 WT TSE RSS
1036 
3471 876 MT 3485 876 LS
1037 
3905 876 MT 3919 876 LS
1038 
4339 876 MT 4353 876 LS
1039 
4772 876 MT 4786 876 LS
1040 
5206 876 MT 5220 876 LS
1041 
5640 876 MT 5654 876 LS
1042 
6074 876 MT 6088 876 LS
1043 
3045 946 MT 3261 946 LS
1044 
3261 946 MT 3261 986 LS
1045 
3261 986 MT 6298 986 LS
1046 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) 3008 1129 WT TSE RSS
1047 
3471 1020 MT 3485 1020 LS
1048 
3905 1020 MT 3919 1020 LS
1049 
4339 1020 MT 4353 1020 LS
1050 
4772 1020 MT 4786 1020 LS
1051 
5206 1020 MT 5220 1020 LS
1052 
5640 1020 MT 5654 1020 LS
1053 
6074 1020 MT 6088 1020 LS
1054 
3045 1090 MT 3261 1090 LS
1055 
3261 1090 MT 3261 1090 LT 3268 1049 LT 6298 1049 LT ST
1056 
3261 1090 MT 3261 1090 LT 3268 1130 LT 6298 1130 LT ST
1057 
(0) 3275 1090 WT pop 0 originOffset 37 add RSS
1058 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) 3008 1273 WT TSE RSS
1059 
3471 1164 MT 3485 1164 LS
1060 
3905 1164 MT 3919 1164 LS
1061 
4339 1164 MT 4353 1164 LS
1062 
4772 1164 MT 4786 1164 LS
1063 
5206 1164 MT 5220 1164 LS
1064 
5640 1164 MT 5654 1164 LS
1065 
6074 1164 MT 6088 1164 LS
1066 
3045 1234 MT 3045 1274 LS
1067 
3045 1274 MT 3261 1274 LS
1068 
3261 1274 MT 3261 1194 LS
1069 
3261 1194 MT 3478 1194 LS
1070 
3478 1194 MT 3478 1274 LS
1071 
3478 1274 MT 6298 1274 LS
1072 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) 3008 1417 WT TSE RSS
1073 
3471 1308 MT 3485 1308 LS
1074 
3905 1308 MT 3919 1308 LS
1075 
4339 1308 MT 4353 1308 LS
1076 
4772 1308 MT 4786 1308 LS
1077 
5206 1308 MT 5220 1308 LS
1078 
5640 1308 MT 5654 1308 LS
1079 
6074 1308 MT 6088 1308 LS
1080 
3045 1378 MT 3261 1378 LS
1081 
3261 1378 MT 3261 1378 LT 3268 1337 LT 6298 1337 LT ST
1082 
3261 1378 MT 3261 1378 LT 3268 1418 LT 6298 1418 LT ST
1083 
(0) 3275 1378 WT pop 0 originOffset 37 add RSS
1084 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) 3008 1561 WT TSE RSS
1085 
3471 1452 MT 3485 1452 LS
1086 
3905 1452 MT 3919 1452 LS
1087 
4339 1452 MT 4353 1452 LS
1088 
4772 1452 MT 4786 1452 LS
1089 
5206 1452 MT 5220 1452 LS
1090 
5640 1452 MT 5654 1452 LS
1091 
6074 1452 MT 6088 1452 LS
1092 
3045 1522 MT 3261 1522 LS
1093 
3261 1522 MT 3261 1522 LT 3268 1481 LT 6298 1481 LT ST
1094 
3261 1522 MT 3261 1522 LT 3268 1562 LT 6298 1562 LT ST
1095 
(0) 3275 1522 WT pop 0 originOffset 37 add RSS
1096 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) 3008 1705 WT TSE RSS
1097 
3471 1596 MT 3485 1596 LS
1098 
3905 1596 MT 3919 1596 LS
1099 
4339 1596 MT 4353 1596 LS
1100 
4772 1596 MT 4786 1596 LS
1101 
5206 1596 MT 5220 1596 LS
1102 
5640 1596 MT 5654 1596 LS
1103 
6074 1596 MT 6088 1596 LS
1104 
3045 1666 MT 3261 1666 LS
1105 
3261 1666 MT 3261 1706 LS
1106 
3261 1706 MT 6298 1706 LS
1107 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) 3008 1849 WT TSE RSS
1108 
3471 1740 MT 3485 1740 LS
1109 
3905 1740 MT 3919 1740 LS
1110 
4339 1740 MT 4353 1740 LS
1111 
4772 1740 MT 4786 1740 LS
1112 
5206 1740 MT 5220 1740 LS
1113 
5640 1740 MT 5654 1740 LS
1114 
6074 1740 MT 6088 1740 LS
1115 
3045 1810 MT 3261 1810 LS
1116 
3261 1810 MT 3261 1810 LT 3268 1769 LT 6298 1769 LT ST
1117 
3261 1810 MT 3261 1810 LT 3268 1850 LT 6298 1850 LT ST
1118 
(0) 3275 1810 WT pop 0 originOffset 37 add RSS
1119 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) 3008 1993 WT TSE RSS
1120 
3471 1884 MT 3485 1884 LS
1121 
3905 1884 MT 3919 1884 LS
1122 
4339 1884 MT 4353 1884 LS
1123 
4772 1884 MT 4786 1884 LS
1124 
5206 1884 MT 5220 1884 LS
1125 
5640 1884 MT 5654 1884 LS
1126 
6074 1884 MT 6088 1884 LS
1127 
3045 1954 MT 3261 1954 LS
1128 
3261 1954 MT 3261 1994 LS
1129 
3261 1994 MT 6298 1994 LS
1130 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) 3008 2137 WT TSE RSS
1131 
3471 2028 MT 3485 2028 LS
1132 
3905 2028 MT 3919 2028 LS
1133 
4339 2028 MT 4353 2028 LS
1134 
4772 2028 MT 4786 2028 LS
1135 
5206 2028 MT 5220 2028 LS
1136 
5640 2028 MT 5654 2028 LS
1137 
6074 2028 MT 6088 2028 LS
1138 
3045 2098 MT 3261 2098 LS
1139 
3261 2098 MT 3261 2138 LS
1140 
3261 2138 MT 4129 2138 LS
1141 
4129 2138 MT 4129 2098 LS
1142 
4129 2098 MT 6298 2098 LS
1143 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) 3008 2281 WT TSE RSS
1144 
3471 2172 MT 3485 2172 LS
1145 
3905 2172 MT 3919 2172 LS
1146 
4339 2172 MT 4353 2172 LS
1147 
4772 2172 MT 4786 2172 LS
1148 
5206 2172 MT 5220 2172 LS
1149 
5640 2172 MT 5654 2172 LS
1150 
6074 2172 MT 6088 2172 LS
1151 
3045 2242 MT 3261 2242 LS
1152 
3261 2242 MT 3261 2242 LT 3268 2201 LT 6298 2201 LT ST
1153 
3261 2242 MT 3261 2242 LT 3268 2282 LT 6298 2282 LT ST
1154 
(00000000) 3275 2242 WT pop 0 originOffset 37 add RSS
1155 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) 3008 2425 WT TSE RSS
1156 
3471 2316 MT 3485 2316 LS
1157 
3905 2316 MT 3919 2316 LS
1158 
4339 2316 MT 4353 2316 LS
1159 
4772 2316 MT 4786 2316 LS
1160 
5206 2316 MT 5220 2316 LS
1161 
5640 2316 MT 5654 2316 LS
1162 
6074 2316 MT 6088 2316 LS
1163 
3045 2386 MT 3261 2386 LS
1164 
3261 2386 MT 3261 2386 LT 3268 2345 LT 4122 2345 LT 4129 2386 LT ST
1165 
3261 2386 MT 3261 2386 LT 3268 2426 LT 4122 2426 LT 4129 2386 LT ST
1166 
(0000) 3275 2386 WT pop 0 originOffset 37 add RSS
1167 
4129 2386 MT 4129 2386 LT 4136 2345 LT 4556 2345 LT 4563 2386 LT ST
1168 
4129 2386 MT 4129 2386 LT 4136 2426 LT 4556 2426 LT 4563 2386 LT ST
1169 
(1000) 4143 2386 WT pop 0 originOffset 37 add RSS
1170 
4563 2386 MT 4563 2386 LT 4570 2345 LT 6298 2345 LT ST
1171 
4563 2386 MT 4563 2386 LT 4570 2426 LT 6298 2426 LT ST
1172 
(1800) 4577 2386 WT pop 0 originOffset 37 add RSS
1173 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) 3008 2569 WT TSE RSS
1174 
3471 2460 MT 3485 2460 LS
1175 
3905 2460 MT 3919 2460 LS
1176 
4339 2460 MT 4353 2460 LS
1177 
4772 2460 MT 4786 2460 LS
1178 
5206 2460 MT 5220 2460 LS
1179 
5640 2460 MT 5654 2460 LS
1180 
6074 2460 MT 6088 2460 LS
1181 
3045 2530 MT 3261 2530 LS
1182 
3261 2530 MT 3261 2530 LT 3268 2489 LT 4556 2489 LT 4563 2530 LT ST
1183 
3261 2530 MT 3261 2530 LT 3268 2570 LT 4556 2570 LT 4563 2530 LT ST
1184 
(0) 3275 2530 WT pop 0 originOffset 37 add RSS
1185 
4563 2530 MT 4563 2530 LT 4570 2489 LT 4989 2489 LT 4996 2530 LT ST
1186 
4563 2530 MT 4563 2530 LT 4570 2570 LT 4989 2570 LT 4996 2530 LT ST
1187 
(1) 4577 2530 WT pop 0 originOffset 37 add RSS
1188 
4996 2530 MT 4996 2530 LT 5003 2489 LT 5423 2489 LT 5430 2530 LT ST
1189 
4996 2530 MT 4996 2530 LT 5003 2570 LT 5423 2570 LT 5430 2530 LT ST
1190 
(2) 5010 2530 WT pop 0 originOffset 37 add RSS
1191 
5430 2530 MT 5430 2530 LT 5437 2489 LT 5857 2489 LT 5864 2530 LT ST
1192 
5430 2530 MT 5430 2530 LT 5437 2570 LT 5857 2570 LT 5864 2530 LT ST
1193 
(3) 5444 2530 WT pop 0 originOffset 37 add RSS
1194 
5864 2530 MT 5864 2530 LT 5871 2489 LT 6298 2489 LT ST
1195 
5864 2530 MT 5864 2530 LT 5871 2570 LT 6298 2570 LT ST
1196 
(4) 5878 2530 WT pop 0 originOffset 37 add RSS
1197 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) 3008 2713 WT TSE RSS
1198 
3471 2604 MT 3485 2604 LS
1199 
3905 2604 MT 3919 2604 LS
1200 
4339 2604 MT 4353 2604 LS
1201 
4772 2604 MT 4786 2604 LS
1202 
5206 2604 MT 5220 2604 LS
1203 
5640 2604 MT 5654 2604 LS
1204 
6074 2604 MT 6088 2604 LS
1205 
3045 2674 MT 3261 2674 LS
1206 
3261 2674 MT 3261 2674 LT 3268 2633 LT 4989 2633 LT 4996 2674 LT ST
1207 
3261 2674 MT 3261 2674 LT 3268 2714 LT 4989 2714 LT 4996 2674 LT ST
1208 
(0) 3275 2674 WT pop 0 originOffset 37 add RSS
1209 
4996 2674 MT 4996 2674 LT 5003 2633 LT 5423 2633 LT 5430 2674 LT ST
1210 
4996 2674 MT 4996 2674 LT 5003 2714 LT 5423 2714 LT 5430 2674 LT ST
1211 
(1) 5010 2674 WT pop 0 originOffset 37 add RSS
1212 
5430 2674 MT 5430 2674 LT 5437 2633 LT 5857 2633 LT 5864 2674 LT ST
1213 
5430 2674 MT 5430 2674 LT 5437 2714 LT 5857 2714 LT 5864 2674 LT ST
1214 
(2) 5444 2674 WT pop 0 originOffset 37 add RSS
1215 
5864 2674 MT 5864 2674 LT 5871 2633 LT 6298 2633 LT ST
1216 
5864 2674 MT 5864 2674 LT 5871 2714 LT 6298 2714 LT ST
1217 
(3) 5878 2674 WT pop 0 originOffset 37 add RSS
1218 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) 3008 2857 WT TSE RSS
1219 
3471 2748 MT 3485 2748 LS
1220 
3905 2748 MT 3919 2748 LS
1221 
4339 2748 MT 4353 2748 LS
1222 
4772 2748 MT 4786 2748 LS
1223 
5206 2748 MT 5220 2748 LS
1224 
5640 2748 MT 5654 2748 LS
1225 
6074 2748 MT 6088 2748 LS
1226 
3045 2818 MT 3912 2818 LS
1227 
3912 2818 MT 3912 2858 LS
1228 
3912 2858 MT 6298 2858 LS
1229 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) 3008 3001 WT TSE RSS
1230 
3471 2892 MT 3485 2892 LS
1231 
3905 2892 MT 3919 2892 LS
1232 
4339 2892 MT 4353 2892 LS
1233 
4772 2892 MT 4786 2892 LS
1234 
5206 2892 MT 5220 2892 LS
1235 
5640 2892 MT 5654 2892 LS
1236 
6074 2892 MT 6088 2892 LS
1237 
3045 2962 MT 3261 2962 LS
1238 
3261 2962 MT 3261 2962 LT 3268 2921 LT 4989 2921 LT 4996 2962 LT ST
1239 
3261 2962 MT 3261 2962 LT 3268 3002 LT 4989 3002 LT 4996 2962 LT ST
1240 
(14410000) 3275 2962 WT pop 0 originOffset 37 add RSS
1241 
4996 2962 MT 4996 2962 LT 5003 2921 LT 6298 2921 LT ST
1242 
4996 2962 MT 4996 2962 LT 5003 3002 LT 6298 3002 LT ST
1243 
(14610000) 5010 2962 WT pop 0 originOffset 37 add RSS
1244 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) 3008 3145 WT TSE RSS
1245 
3471 3036 MT 3485 3036 LS
1246 
3905 3036 MT 3919 3036 LS
1247 
4339 3036 MT 4353 3036 LS
1248 
4772 3036 MT 4786 3036 LS
1249 
5206 3036 MT 5220 3036 LS
1250 
5640 3036 MT 5654 3036 LS
1251 
6074 3036 MT 6088 3036 LS
1252 
3045 3106 MT 3261 3106 LS
1253 
3261 3106 MT 3261 3106 LT 3268 3065 LT 4556 3065 LT 4563 3106 LT ST
1254 
3261 3106 MT 3261 3106 LT 3268 3146 LT 4556 3146 LT 4563 3106 LT ST
1255 
(00) 3275 3106 WT pop 0 originOffset 37 add RSS
1256 
4563 3106 MT 4563 3106 LT 4570 3065 LT 4989 3065 LT 4996 3106 LT ST
1257 
4563 3106 MT 4563 3106 LT 4570 3146 LT 4989 3146 LT 4996 3106 LT ST
1258 
(02) 4577 3106 WT pop 0 originOffset 37 add RSS
1259 
4996 3106 MT 4996 3106 LT 5003 3065 LT 6298 3065 LT ST
1260 
4996 3106 MT 4996 3106 LT 5003 3146 LT 6298 3146 LT ST
1261 
(03) 5010 3106 WT pop 0 originOffset 37 add RSS
1262 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) 3008 3289 WT TSE RSS
1263 
3471 3180 MT 3485 3180 LS
1264 
3905 3180 MT 3919 3180 LS
1265 
4339 3180 MT 4353 3180 LS
1266 
4772 3180 MT 4786 3180 LS
1267 
5206 3180 MT 5220 3180 LS
1268 
5640 3180 MT 5654 3180 LS
1269 
6074 3180 MT 6088 3180 LS
1270 
3045 3250 MT 3261 3250 LS
1271 
3261 3250 MT 3261 3290 LS
1272 
3261 3290 MT 6298 3290 LS
1273 
% draw footer
1274 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 1 Page: 2) 300 4799 WT TSW RSS
1275 
grestore
1276 
showpage
1277 
%%Page: 3 3
1278 
gsave
1279 
90 rotate 0.12 dup neg scale
1280 
% dump string table
1281 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
1282 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
1283 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
1284 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
1285 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
1286 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
1287 
/ARC {5 -2 roll SX 5 2 roll arc} def
1288 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
1289 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
1290 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
1291 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
1292 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
1293 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
1294 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
1295 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
1296 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
1297 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
1298 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
1299 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
1300 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
1301 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
1302 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
1303 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
1304 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
1305 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
1306 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
1307 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
1308 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
1309 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
1310 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
1311 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
1312 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
1313 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
1314 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
1315 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
1316 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
1317 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
1318 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
1319 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
1320 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
1321 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
1322 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
1323 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
1324 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
1325 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
1326 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
1327 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
1328 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
1329 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
1330 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
1331 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
1332 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
1333 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
1334 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
1335 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
1336 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
1337 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
1338 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
1339 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
1340 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
1341 
% draw waveform shading
1342 
[] 0 SD
1343 
2.995 setlinewidth
1344 
 
1345 
 
1346 
 
1347 
3045 329 MT 3045 329 LT 6298 329 LT ST
1348 
3045 410 MT 3045 410 LT 6298 410 LT ST
1349 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
1350 
3045 473 MT 3045 473 LT 6298 473 LT ST
1351 
3045 554 MT 3045 554 LT 6298 554 LT ST
1352 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
1353 
3045 617 MT 3045 617 LT 6298 617 LT ST
1354 
3045 698 MT 3045 698 LT 6298 698 LT ST
1355 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
1356 
3045 842 MT 6298 842 LS
1357 
3045 986 MT 3045 906 LS
1358 
3045 906 MT 3261 906 LS
1359 
3261 906 MT 3261 986 LS
1360 
3261 986 MT 3478 986 LS
1361 
3478 986 MT 3478 906 LS
1362 
3478 906 MT 3695 906 LS
1363 
3695 906 MT 3695 986 LS
1364 
3695 986 MT 3912 986 LS
1365 
3912 986 MT 3912 906 LS
1366 
3912 906 MT 4129 906 LS
1367 
4129 906 MT 4129 986 LS
1368 
4129 986 MT 4346 986 LS
1369 
4346 986 MT 4346 906 LS
1370 
4346 906 MT 4563 906 LS
1371 
4563 906 MT 4563 986 LS
1372 
4563 986 MT 4779 986 LS
1373 
4779 986 MT 4779 906 LS
1374 
4779 906 MT 4996 906 LS
1375 
4996 906 MT 4996 986 LS
1376 
4996 986 MT 5213 986 LS
1377 
5213 986 MT 5213 906 LS
1378 
5213 906 MT 5430 906 LS
1379 
5430 906 MT 5430 986 LS
1380 
5430 986 MT 5647 986 LS
1381 
5647 986 MT 5647 906 LS
1382 
5647 906 MT 5864 906 LS
1383 
5864 906 MT 5864 986 LS
1384 
5864 986 MT 6081 986 LS
1385 
6081 986 MT 6081 906 LS
1386 
6081 906 MT 6298 906 LS
1387 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
1388 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
1389 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
1390 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
1391 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
1392 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
1393 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
1394 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
1395 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
1396 
3045 1522 MT 6298 1522 LS
1397 
3045 1706 MT 6298 1706 LS
1398 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
1399 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
1400 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
1401 
3045 1994 MT 6298 1994 LS
1402 
3045 2058 MT 6298 2058 LS
1403 
3045 2282 MT 6298 2282 LS
1404 
3045 2386 MT 6298 2386 LS
1405 
3045 2570 MT 6298 2570 LS
1406 
3045 2714 MT 6298 2714 LS
1407 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
1408 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
1409 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
1410 
3045 3002 MT 6298 3002 LS
1411 
3045 3066 MT 6298 3066 LS
1412 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
1413 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
1414 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
1415 
3045 3434 MT 6298 3434 LS
1416 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
1417 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
1418 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
1419 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
1420 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
1421 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
1422 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
1423 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
1424 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
1425 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
1426 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
1427 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
1428 
3045 4154 MT 6298 4154 LS
1429 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
1430 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
1431 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
1432 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
1433 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
1434 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
1435 
% draw timeline
1436 
3088 4533 MT 3088 4570 LS
1437 
3132 4533 MT 3132 4570 LS
1438 
3175 4533 MT 3175 4570 LS
1439 
3218 4533 MT 3218 4570 LS
1440 
3304 4533 MT 3304 4570 LS
1441 
3348 4533 MT 3348 4570 LS
1442 
3391 4533 MT 3391 4570 LS
1443 
3434 4533 MT 3434 4570 LS
1444 
3478 4533 MT 3478 4570 LS
1445 
3521 4533 MT 3521 4570 LS
1446 
3565 4533 MT 3565 4570 LS
1447 
3608 4533 MT 3608 4570 LS
1448 
3651 4533 MT 3651 4570 LS
1449 
3261 4506 MT 3261 4570 LS
1450 
(80) 3261 4649 WT TS RSS
1451 
3738 4533 MT 3738 4570 LS
1452 
3782 4533 MT 3782 4570 LS
1453 
3825 4533 MT 3825 4570 LS
1454 
3868 4533 MT 3868 4570 LS
1455 
3912 4533 MT 3912 4570 LS
1456 
3955 4533 MT 3955 4570 LS
1457 
3999 4533 MT 3999 4570 LS
1458 
4042 4533 MT 4042 4570 LS
1459 
4085 4533 MT 4085 4570 LS
1460 
3695 4506 MT 3695 4570 LS
1461 
4172 4533 MT 4172 4570 LS
1462 
4216 4533 MT 4216 4570 LS
1463 
4259 4533 MT 4259 4570 LS
1464 
4302 4533 MT 4302 4570 LS
1465 
4346 4533 MT 4346 4570 LS
1466 
4389 4533 MT 4389 4570 LS
1467 
4433 4533 MT 4433 4570 LS
1468 
4476 4533 MT 4476 4570 LS
1469 
4519 4533 MT 4519 4570 LS
1470 
4129 4506 MT 4129 4570 LS
1471 
(100) 4129 4649 WT TS RSS
1472 
4606 4533 MT 4606 4570 LS
1473 
4650 4533 MT 4650 4570 LS
1474 
4693 4533 MT 4693 4570 LS
1475 
4736 4533 MT 4736 4570 LS
1476 
4780 4533 MT 4780 4570 LS
1477 
4823 4533 MT 4823 4570 LS
1478 
4867 4533 MT 4867 4570 LS
1479 
4910 4533 MT 4910 4570 LS
1480 
4953 4533 MT 4953 4570 LS
1481 
4563 4506 MT 4563 4570 LS
1482 
5039 4533 MT 5039 4570 LS
1483 
5083 4533 MT 5083 4570 LS
1484 
5126 4533 MT 5126 4570 LS
1485 
5169 4533 MT 5169 4570 LS
1486 
5213 4533 MT 5213 4570 LS
1487 
5256 4533 MT 5256 4570 LS
1488 
5300 4533 MT 5300 4570 LS
1489 
5343 4533 MT 5343 4570 LS
1490 
5386 4533 MT 5386 4570 LS
1491 
4996 4506 MT 4996 4570 LS
1492 
(120) 4996 4649 WT TS RSS
1493 
5473 4533 MT 5473 4570 LS
1494 
5517 4533 MT 5517 4570 LS
1495 
5560 4533 MT 5560 4570 LS
1496 
5603 4533 MT 5603 4570 LS
1497 
5647 4533 MT 5647 4570 LS
1498 
5690 4533 MT 5690 4570 LS
1499 
5734 4533 MT 5734 4570 LS
1500 
5777 4533 MT 5777 4570 LS
1501 
5820 4533 MT 5820 4570 LS
1502 
5430 4506 MT 5430 4570 LS
1503 
5907 4533 MT 5907 4570 LS
1504 
5951 4533 MT 5951 4570 LS
1505 
5994 4533 MT 5994 4570 LS
1506 
6037 4533 MT 6037 4570 LS
1507 
6081 4533 MT 6081 4570 LS
1508 
6124 4533 MT 6124 4570 LS
1509 
6168 4533 MT 6168 4570 LS
1510 
6211 4533 MT 6211 4570 LS
1511 
6254 4533 MT 6254 4570 LS
1512 
5864 4506 MT 5864 4570 LS
1513 
(140) 5864 4649 WT TS RSS
1514 
6341 4533 MT 6341 4570 LS
1515 
6385 4533 MT 6385 4570 LS
1516 
6428 4533 MT 6428 4570 LS
1517 
6471 4533 MT 6471 4570 LS
1518 
6515 4533 MT 6515 4570 LS
1519 
6558 4533 MT 6558 4570 LS
1520 
6602 4533 MT 6602 4570 LS
1521 
6645 4533 MT 6645 4570 LS
1522 
6688 4533 MT 6688 4570 LS
1523 
6298 4506 MT 6298 4570 LS
1524 
% draw grid
1525 
3261 300 MT 3261 4506 LS
1526 
3695 300 MT 3695 4506 LS
1527 
4129 300 MT 4129 4506 LS
1528 
4563 300 MT 4563 4506 LS
1529 
4996 300 MT 4996 4506 LS
1530 
5430 300 MT 5430 4506 LS
1531 
5864 300 MT 5864 4506 LS
1532 
6298 300 MT 6298 4506 LS
1533 
% draw waveforms
1534 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) 3008 409 WT TSE RSS
1535 
3254 300 MT 3268 300 LS
1536 
3688 300 MT 3702 300 LS
1537 
4122 300 MT 4136 300 LS
1538 
4556 300 MT 4570 300 LS
1539 
4989 300 MT 5003 300 LS
1540 
5423 300 MT 5437 300 LS
1541 
5857 300 MT 5871 300 LS
1542 
6291 300 MT 6305 300 LS
1543 
3045 329 MT 3045 329 LT 6298 329 LT ST
1544 
3045 410 MT 3045 410 LT 6298 410 LT ST
1545 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
1546 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) 3008 553 WT TSE RSS
1547 
3254 444 MT 3268 444 LS
1548 
3688 444 MT 3702 444 LS
1549 
4122 444 MT 4136 444 LS
1550 
4556 444 MT 4570 444 LS
1551 
4989 444 MT 5003 444 LS
1552 
5423 444 MT 5437 444 LS
1553 
5857 444 MT 5871 444 LS
1554 
6291 444 MT 6305 444 LS
1555 
3045 473 MT 3045 473 LT 6298 473 LT ST
1556 
3045 554 MT 3045 554 LT 6298 554 LT ST
1557 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
1558 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) 3008 697 WT TSE RSS
1559 
3254 588 MT 3268 588 LS
1560 
3688 588 MT 3702 588 LS
1561 
4122 588 MT 4136 588 LS
1562 
4556 588 MT 4570 588 LS
1563 
4989 588 MT 5003 588 LS
1564 
5423 588 MT 5437 588 LS
1565 
5857 588 MT 5871 588 LS
1566 
6291 588 MT 6305 588 LS
1567 
3045 617 MT 3045 617 LT 6298 617 LT ST
1568 
3045 698 MT 3045 698 LT 6298 698 LT ST
1569 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
1570 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) 3008 841 WT TSE RSS
1571 
3254 732 MT 3268 732 LS
1572 
3688 732 MT 3702 732 LS
1573 
4122 732 MT 4136 732 LS
1574 
4556 732 MT 4570 732 LS
1575 
4989 732 MT 5003 732 LS
1576 
5423 732 MT 5437 732 LS
1577 
5857 732 MT 5871 732 LS
1578 
6291 732 MT 6305 732 LS
1579 
3045 842 MT 6298 842 LS
1580 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) 3008 985 WT TSE RSS
1581 
3254 876 MT 3268 876 LS
1582 
3688 876 MT 3702 876 LS
1583 
4122 876 MT 4136 876 LS
1584 
4556 876 MT 4570 876 LS
1585 
4989 876 MT 5003 876 LS
1586 
5423 876 MT 5437 876 LS
1587 
5857 876 MT 5871 876 LS
1588 
6291 876 MT 6305 876 LS
1589 
3045 986 MT 3045 906 LS
1590 
3045 906 MT 3261 906 LS
1591 
3261 906 MT 3261 986 LS
1592 
3261 986 MT 3478 986 LS
1593 
3478 986 MT 3478 906 LS
1594 
3478 906 MT 3695 906 LS
1595 
3695 906 MT 3695 986 LS
1596 
3695 986 MT 3912 986 LS
1597 
3912 986 MT 3912 906 LS
1598 
3912 906 MT 4129 906 LS
1599 
4129 906 MT 4129 986 LS
1600 
4129 986 MT 4346 986 LS
1601 
4346 986 MT 4346 906 LS
1602 
4346 906 MT 4563 906 LS
1603 
4563 906 MT 4563 986 LS
1604 
4563 986 MT 4779 986 LS
1605 
4779 986 MT 4779 906 LS
1606 
4779 906 MT 4996 906 LS
1607 
4996 906 MT 4996 986 LS
1608 
4996 986 MT 5213 986 LS
1609 
5213 986 MT 5213 906 LS
1610 
5213 906 MT 5430 906 LS
1611 
5430 906 MT 5430 986 LS
1612 
5430 986 MT 5647 986 LS
1613 
5647 986 MT 5647 906 LS
1614 
5647 906 MT 5864 906 LS
1615 
5864 906 MT 5864 986 LS
1616 
5864 986 MT 6081 986 LS
1617 
6081 986 MT 6081 906 LS
1618 
6081 906 MT 6298 906 LS
1619 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) 3008 1129 WT TSE RSS
1620 
3254 1020 MT 3268 1020 LS
1621 
3688 1020 MT 3702 1020 LS
1622 
4122 1020 MT 4136 1020 LS
1623 
4556 1020 MT 4570 1020 LS
1624 
4989 1020 MT 5003 1020 LS
1625 
5423 1020 MT 5437 1020 LS
1626 
5857 1020 MT 5871 1020 LS
1627 
6291 1020 MT 6305 1020 LS
1628 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
1629 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
1630 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
1631 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) 3008 1273 WT TSE RSS
1632 
3254 1164 MT 3268 1164 LS
1633 
3688 1164 MT 3702 1164 LS
1634 
4122 1164 MT 4136 1164 LS
1635 
4556 1164 MT 4570 1164 LS
1636 
4989 1164 MT 5003 1164 LS
1637 
5423 1164 MT 5437 1164 LS
1638 
5857 1164 MT 5871 1164 LS
1639 
6291 1164 MT 6305 1164 LS
1640 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
1641 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
1642 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
1643 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) 3008 1417 WT TSE RSS
1644 
3254 1308 MT 3268 1308 LS
1645 
3688 1308 MT 3702 1308 LS
1646 
4122 1308 MT 4136 1308 LS
1647 
4556 1308 MT 4570 1308 LS
1648 
4989 1308 MT 5003 1308 LS
1649 
5423 1308 MT 5437 1308 LS
1650 
5857 1308 MT 5871 1308 LS
1651 
6291 1308 MT 6305 1308 LS
1652 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
1653 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
1654 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
1655 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) 3008 1561 WT TSE RSS
1656 
3254 1452 MT 3268 1452 LS
1657 
3688 1452 MT 3702 1452 LS
1658 
4122 1452 MT 4136 1452 LS
1659 
4556 1452 MT 4570 1452 LS
1660 
4989 1452 MT 5003 1452 LS
1661 
5423 1452 MT 5437 1452 LS
1662 
5857 1452 MT 5871 1452 LS
1663 
6291 1452 MT 6305 1452 LS
1664 
3045 1522 MT 6298 1522 LS
1665 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) 3008 1705 WT TSE RSS
1666 
3254 1596 MT 3268 1596 LS
1667 
3688 1596 MT 3702 1596 LS
1668 
4122 1596 MT 4136 1596 LS
1669 
4556 1596 MT 4570 1596 LS
1670 
4989 1596 MT 5003 1596 LS
1671 
5423 1596 MT 5437 1596 LS
1672 
5857 1596 MT 5871 1596 LS
1673 
6291 1596 MT 6305 1596 LS
1674 
3045 1706 MT 6298 1706 LS
1675 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) 3008 1849 WT TSE RSS
1676 
3254 1740 MT 3268 1740 LS
1677 
3688 1740 MT 3702 1740 LS
1678 
4122 1740 MT 4136 1740 LS
1679 
4556 1740 MT 4570 1740 LS
1680 
4989 1740 MT 5003 1740 LS
1681 
5423 1740 MT 5437 1740 LS
1682 
5857 1740 MT 5871 1740 LS
1683 
6291 1740 MT 6305 1740 LS
1684 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
1685 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
1686 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
1687 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) 3008 1993 WT TSE RSS
1688 
3254 1884 MT 3268 1884 LS
1689 
3688 1884 MT 3702 1884 LS
1690 
4122 1884 MT 4136 1884 LS
1691 
4556 1884 MT 4570 1884 LS
1692 
4989 1884 MT 5003 1884 LS
1693 
5423 1884 MT 5437 1884 LS
1694 
5857 1884 MT 5871 1884 LS
1695 
6291 1884 MT 6305 1884 LS
1696 
3045 1994 MT 6298 1994 LS
1697 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) 3008 2137 WT TSE RSS
1698 
3254 2028 MT 3268 2028 LS
1699 
3688 2028 MT 3702 2028 LS
1700 
4122 2028 MT 4136 2028 LS
1701 
4556 2028 MT 4570 2028 LS
1702 
4989 2028 MT 5003 2028 LS
1703 
5423 2028 MT 5437 2028 LS
1704 
5857 2028 MT 5871 2028 LS
1705 
6291 2028 MT 6305 2028 LS
1706 
3045 2058 MT 6298 2058 LS
1707 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) 3008 2281 WT TSE RSS
1708 
3254 2172 MT 3268 2172 LS
1709 
3688 2172 MT 3702 2172 LS
1710 
4122 2172 MT 4136 2172 LS
1711 
4556 2172 MT 4570 2172 LS
1712 
4989 2172 MT 5003 2172 LS
1713 
5423 2172 MT 5437 2172 LS
1714 
5857 2172 MT 5871 2172 LS
1715 
6291 2172 MT 6305 2172 LS
1716 
3045 2282 MT 6298 2282 LS
1717 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) 3008 2425 WT TSE RSS
1718 
3254 2316 MT 3268 2316 LS
1719 
3688 2316 MT 3702 2316 LS
1720 
4122 2316 MT 4136 2316 LS
1721 
4556 2316 MT 4570 2316 LS
1722 
4989 2316 MT 5003 2316 LS
1723 
5423 2316 MT 5437 2316 LS
1724 
5857 2316 MT 5871 2316 LS
1725 
6291 2316 MT 6305 2316 LS
1726 
3045 2386 MT 6298 2386 LS
1727 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) 3008 2569 WT TSE RSS
1728 
3254 2460 MT 3268 2460 LS
1729 
3688 2460 MT 3702 2460 LS
1730 
4122 2460 MT 4136 2460 LS
1731 
4556 2460 MT 4570 2460 LS
1732 
4989 2460 MT 5003 2460 LS
1733 
5423 2460 MT 5437 2460 LS
1734 
5857 2460 MT 5871 2460 LS
1735 
6291 2460 MT 6305 2460 LS
1736 
3045 2570 MT 6298 2570 LS
1737 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) 3008 2713 WT TSE RSS
1738 
3254 2604 MT 3268 2604 LS
1739 
3688 2604 MT 3702 2604 LS
1740 
4122 2604 MT 4136 2604 LS
1741 
4556 2604 MT 4570 2604 LS
1742 
4989 2604 MT 5003 2604 LS
1743 
5423 2604 MT 5437 2604 LS
1744 
5857 2604 MT 5871 2604 LS
1745 
6291 2604 MT 6305 2604 LS
1746 
3045 2714 MT 6298 2714 LS
1747 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) 3008 2857 WT TSE RSS
1748 
3254 2748 MT 3268 2748 LS
1749 
3688 2748 MT 3702 2748 LS
1750 
4122 2748 MT 4136 2748 LS
1751 
4556 2748 MT 4570 2748 LS
1752 
4989 2748 MT 5003 2748 LS
1753 
5423 2748 MT 5437 2748 LS
1754 
5857 2748 MT 5871 2748 LS
1755 
6291 2748 MT 6305 2748 LS
1756 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
1757 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
1758 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
1759 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) 3008 3001 WT TSE RSS
1760 
3254 2892 MT 3268 2892 LS
1761 
3688 2892 MT 3702 2892 LS
1762 
4122 2892 MT 4136 2892 LS
1763 
4556 2892 MT 4570 2892 LS
1764 
4989 2892 MT 5003 2892 LS
1765 
5423 2892 MT 5437 2892 LS
1766 
5857 2892 MT 5871 2892 LS
1767 
6291 2892 MT 6305 2892 LS
1768 
3045 3002 MT 6298 3002 LS
1769 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) 3008 3145 WT TSE RSS
1770 
3254 3036 MT 3268 3036 LS
1771 
3688 3036 MT 3702 3036 LS
1772 
4122 3036 MT 4136 3036 LS
1773 
4556 3036 MT 4570 3036 LS
1774 
4989 3036 MT 5003 3036 LS
1775 
5423 3036 MT 5437 3036 LS
1776 
5857 3036 MT 5871 3036 LS
1777 
6291 3036 MT 6305 3036 LS
1778 
3045 3066 MT 6298 3066 LS
1779 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) 3008 3289 WT TSE RSS
1780 
3254 3180 MT 3268 3180 LS
1781 
3688 3180 MT 3702 3180 LS
1782 
4122 3180 MT 4136 3180 LS
1783 
4556 3180 MT 4570 3180 LS
1784 
4989 3180 MT 5003 3180 LS
1785 
5423 3180 MT 5437 3180 LS
1786 
5857 3180 MT 5871 3180 LS
1787 
6291 3180 MT 6305 3180 LS
1788 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
1789 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
1790 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
1791 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) 3008 3433 WT TSE RSS
1792 
3254 3324 MT 3268 3324 LS
1793 
3688 3324 MT 3702 3324 LS
1794 
4122 3324 MT 4136 3324 LS
1795 
4556 3324 MT 4570 3324 LS
1796 
4989 3324 MT 5003 3324 LS
1797 
5423 3324 MT 5437 3324 LS
1798 
5857 3324 MT 5871 3324 LS
1799 
6291 3324 MT 6305 3324 LS
1800 
3045 3434 MT 6298 3434 LS
1801 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) 3008 3577 WT TSE RSS
1802 
3254 3468 MT 3268 3468 LS
1803 
3688 3468 MT 3702 3468 LS
1804 
4122 3468 MT 4136 3468 LS
1805 
4556 3468 MT 4570 3468 LS
1806 
4989 3468 MT 5003 3468 LS
1807 
5423 3468 MT 5437 3468 LS
1808 
5857 3468 MT 5871 3468 LS
1809 
6291 3468 MT 6305 3468 LS
1810 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
1811 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
1812 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
1813 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) 3008 3721 WT TSE RSS
1814 
3254 3612 MT 3268 3612 LS
1815 
3688 3612 MT 3702 3612 LS
1816 
4122 3612 MT 4136 3612 LS
1817 
4556 3612 MT 4570 3612 LS
1818 
4989 3612 MT 5003 3612 LS
1819 
5423 3612 MT 5437 3612 LS
1820 
5857 3612 MT 5871 3612 LS
1821 
6291 3612 MT 6305 3612 LS
1822 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
1823 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
1824 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
1825 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) 3008 3865 WT TSE RSS
1826 
3254 3756 MT 3268 3756 LS
1827 
3688 3756 MT 3702 3756 LS
1828 
4122 3756 MT 4136 3756 LS
1829 
4556 3756 MT 4570 3756 LS
1830 
4989 3756 MT 5003 3756 LS
1831 
5423 3756 MT 5437 3756 LS
1832 
5857 3756 MT 5871 3756 LS
1833 
6291 3756 MT 6305 3756 LS
1834 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
1835 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
1836 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
1837 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) 3008 4009 WT TSE RSS
1838 
3254 3900 MT 3268 3900 LS
1839 
3688 3900 MT 3702 3900 LS
1840 
4122 3900 MT 4136 3900 LS
1841 
4556 3900 MT 4570 3900 LS
1842 
4989 3900 MT 5003 3900 LS
1843 
5423 3900 MT 5437 3900 LS
1844 
5857 3900 MT 5871 3900 LS
1845 
6291 3900 MT 6305 3900 LS
1846 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
1847 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
1848 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
1849 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) 3008 4153 WT TSE RSS
1850 
3254 4044 MT 3268 4044 LS
1851 
3688 4044 MT 3702 4044 LS
1852 
4122 4044 MT 4136 4044 LS
1853 
4556 4044 MT 4570 4044 LS
1854 
4989 4044 MT 5003 4044 LS
1855 
5423 4044 MT 5437 4044 LS
1856 
5857 4044 MT 5871 4044 LS
1857 
6291 4044 MT 6305 4044 LS
1858 
3045 4154 MT 6298 4154 LS
1859 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) 3008 4297 WT TSE RSS
1860 
3254 4188 MT 3268 4188 LS
1861 
3688 4188 MT 3702 4188 LS
1862 
4122 4188 MT 4136 4188 LS
1863 
4556 4188 MT 4570 4188 LS
1864 
4989 4188 MT 5003 4188 LS
1865 
5423 4188 MT 5437 4188 LS
1866 
5857 4188 MT 5871 4188 LS
1867 
6291 4188 MT 6305 4188 LS
1868 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
1869 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
1870 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
1871 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) 3008 4441 WT TSE RSS
1872 
3254 4332 MT 3268 4332 LS
1873 
3688 4332 MT 3702 4332 LS
1874 
4122 4332 MT 4136 4332 LS
1875 
4556 4332 MT 4570 4332 LS
1876 
4989 4332 MT 5003 4332 LS
1877 
5423 4332 MT 5437 4332 LS
1878 
5857 4332 MT 5871 4332 LS
1879 
6291 4332 MT 6305 4332 LS
1880 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
1881 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
1882 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
1883 
% draw footer
1884 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 2 Page: 3) 300 4799 WT TSW RSS
1885 
grestore
1886 
showpage
1887 
%%Page: 4 4
1888 
gsave
1889 
90 rotate 0.12 dup neg scale
1890 
% dump string table
1891 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
1892 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
1893 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
1894 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
1895 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
1896 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
1897 
/ARC {5 -2 roll SX 5 2 roll arc} def
1898 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
1899 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
1900 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
1901 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
1902 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
1903 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
1904 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
1905 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
1906 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
1907 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
1908 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
1909 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
1910 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
1911 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
1912 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
1913 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
1914 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
1915 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
1916 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
1917 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
1918 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
1919 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
1920 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
1921 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
1922 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
1923 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
1924 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
1925 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
1926 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
1927 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
1928 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
1929 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
1930 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
1931 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
1932 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
1933 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
1934 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
1935 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
1936 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
1937 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
1938 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
1939 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
1940 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
1941 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
1942 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
1943 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
1944 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
1945 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
1946 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
1947 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
1948 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
1949 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
1950 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
1951 
% draw waveform shading
1952 
[] 0 SD
1953 
2.995 setlinewidth
1954 
 
1955 
 
1956 
 
1957 
3045 329 MT 3045 329 LT 6298 329 LT ST
1958 
3045 410 MT 3045 410 LT 6298 410 LT ST
1959 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
1960 
3045 473 MT 3045 473 LT 6298 473 LT ST
1961 
3045 554 MT 3045 554 LT 6298 554 LT ST
1962 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
1963 
3045 698 MT 6298 698 LS
1964 
3045 842 MT 6298 842 LS
1965 
3045 986 MT 6298 986 LS
1966 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
1967 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
1968 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
1969 
3045 1274 MT 6298 1274 LS
1970 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
1971 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
1972 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
1973 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
1974 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
1975 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
1976 
3045 1706 MT 6298 1706 LS
1977 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
1978 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
1979 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
1980 
3045 1994 MT 6298 1994 LS
1981 
3045 2098 MT 6298 2098 LS
1982 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
1983 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
1984 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
1985 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
1986 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
1987 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
1988 
3045 2489 MT 3045 2489 LT 3471 2489 LT 3478 2530 LT ST
1989 
3045 2570 MT 3045 2570 LT 3471 2570 LT 3478 2530 LT ST
1990 
(5) 3059 2530 WT pop 0 originOffset 37 add RSS
1991 
3478 2530 MT 3478 2530 LT 3485 2489 LT 3905 2489 LT 3912 2530 LT ST
1992 
3478 2530 MT 3478 2530 LT 3485 2570 LT 3905 2570 LT 3912 2530 LT ST
1993 
(6) 3492 2530 WT pop 0 originOffset 37 add RSS
1994 
3912 2530 MT 3912 2530 LT 3919 2489 LT 4339 2489 LT 4346 2530 LT ST
1995 
3912 2530 MT 3912 2530 LT 3919 2570 LT 4339 2570 LT 4346 2530 LT ST
1996 
(7) 3926 2530 WT pop 0 originOffset 37 add RSS
1997 
4346 2530 MT 4346 2530 LT 4353 2489 LT 4772 2489 LT 4779 2530 LT ST
1998 
4346 2530 MT 4346 2530 LT 4353 2570 LT 4772 2570 LT 4779 2530 LT ST
1999 
(0) 4360 2530 WT pop 0 originOffset 37 add RSS
2000 
4779 2530 MT 4779 2530 LT 4786 2489 LT 5206 2489 LT 5213 2530 LT ST
2001 
4779 2530 MT 4779 2530 LT 4786 2570 LT 5206 2570 LT 5213 2530 LT ST
2002 
(1) 4793 2530 WT pop 0 originOffset 37 add RSS
2003 
5213 2530 MT 5213 2530 LT 5220 2489 LT 5640 2489 LT 5647 2530 LT ST
2004 
5213 2530 MT 5213 2530 LT 5220 2570 LT 5640 2570 LT 5647 2530 LT ST
2005 
(2) 5227 2530 WT pop 0 originOffset 37 add RSS
2006 
5647 2530 MT 5647 2530 LT 5654 2489 LT 6074 2489 LT 6081 2530 LT ST
2007 
5647 2530 MT 5647 2530 LT 5654 2570 LT 6074 2570 LT 6081 2530 LT ST
2008 
(3) 5661 2530 WT pop 0 originOffset 37 add RSS
2009 
6081 2530 MT 6081 2530 LT 6088 2489 LT 6298 2489 LT ST
2010 
6081 2530 MT 6081 2530 LT 6088 2570 LT 6298 2570 LT ST
2011 
(4) 6095 2530 WT pop 0 originOffset 37 add RSS
2012 
3045 2633 MT 3045 2633 LT 3471 2633 LT 3478 2674 LT ST
2013 
3045 2714 MT 3045 2714 LT 3471 2714 LT 3478 2674 LT ST
2014 
(4) 3059 2674 WT pop 0 originOffset 37 add RSS
2015 
3478 2674 MT 3478 2674 LT 3485 2633 LT 3905 2633 LT 3912 2674 LT ST
2016 
3478 2674 MT 3478 2674 LT 3485 2714 LT 3905 2714 LT 3912 2674 LT ST
2017 
(5) 3492 2674 WT pop 0 originOffset 37 add RSS
2018 
3912 2674 MT 3912 2674 LT 3919 2633 LT 4339 2633 LT 4346 2674 LT ST
2019 
3912 2674 MT 3912 2674 LT 3919 2714 LT 4339 2714 LT 4346 2674 LT ST
2020 
(6) 3926 2674 WT pop 0 originOffset 37 add RSS
2021 
4346 2674 MT 4346 2674 LT 4353 2633 LT 4772 2633 LT 4779 2674 LT ST
2022 
4346 2674 MT 4346 2674 LT 4353 2714 LT 4772 2714 LT 4779 2674 LT ST
2023 
(7) 4360 2674 WT pop 0 originOffset 37 add RSS
2024 
4779 2674 MT 4779 2674 LT 4786 2633 LT 5206 2633 LT 5213 2674 LT ST
2025 
4779 2674 MT 4779 2674 LT 4786 2714 LT 5206 2714 LT 5213 2674 LT ST
2026 
(0) 4793 2674 WT pop 0 originOffset 37 add RSS
2027 
5213 2674 MT 5213 2674 LT 5220 2633 LT 5640 2633 LT 5647 2674 LT ST
2028 
5213 2674 MT 5213 2674 LT 5220 2714 LT 5640 2714 LT 5647 2674 LT ST
2029 
(1) 5227 2674 WT pop 0 originOffset 37 add RSS
2030 
5647 2674 MT 5647 2674 LT 5654 2633 LT 6074 2633 LT 6081 2674 LT ST
2031 
5647 2674 MT 5647 2674 LT 5654 2714 LT 6074 2714 LT 6081 2674 LT ST
2032 
(2) 5661 2674 WT pop 0 originOffset 37 add RSS
2033 
6081 2674 MT 6081 2674 LT 6088 2633 LT 6298 2633 LT ST
2034 
6081 2674 MT 6081 2674 LT 6088 2714 LT 6298 2714 LT ST
2035 
(3) 6095 2674 WT pop 0 originOffset 37 add RSS
2036 
3045 2858 MT 6298 2858 LS
2037 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
2038 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
2039 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
2040 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
2041 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
2042 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
2043 
3045 3290 MT 6298 3290 LS
2044 
% draw timeline
2045 
3088 4533 MT 3088 4570 LS
2046 
3132 4533 MT 3132 4570 LS
2047 
3175 4533 MT 3175 4570 LS
2048 
3218 4533 MT 3218 4570 LS
2049 
3304 4533 MT 3304 4570 LS
2050 
3348 4533 MT 3348 4570 LS
2051 
3391 4533 MT 3391 4570 LS
2052 
3434 4533 MT 3434 4570 LS
2053 
3478 4533 MT 3478 4570 LS
2054 
3521 4533 MT 3521 4570 LS
2055 
3565 4533 MT 3565 4570 LS
2056 
3608 4533 MT 3608 4570 LS
2057 
3651 4533 MT 3651 4570 LS
2058 
3261 4506 MT 3261 4570 LS
2059 
(80) 3261 4649 WT TS RSS
2060 
3738 4533 MT 3738 4570 LS
2061 
3782 4533 MT 3782 4570 LS
2062 
3825 4533 MT 3825 4570 LS
2063 
3868 4533 MT 3868 4570 LS
2064 
3912 4533 MT 3912 4570 LS
2065 
3955 4533 MT 3955 4570 LS
2066 
3999 4533 MT 3999 4570 LS
2067 
4042 4533 MT 4042 4570 LS
2068 
4085 4533 MT 4085 4570 LS
2069 
3695 4506 MT 3695 4570 LS
2070 
4172 4533 MT 4172 4570 LS
2071 
4216 4533 MT 4216 4570 LS
2072 
4259 4533 MT 4259 4570 LS
2073 
4302 4533 MT 4302 4570 LS
2074 
4346 4533 MT 4346 4570 LS
2075 
4389 4533 MT 4389 4570 LS
2076 
4433 4533 MT 4433 4570 LS
2077 
4476 4533 MT 4476 4570 LS
2078 
4519 4533 MT 4519 4570 LS
2079 
4129 4506 MT 4129 4570 LS
2080 
(100) 4129 4649 WT TS RSS
2081 
4606 4533 MT 4606 4570 LS
2082 
4650 4533 MT 4650 4570 LS
2083 
4693 4533 MT 4693 4570 LS
2084 
4736 4533 MT 4736 4570 LS
2085 
4780 4533 MT 4780 4570 LS
2086 
4823 4533 MT 4823 4570 LS
2087 
4867 4533 MT 4867 4570 LS
2088 
4910 4533 MT 4910 4570 LS
2089 
4953 4533 MT 4953 4570 LS
2090 
4563 4506 MT 4563 4570 LS
2091 
5039 4533 MT 5039 4570 LS
2092 
5083 4533 MT 5083 4570 LS
2093 
5126 4533 MT 5126 4570 LS
2094 
5169 4533 MT 5169 4570 LS
2095 
5213 4533 MT 5213 4570 LS
2096 
5256 4533 MT 5256 4570 LS
2097 
5300 4533 MT 5300 4570 LS
2098 
5343 4533 MT 5343 4570 LS
2099 
5386 4533 MT 5386 4570 LS
2100 
4996 4506 MT 4996 4570 LS
2101 
(120) 4996 4649 WT TS RSS
2102 
5473 4533 MT 5473 4570 LS
2103 
5517 4533 MT 5517 4570 LS
2104 
5560 4533 MT 5560 4570 LS
2105 
5603 4533 MT 5603 4570 LS
2106 
5647 4533 MT 5647 4570 LS
2107 
5690 4533 MT 5690 4570 LS
2108 
5734 4533 MT 5734 4570 LS
2109 
5777 4533 MT 5777 4570 LS
2110 
5820 4533 MT 5820 4570 LS
2111 
5430 4506 MT 5430 4570 LS
2112 
5907 4533 MT 5907 4570 LS
2113 
5951 4533 MT 5951 4570 LS
2114 
5994 4533 MT 5994 4570 LS
2115 
6037 4533 MT 6037 4570 LS
2116 
6081 4533 MT 6081 4570 LS
2117 
6124 4533 MT 6124 4570 LS
2118 
6168 4533 MT 6168 4570 LS
2119 
6211 4533 MT 6211 4570 LS
2120 
6254 4533 MT 6254 4570 LS
2121 
5864 4506 MT 5864 4570 LS
2122 
(140) 5864 4649 WT TS RSS
2123 
6341 4533 MT 6341 4570 LS
2124 
6385 4533 MT 6385 4570 LS
2125 
6428 4533 MT 6428 4570 LS
2126 
6471 4533 MT 6471 4570 LS
2127 
6515 4533 MT 6515 4570 LS
2128 
6558 4533 MT 6558 4570 LS
2129 
6602 4533 MT 6602 4570 LS
2130 
6645 4533 MT 6645 4570 LS
2131 
6688 4533 MT 6688 4570 LS
2132 
6298 4506 MT 6298 4570 LS
2133 
% draw grid
2134 
3261 300 MT 3261 4506 LS
2135 
3695 300 MT 3695 4506 LS
2136 
4129 300 MT 4129 4506 LS
2137 
4563 300 MT 4563 4506 LS
2138 
4996 300 MT 4996 4506 LS
2139 
5430 300 MT 5430 4506 LS
2140 
5864 300 MT 5864 4506 LS
2141 
6298 300 MT 6298 4506 LS
2142 
% draw waveforms
2143 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) 3008 409 WT TSE RSS
2144 
3254 300 MT 3268 300 LS
2145 
3688 300 MT 3702 300 LS
2146 
4122 300 MT 4136 300 LS
2147 
4556 300 MT 4570 300 LS
2148 
4989 300 MT 5003 300 LS
2149 
5423 300 MT 5437 300 LS
2150 
5857 300 MT 5871 300 LS
2151 
6291 300 MT 6305 300 LS
2152 
3045 329 MT 3045 329 LT 6298 329 LT ST
2153 
3045 410 MT 3045 410 LT 6298 410 LT ST
2154 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
2155 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) 3008 553 WT TSE RSS
2156 
3254 444 MT 3268 444 LS
2157 
3688 444 MT 3702 444 LS
2158 
4122 444 MT 4136 444 LS
2159 
4556 444 MT 4570 444 LS
2160 
4989 444 MT 5003 444 LS
2161 
5423 444 MT 5437 444 LS
2162 
5857 444 MT 5871 444 LS
2163 
6291 444 MT 6305 444 LS
2164 
3045 473 MT 3045 473 LT 6298 473 LT ST
2165 
3045 554 MT 3045 554 LT 6298 554 LT ST
2166 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
2167 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) 3008 697 WT TSE RSS
2168 
3254 588 MT 3268 588 LS
2169 
3688 588 MT 3702 588 LS
2170 
4122 588 MT 4136 588 LS
2171 
4556 588 MT 4570 588 LS
2172 
4989 588 MT 5003 588 LS
2173 
5423 588 MT 5437 588 LS
2174 
5857 588 MT 5871 588 LS
2175 
6291 588 MT 6305 588 LS
2176 
3045 698 MT 6298 698 LS
2177 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) 3008 841 WT TSE RSS
2178 
3254 732 MT 3268 732 LS
2179 
3688 732 MT 3702 732 LS
2180 
4122 732 MT 4136 732 LS
2181 
4556 732 MT 4570 732 LS
2182 
4989 732 MT 5003 732 LS
2183 
5423 732 MT 5437 732 LS
2184 
5857 732 MT 5871 732 LS
2185 
6291 732 MT 6305 732 LS
2186 
3045 842 MT 6298 842 LS
2187 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) 3008 985 WT TSE RSS
2188 
3254 876 MT 3268 876 LS
2189 
3688 876 MT 3702 876 LS
2190 
4122 876 MT 4136 876 LS
2191 
4556 876 MT 4570 876 LS
2192 
4989 876 MT 5003 876 LS
2193 
5423 876 MT 5437 876 LS
2194 
5857 876 MT 5871 876 LS
2195 
6291 876 MT 6305 876 LS
2196 
3045 986 MT 6298 986 LS
2197 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) 3008 1129 WT TSE RSS
2198 
3254 1020 MT 3268 1020 LS
2199 
3688 1020 MT 3702 1020 LS
2200 
4122 1020 MT 4136 1020 LS
2201 
4556 1020 MT 4570 1020 LS
2202 
4989 1020 MT 5003 1020 LS
2203 
5423 1020 MT 5437 1020 LS
2204 
5857 1020 MT 5871 1020 LS
2205 
6291 1020 MT 6305 1020 LS
2206 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
2207 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
2208 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
2209 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) 3008 1273 WT TSE RSS
2210 
3254 1164 MT 3268 1164 LS
2211 
3688 1164 MT 3702 1164 LS
2212 
4122 1164 MT 4136 1164 LS
2213 
4556 1164 MT 4570 1164 LS
2214 
4989 1164 MT 5003 1164 LS
2215 
5423 1164 MT 5437 1164 LS
2216 
5857 1164 MT 5871 1164 LS
2217 
6291 1164 MT 6305 1164 LS
2218 
3045 1274 MT 6298 1274 LS
2219 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) 3008 1417 WT TSE RSS
2220 
3254 1308 MT 3268 1308 LS
2221 
3688 1308 MT 3702 1308 LS
2222 
4122 1308 MT 4136 1308 LS
2223 
4556 1308 MT 4570 1308 LS
2224 
4989 1308 MT 5003 1308 LS
2225 
5423 1308 MT 5437 1308 LS
2226 
5857 1308 MT 5871 1308 LS
2227 
6291 1308 MT 6305 1308 LS
2228 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
2229 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
2230 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
2231 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) 3008 1561 WT TSE RSS
2232 
3254 1452 MT 3268 1452 LS
2233 
3688 1452 MT 3702 1452 LS
2234 
4122 1452 MT 4136 1452 LS
2235 
4556 1452 MT 4570 1452 LS
2236 
4989 1452 MT 5003 1452 LS
2237 
5423 1452 MT 5437 1452 LS
2238 
5857 1452 MT 5871 1452 LS
2239 
6291 1452 MT 6305 1452 LS
2240 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
2241 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
2242 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
2243 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) 3008 1705 WT TSE RSS
2244 
3254 1596 MT 3268 1596 LS
2245 
3688 1596 MT 3702 1596 LS
2246 
4122 1596 MT 4136 1596 LS
2247 
4556 1596 MT 4570 1596 LS
2248 
4989 1596 MT 5003 1596 LS
2249 
5423 1596 MT 5437 1596 LS
2250 
5857 1596 MT 5871 1596 LS
2251 
6291 1596 MT 6305 1596 LS
2252 
3045 1706 MT 6298 1706 LS
2253 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) 3008 1849 WT TSE RSS
2254 
3254 1740 MT 3268 1740 LS
2255 
3688 1740 MT 3702 1740 LS
2256 
4122 1740 MT 4136 1740 LS
2257 
4556 1740 MT 4570 1740 LS
2258 
4989 1740 MT 5003 1740 LS
2259 
5423 1740 MT 5437 1740 LS
2260 
5857 1740 MT 5871 1740 LS
2261 
6291 1740 MT 6305 1740 LS
2262 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
2263 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
2264 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
2265 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) 3008 1993 WT TSE RSS
2266 
3254 1884 MT 3268 1884 LS
2267 
3688 1884 MT 3702 1884 LS
2268 
4122 1884 MT 4136 1884 LS
2269 
4556 1884 MT 4570 1884 LS
2270 
4989 1884 MT 5003 1884 LS
2271 
5423 1884 MT 5437 1884 LS
2272 
5857 1884 MT 5871 1884 LS
2273 
6291 1884 MT 6305 1884 LS
2274 
3045 1994 MT 6298 1994 LS
2275 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) 3008 2137 WT TSE RSS
2276 
3254 2028 MT 3268 2028 LS
2277 
3688 2028 MT 3702 2028 LS
2278 
4122 2028 MT 4136 2028 LS
2279 
4556 2028 MT 4570 2028 LS
2280 
4989 2028 MT 5003 2028 LS
2281 
5423 2028 MT 5437 2028 LS
2282 
5857 2028 MT 5871 2028 LS
2283 
6291 2028 MT 6305 2028 LS
2284 
3045 2098 MT 6298 2098 LS
2285 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) 3008 2281 WT TSE RSS
2286 
3254 2172 MT 3268 2172 LS
2287 
3688 2172 MT 3702 2172 LS
2288 
4122 2172 MT 4136 2172 LS
2289 
4556 2172 MT 4570 2172 LS
2290 
4989 2172 MT 5003 2172 LS
2291 
5423 2172 MT 5437 2172 LS
2292 
5857 2172 MT 5871 2172 LS
2293 
6291 2172 MT 6305 2172 LS
2294 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
2295 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
2296 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
2297 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) 3008 2425 WT TSE RSS
2298 
3254 2316 MT 3268 2316 LS
2299 
3688 2316 MT 3702 2316 LS
2300 
4122 2316 MT 4136 2316 LS
2301 
4556 2316 MT 4570 2316 LS
2302 
4989 2316 MT 5003 2316 LS
2303 
5423 2316 MT 5437 2316 LS
2304 
5857 2316 MT 5871 2316 LS
2305 
6291 2316 MT 6305 2316 LS
2306 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
2307 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
2308 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
2309 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) 3008 2569 WT TSE RSS
2310 
3254 2460 MT 3268 2460 LS
2311 
3688 2460 MT 3702 2460 LS
2312 
4122 2460 MT 4136 2460 LS
2313 
4556 2460 MT 4570 2460 LS
2314 
4989 2460 MT 5003 2460 LS
2315 
5423 2460 MT 5437 2460 LS
2316 
5857 2460 MT 5871 2460 LS
2317 
6291 2460 MT 6305 2460 LS
2318 
3045 2489 MT 3045 2489 LT 3471 2489 LT 3478 2530 LT ST
2319 
3045 2570 MT 3045 2570 LT 3471 2570 LT 3478 2530 LT ST
2320 
(5) 3059 2530 WT pop 0 originOffset 37 add RSS
2321 
3478 2530 MT 3478 2530 LT 3485 2489 LT 3905 2489 LT 3912 2530 LT ST
2322 
3478 2530 MT 3478 2530 LT 3485 2570 LT 3905 2570 LT 3912 2530 LT ST
2323 
(6) 3492 2530 WT pop 0 originOffset 37 add RSS
2324 
3912 2530 MT 3912 2530 LT 3919 2489 LT 4339 2489 LT 4346 2530 LT ST
2325 
3912 2530 MT 3912 2530 LT 3919 2570 LT 4339 2570 LT 4346 2530 LT ST
2326 
(7) 3926 2530 WT pop 0 originOffset 37 add RSS
2327 
4346 2530 MT 4346 2530 LT 4353 2489 LT 4772 2489 LT 4779 2530 LT ST
2328 
4346 2530 MT 4346 2530 LT 4353 2570 LT 4772 2570 LT 4779 2530 LT ST
2329 
(0) 4360 2530 WT pop 0 originOffset 37 add RSS
2330 
4779 2530 MT 4779 2530 LT 4786 2489 LT 5206 2489 LT 5213 2530 LT ST
2331 
4779 2530 MT 4779 2530 LT 4786 2570 LT 5206 2570 LT 5213 2530 LT ST
2332 
(1) 4793 2530 WT pop 0 originOffset 37 add RSS
2333 
5213 2530 MT 5213 2530 LT 5220 2489 LT 5640 2489 LT 5647 2530 LT ST
2334 
5213 2530 MT 5213 2530 LT 5220 2570 LT 5640 2570 LT 5647 2530 LT ST
2335 
(2) 5227 2530 WT pop 0 originOffset 37 add RSS
2336 
5647 2530 MT 5647 2530 LT 5654 2489 LT 6074 2489 LT 6081 2530 LT ST
2337 
5647 2530 MT 5647 2530 LT 5654 2570 LT 6074 2570 LT 6081 2530 LT ST
2338 
(3) 5661 2530 WT pop 0 originOffset 37 add RSS
2339 
6081 2530 MT 6081 2530 LT 6088 2489 LT 6298 2489 LT ST
2340 
6081 2530 MT 6081 2530 LT 6088 2570 LT 6298 2570 LT ST
2341 
(4) 6095 2530 WT pop 0 originOffset 37 add RSS
2342 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) 3008 2713 WT TSE RSS
2343 
3254 2604 MT 3268 2604 LS
2344 
3688 2604 MT 3702 2604 LS
2345 
4122 2604 MT 4136 2604 LS
2346 
4556 2604 MT 4570 2604 LS
2347 
4989 2604 MT 5003 2604 LS
2348 
5423 2604 MT 5437 2604 LS
2349 
5857 2604 MT 5871 2604 LS
2350 
6291 2604 MT 6305 2604 LS
2351 
3045 2633 MT 3045 2633 LT 3471 2633 LT 3478 2674 LT ST
2352 
3045 2714 MT 3045 2714 LT 3471 2714 LT 3478 2674 LT ST
2353 
(4) 3059 2674 WT pop 0 originOffset 37 add RSS
2354 
3478 2674 MT 3478 2674 LT 3485 2633 LT 3905 2633 LT 3912 2674 LT ST
2355 
3478 2674 MT 3478 2674 LT 3485 2714 LT 3905 2714 LT 3912 2674 LT ST
2356 
(5) 3492 2674 WT pop 0 originOffset 37 add RSS
2357 
3912 2674 MT 3912 2674 LT 3919 2633 LT 4339 2633 LT 4346 2674 LT ST
2358 
3912 2674 MT 3912 2674 LT 3919 2714 LT 4339 2714 LT 4346 2674 LT ST
2359 
(6) 3926 2674 WT pop 0 originOffset 37 add RSS
2360 
4346 2674 MT 4346 2674 LT 4353 2633 LT 4772 2633 LT 4779 2674 LT ST
2361 
4346 2674 MT 4346 2674 LT 4353 2714 LT 4772 2714 LT 4779 2674 LT ST
2362 
(7) 4360 2674 WT pop 0 originOffset 37 add RSS
2363 
4779 2674 MT 4779 2674 LT 4786 2633 LT 5206 2633 LT 5213 2674 LT ST
2364 
4779 2674 MT 4779 2674 LT 4786 2714 LT 5206 2714 LT 5213 2674 LT ST
2365 
(0) 4793 2674 WT pop 0 originOffset 37 add RSS
2366 
5213 2674 MT 5213 2674 LT 5220 2633 LT 5640 2633 LT 5647 2674 LT ST
2367 
5213 2674 MT 5213 2674 LT 5220 2714 LT 5640 2714 LT 5647 2674 LT ST
2368 
(1) 5227 2674 WT pop 0 originOffset 37 add RSS
2369 
5647 2674 MT 5647 2674 LT 5654 2633 LT 6074 2633 LT 6081 2674 LT ST
2370 
5647 2674 MT 5647 2674 LT 5654 2714 LT 6074 2714 LT 6081 2674 LT ST
2371 
(2) 5661 2674 WT pop 0 originOffset 37 add RSS
2372 
6081 2674 MT 6081 2674 LT 6088 2633 LT 6298 2633 LT ST
2373 
6081 2674 MT 6081 2674 LT 6088 2714 LT 6298 2714 LT ST
2374 
(3) 6095 2674 WT pop 0 originOffset 37 add RSS
2375 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) 3008 2857 WT TSE RSS
2376 
3254 2748 MT 3268 2748 LS
2377 
3688 2748 MT 3702 2748 LS
2378 
4122 2748 MT 4136 2748 LS
2379 
4556 2748 MT 4570 2748 LS
2380 
4989 2748 MT 5003 2748 LS
2381 
5423 2748 MT 5437 2748 LS
2382 
5857 2748 MT 5871 2748 LS
2383 
6291 2748 MT 6305 2748 LS
2384 
3045 2858 MT 6298 2858 LS
2385 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) 3008 3001 WT TSE RSS
2386 
3254 2892 MT 3268 2892 LS
2387 
3688 2892 MT 3702 2892 LS
2388 
4122 2892 MT 4136 2892 LS
2389 
4556 2892 MT 4570 2892 LS
2390 
4989 2892 MT 5003 2892 LS
2391 
5423 2892 MT 5437 2892 LS
2392 
5857 2892 MT 5871 2892 LS
2393 
6291 2892 MT 6305 2892 LS
2394 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
2395 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
2396 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
2397 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) 3008 3145 WT TSE RSS
2398 
3254 3036 MT 3268 3036 LS
2399 
3688 3036 MT 3702 3036 LS
2400 
4122 3036 MT 4136 3036 LS
2401 
4556 3036 MT 4570 3036 LS
2402 
4989 3036 MT 5003 3036 LS
2403 
5423 3036 MT 5437 3036 LS
2404 
5857 3036 MT 5871 3036 LS
2405 
6291 3036 MT 6305 3036 LS
2406 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
2407 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
2408 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
2409 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) 3008 3289 WT TSE RSS
2410 
3254 3180 MT 3268 3180 LS
2411 
3688 3180 MT 3702 3180 LS
2412 
4122 3180 MT 4136 3180 LS
2413 
4556 3180 MT 4570 3180 LS
2414 
4989 3180 MT 5003 3180 LS
2415 
5423 3180 MT 5437 3180 LS
2416 
5857 3180 MT 5871 3180 LS
2417 
6291 3180 MT 6305 3180 LS
2418 
3045 3290 MT 6298 3290 LS
2419 
% draw footer
2420 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 2 Page: 4) 300 4799 WT TSW RSS
2421 
grestore
2422 
showpage
2423 
%%Page: 5 5
2424 
gsave
2425 
90 rotate 0.12 dup neg scale
2426 
% dump string table
2427 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
2428 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
2429 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
2430 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
2431 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
2432 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
2433 
/ARC {5 -2 roll SX 5 2 roll arc} def
2434 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
2435 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
2436 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
2437 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
2438 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
2439 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
2440 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
2441 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
2442 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
2443 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
2444 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
2445 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
2446 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
2447 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
2448 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
2449 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
2450 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
2451 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
2452 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
2453 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
2454 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
2455 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
2456 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
2457 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
2458 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
2459 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
2460 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
2461 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
2462 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
2463 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
2464 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
2465 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
2466 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
2467 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
2468 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
2469 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
2470 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
2471 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
2472 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
2473 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
2474 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
2475 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
2476 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
2477 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
2478 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
2479 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
2480 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
2481 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
2482 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
2483 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
2484 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
2485 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
2486 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
2487 
% draw waveform shading
2488 
[] 0 SD
2489 
2.995 setlinewidth
2490 
 
2491 
 
2492 
 
2493 
3045 329 MT 3045 329 LT 6298 329 LT ST
2494 
3045 410 MT 3045 410 LT 6298 410 LT ST
2495 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
2496 
3045 473 MT 3045 473 LT 6298 473 LT ST
2497 
3045 554 MT 3045 554 LT 6298 554 LT ST
2498 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
2499 
3045 617 MT 3045 617 LT 6298 617 LT ST
2500 
3045 698 MT 3045 698 LT 6298 698 LT ST
2501 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
2502 
3045 842 MT 6298 842 LS
2503 
3045 906 MT 3045 986 LS
2504 
3045 986 MT 3261 986 LS
2505 
3261 986 MT 3261 906 LS
2506 
3261 906 MT 3478 906 LS
2507 
3478 906 MT 3478 986 LS
2508 
3478 986 MT 3695 986 LS
2509 
3695 986 MT 3695 906 LS
2510 
3695 906 MT 3912 906 LS
2511 
3912 906 MT 3912 986 LS
2512 
3912 986 MT 4129 986 LS
2513 
4129 986 MT 4129 906 LS
2514 
4129 906 MT 4346 906 LS
2515 
4346 906 MT 4346 986 LS
2516 
4346 986 MT 4563 986 LS
2517 
4563 986 MT 4563 906 LS
2518 
4563 906 MT 4779 906 LS
2519 
4779 906 MT 4779 986 LS
2520 
4779 986 MT 4996 986 LS
2521 
4996 986 MT 4996 906 LS
2522 
4996 906 MT 5213 906 LS
2523 
5213 906 MT 5213 986 LS
2524 
5213 986 MT 5430 986 LS
2525 
5430 986 MT 5430 906 LS
2526 
5430 906 MT 5647 906 LS
2527 
5647 906 MT 5647 986 LS
2528 
5647 986 MT 5864 986 LS
2529 
5864 986 MT 5864 906 LS
2530 
5864 906 MT 6081 906 LS
2531 
6081 906 MT 6081 986 LS
2532 
6081 986 MT 6298 986 LS
2533 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
2534 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
2535 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
2536 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
2537 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
2538 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
2539 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
2540 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
2541 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
2542 
3045 1522 MT 6298 1522 LS
2543 
3045 1706 MT 6298 1706 LS
2544 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
2545 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
2546 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
2547 
3045 1994 MT 6298 1994 LS
2548 
3045 2058 MT 6298 2058 LS
2549 
3045 2282 MT 6298 2282 LS
2550 
3045 2386 MT 6298 2386 LS
2551 
3045 2570 MT 6298 2570 LS
2552 
3045 2714 MT 6298 2714 LS
2553 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
2554 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
2555 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
2556 
3045 3002 MT 6298 3002 LS
2557 
3045 3066 MT 6298 3066 LS
2558 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
2559 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
2560 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
2561 
3045 3434 MT 6298 3434 LS
2562 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
2563 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
2564 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
2565 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
2566 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
2567 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
2568 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
2569 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
2570 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
2571 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
2572 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
2573 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
2574 
3045 4154 MT 6298 4154 LS
2575 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
2576 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
2577 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
2578 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
2579 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
2580 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
2581 
% draw timeline
2582 
3088 4533 MT 3088 4570 LS
2583 
3132 4533 MT 3132 4570 LS
2584 
3175 4533 MT 3175 4570 LS
2585 
3218 4533 MT 3218 4570 LS
2586 
3262 4533 MT 3262 4570 LS
2587 
3305 4533 MT 3305 4570 LS
2588 
3349 4533 MT 3349 4570 LS
2589 
3392 4533 MT 3392 4570 LS
2590 
3435 4533 MT 3435 4570 LS
2591 
3521 4533 MT 3521 4570 LS
2592 
3565 4533 MT 3565 4570 LS
2593 
3608 4533 MT 3608 4570 LS
2594 
3651 4533 MT 3651 4570 LS
2595 
3695 4533 MT 3695 4570 LS
2596 
3738 4533 MT 3738 4570 LS
2597 
3782 4533 MT 3782 4570 LS
2598 
3825 4533 MT 3825 4570 LS
2599 
3868 4533 MT 3868 4570 LS
2600 
3478 4506 MT 3478 4570 LS
2601 
(160) 3478 4649 WT TS RSS
2602 
3955 4533 MT 3955 4570 LS
2603 
3999 4533 MT 3999 4570 LS
2604 
4042 4533 MT 4042 4570 LS
2605 
4085 4533 MT 4085 4570 LS
2606 
4129 4533 MT 4129 4570 LS
2607 
4172 4533 MT 4172 4570 LS
2608 
4216 4533 MT 4216 4570 LS
2609 
4259 4533 MT 4259 4570 LS
2610 
4302 4533 MT 4302 4570 LS
2611 
3912 4506 MT 3912 4570 LS
2612 
4389 4533 MT 4389 4570 LS
2613 
4433 4533 MT 4433 4570 LS
2614 
4476 4533 MT 4476 4570 LS
2615 
4519 4533 MT 4519 4570 LS
2616 
4563 4533 MT 4563 4570 LS
2617 
4606 4533 MT 4606 4570 LS
2618 
4650 4533 MT 4650 4570 LS
2619 
4693 4533 MT 4693 4570 LS
2620 
4736 4533 MT 4736 4570 LS
2621 
4346 4506 MT 4346 4570 LS
2622 
(180) 4346 4649 WT TS RSS
2623 
4822 4533 MT 4822 4570 LS
2624 
4866 4533 MT 4866 4570 LS
2625 
4909 4533 MT 4909 4570 LS
2626 
4952 4533 MT 4952 4570 LS
2627 
4996 4533 MT 4996 4570 LS
2628 
5039 4533 MT 5039 4570 LS
2629 
5083 4533 MT 5083 4570 LS
2630 
5126 4533 MT 5126 4570 LS
2631 
5169 4533 MT 5169 4570 LS
2632 
4779 4506 MT 4779 4570 LS
2633 
5256 4533 MT 5256 4570 LS
2634 
5300 4533 MT 5300 4570 LS
2635 
5343 4533 MT 5343 4570 LS
2636 
5386 4533 MT 5386 4570 LS
2637 
5430 4533 MT 5430 4570 LS
2638 
5473 4533 MT 5473 4570 LS
2639 
5517 4533 MT 5517 4570 LS
2640 
5560 4533 MT 5560 4570 LS
2641 
5603 4533 MT 5603 4570 LS
2642 
5213 4506 MT 5213 4570 LS
2643 
(200) 5213 4649 WT TS RSS
2644 
5690 4533 MT 5690 4570 LS
2645 
5734 4533 MT 5734 4570 LS
2646 
5777 4533 MT 5777 4570 LS
2647 
5820 4533 MT 5820 4570 LS
2648 
5864 4533 MT 5864 4570 LS
2649 
5907 4533 MT 5907 4570 LS
2650 
5951 4533 MT 5951 4570 LS
2651 
5994 4533 MT 5994 4570 LS
2652 
6037 4533 MT 6037 4570 LS
2653 
5647 4506 MT 5647 4570 LS
2654 
6124 4533 MT 6124 4570 LS
2655 
6168 4533 MT 6168 4570 LS
2656 
6211 4533 MT 6211 4570 LS
2657 
6254 4533 MT 6254 4570 LS
2658 
6298 4533 MT 6298 4570 LS
2659 
6341 4533 MT 6341 4570 LS
2660 
6385 4533 MT 6385 4570 LS
2661 
6428 4533 MT 6428 4570 LS
2662 
6471 4533 MT 6471 4570 LS
2663 
6081 4506 MT 6081 4570 LS
2664 
(220) 6081 4649 WT TS RSS
2665 
% draw grid
2666 
3478 300 MT 3478 4506 LS
2667 
3912 300 MT 3912 4506 LS
2668 
4346 300 MT 4346 4506 LS
2669 
4779 300 MT 4779 4506 LS
2670 
5213 300 MT 5213 4506 LS
2671 
5647 300 MT 5647 4506 LS
2672 
6081 300 MT 6081 4506 LS
2673 
% draw waveforms
2674 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) 3008 409 WT TSE RSS
2675 
3471 300 MT 3485 300 LS
2676 
3905 300 MT 3919 300 LS
2677 
4339 300 MT 4353 300 LS
2678 
4772 300 MT 4786 300 LS
2679 
5206 300 MT 5220 300 LS
2680 
5640 300 MT 5654 300 LS
2681 
6074 300 MT 6088 300 LS
2682 
3045 329 MT 3045 329 LT 6298 329 LT ST
2683 
3045 410 MT 3045 410 LT 6298 410 LT ST
2684 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
2685 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) 3008 553 WT TSE RSS
2686 
3471 444 MT 3485 444 LS
2687 
3905 444 MT 3919 444 LS
2688 
4339 444 MT 4353 444 LS
2689 
4772 444 MT 4786 444 LS
2690 
5206 444 MT 5220 444 LS
2691 
5640 444 MT 5654 444 LS
2692 
6074 444 MT 6088 444 LS
2693 
3045 473 MT 3045 473 LT 6298 473 LT ST
2694 
3045 554 MT 3045 554 LT 6298 554 LT ST
2695 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
2696 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) 3008 697 WT TSE RSS
2697 
3471 588 MT 3485 588 LS
2698 
3905 588 MT 3919 588 LS
2699 
4339 588 MT 4353 588 LS
2700 
4772 588 MT 4786 588 LS
2701 
5206 588 MT 5220 588 LS
2702 
5640 588 MT 5654 588 LS
2703 
6074 588 MT 6088 588 LS
2704 
3045 617 MT 3045 617 LT 6298 617 LT ST
2705 
3045 698 MT 3045 698 LT 6298 698 LT ST
2706 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
2707 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) 3008 841 WT TSE RSS
2708 
3471 732 MT 3485 732 LS
2709 
3905 732 MT 3919 732 LS
2710 
4339 732 MT 4353 732 LS
2711 
4772 732 MT 4786 732 LS
2712 
5206 732 MT 5220 732 LS
2713 
5640 732 MT 5654 732 LS
2714 
6074 732 MT 6088 732 LS
2715 
3045 842 MT 6298 842 LS
2716 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) 3008 985 WT TSE RSS
2717 
3471 876 MT 3485 876 LS
2718 
3905 876 MT 3919 876 LS
2719 
4339 876 MT 4353 876 LS
2720 
4772 876 MT 4786 876 LS
2721 
5206 876 MT 5220 876 LS
2722 
5640 876 MT 5654 876 LS
2723 
6074 876 MT 6088 876 LS
2724 
3045 906 MT 3045 986 LS
2725 
3045 986 MT 3261 986 LS
2726 
3261 986 MT 3261 906 LS
2727 
3261 906 MT 3478 906 LS
2728 
3478 906 MT 3478 986 LS
2729 
3478 986 MT 3695 986 LS
2730 
3695 986 MT 3695 906 LS
2731 
3695 906 MT 3912 906 LS
2732 
3912 906 MT 3912 986 LS
2733 
3912 986 MT 4129 986 LS
2734 
4129 986 MT 4129 906 LS
2735 
4129 906 MT 4346 906 LS
2736 
4346 906 MT 4346 986 LS
2737 
4346 986 MT 4563 986 LS
2738 
4563 986 MT 4563 906 LS
2739 
4563 906 MT 4779 906 LS
2740 
4779 906 MT 4779 986 LS
2741 
4779 986 MT 4996 986 LS
2742 
4996 986 MT 4996 906 LS
2743 
4996 906 MT 5213 906 LS
2744 
5213 906 MT 5213 986 LS
2745 
5213 986 MT 5430 986 LS
2746 
5430 986 MT 5430 906 LS
2747 
5430 906 MT 5647 906 LS
2748 
5647 906 MT 5647 986 LS
2749 
5647 986 MT 5864 986 LS
2750 
5864 986 MT 5864 906 LS
2751 
5864 906 MT 6081 906 LS
2752 
6081 906 MT 6081 986 LS
2753 
6081 986 MT 6298 986 LS
2754 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) 3008 1129 WT TSE RSS
2755 
3471 1020 MT 3485 1020 LS
2756 
3905 1020 MT 3919 1020 LS
2757 
4339 1020 MT 4353 1020 LS
2758 
4772 1020 MT 4786 1020 LS
2759 
5206 1020 MT 5220 1020 LS
2760 
5640 1020 MT 5654 1020 LS
2761 
6074 1020 MT 6088 1020 LS
2762 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
2763 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
2764 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
2765 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) 3008 1273 WT TSE RSS
2766 
3471 1164 MT 3485 1164 LS
2767 
3905 1164 MT 3919 1164 LS
2768 
4339 1164 MT 4353 1164 LS
2769 
4772 1164 MT 4786 1164 LS
2770 
5206 1164 MT 5220 1164 LS
2771 
5640 1164 MT 5654 1164 LS
2772 
6074 1164 MT 6088 1164 LS
2773 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
2774 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
2775 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
2776 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) 3008 1417 WT TSE RSS
2777 
3471 1308 MT 3485 1308 LS
2778 
3905 1308 MT 3919 1308 LS
2779 
4339 1308 MT 4353 1308 LS
2780 
4772 1308 MT 4786 1308 LS
2781 
5206 1308 MT 5220 1308 LS
2782 
5640 1308 MT 5654 1308 LS
2783 
6074 1308 MT 6088 1308 LS
2784 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
2785 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
2786 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
2787 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) 3008 1561 WT TSE RSS
2788 
3471 1452 MT 3485 1452 LS
2789 
3905 1452 MT 3919 1452 LS
2790 
4339 1452 MT 4353 1452 LS
2791 
4772 1452 MT 4786 1452 LS
2792 
5206 1452 MT 5220 1452 LS
2793 
5640 1452 MT 5654 1452 LS
2794 
6074 1452 MT 6088 1452 LS
2795 
3045 1522 MT 6298 1522 LS
2796 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) 3008 1705 WT TSE RSS
2797 
3471 1596 MT 3485 1596 LS
2798 
3905 1596 MT 3919 1596 LS
2799 
4339 1596 MT 4353 1596 LS
2800 
4772 1596 MT 4786 1596 LS
2801 
5206 1596 MT 5220 1596 LS
2802 
5640 1596 MT 5654 1596 LS
2803 
6074 1596 MT 6088 1596 LS
2804 
3045 1706 MT 6298 1706 LS
2805 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) 3008 1849 WT TSE RSS
2806 
3471 1740 MT 3485 1740 LS
2807 
3905 1740 MT 3919 1740 LS
2808 
4339 1740 MT 4353 1740 LS
2809 
4772 1740 MT 4786 1740 LS
2810 
5206 1740 MT 5220 1740 LS
2811 
5640 1740 MT 5654 1740 LS
2812 
6074 1740 MT 6088 1740 LS
2813 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
2814 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
2815 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
2816 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) 3008 1993 WT TSE RSS
2817 
3471 1884 MT 3485 1884 LS
2818 
3905 1884 MT 3919 1884 LS
2819 
4339 1884 MT 4353 1884 LS
2820 
4772 1884 MT 4786 1884 LS
2821 
5206 1884 MT 5220 1884 LS
2822 
5640 1884 MT 5654 1884 LS
2823 
6074 1884 MT 6088 1884 LS
2824 
3045 1994 MT 6298 1994 LS
2825 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) 3008 2137 WT TSE RSS
2826 
3471 2028 MT 3485 2028 LS
2827 
3905 2028 MT 3919 2028 LS
2828 
4339 2028 MT 4353 2028 LS
2829 
4772 2028 MT 4786 2028 LS
2830 
5206 2028 MT 5220 2028 LS
2831 
5640 2028 MT 5654 2028 LS
2832 
6074 2028 MT 6088 2028 LS
2833 
3045 2058 MT 6298 2058 LS
2834 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) 3008 2281 WT TSE RSS
2835 
3471 2172 MT 3485 2172 LS
2836 
3905 2172 MT 3919 2172 LS
2837 
4339 2172 MT 4353 2172 LS
2838 
4772 2172 MT 4786 2172 LS
2839 
5206 2172 MT 5220 2172 LS
2840 
5640 2172 MT 5654 2172 LS
2841 
6074 2172 MT 6088 2172 LS
2842 
3045 2282 MT 6298 2282 LS
2843 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) 3008 2425 WT TSE RSS
2844 
3471 2316 MT 3485 2316 LS
2845 
3905 2316 MT 3919 2316 LS
2846 
4339 2316 MT 4353 2316 LS
2847 
4772 2316 MT 4786 2316 LS
2848 
5206 2316 MT 5220 2316 LS
2849 
5640 2316 MT 5654 2316 LS
2850 
6074 2316 MT 6088 2316 LS
2851 
3045 2386 MT 6298 2386 LS
2852 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) 3008 2569 WT TSE RSS
2853 
3471 2460 MT 3485 2460 LS
2854 
3905 2460 MT 3919 2460 LS
2855 
4339 2460 MT 4353 2460 LS
2856 
4772 2460 MT 4786 2460 LS
2857 
5206 2460 MT 5220 2460 LS
2858 
5640 2460 MT 5654 2460 LS
2859 
6074 2460 MT 6088 2460 LS
2860 
3045 2570 MT 6298 2570 LS
2861 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) 3008 2713 WT TSE RSS
2862 
3471 2604 MT 3485 2604 LS
2863 
3905 2604 MT 3919 2604 LS
2864 
4339 2604 MT 4353 2604 LS
2865 
4772 2604 MT 4786 2604 LS
2866 
5206 2604 MT 5220 2604 LS
2867 
5640 2604 MT 5654 2604 LS
2868 
6074 2604 MT 6088 2604 LS
2869 
3045 2714 MT 6298 2714 LS
2870 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) 3008 2857 WT TSE RSS
2871 
3471 2748 MT 3485 2748 LS
2872 
3905 2748 MT 3919 2748 LS
2873 
4339 2748 MT 4353 2748 LS
2874 
4772 2748 MT 4786 2748 LS
2875 
5206 2748 MT 5220 2748 LS
2876 
5640 2748 MT 5654 2748 LS
2877 
6074 2748 MT 6088 2748 LS
2878 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
2879 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
2880 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
2881 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) 3008 3001 WT TSE RSS
2882 
3471 2892 MT 3485 2892 LS
2883 
3905 2892 MT 3919 2892 LS
2884 
4339 2892 MT 4353 2892 LS
2885 
4772 2892 MT 4786 2892 LS
2886 
5206 2892 MT 5220 2892 LS
2887 
5640 2892 MT 5654 2892 LS
2888 
6074 2892 MT 6088 2892 LS
2889 
3045 3002 MT 6298 3002 LS
2890 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) 3008 3145 WT TSE RSS
2891 
3471 3036 MT 3485 3036 LS
2892 
3905 3036 MT 3919 3036 LS
2893 
4339 3036 MT 4353 3036 LS
2894 
4772 3036 MT 4786 3036 LS
2895 
5206 3036 MT 5220 3036 LS
2896 
5640 3036 MT 5654 3036 LS
2897 
6074 3036 MT 6088 3036 LS
2898 
3045 3066 MT 6298 3066 LS
2899 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) 3008 3289 WT TSE RSS
2900 
3471 3180 MT 3485 3180 LS
2901 
3905 3180 MT 3919 3180 LS
2902 
4339 3180 MT 4353 3180 LS
2903 
4772 3180 MT 4786 3180 LS
2904 
5206 3180 MT 5220 3180 LS
2905 
5640 3180 MT 5654 3180 LS
2906 
6074 3180 MT 6088 3180 LS
2907 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
2908 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
2909 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
2910 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) 3008 3433 WT TSE RSS
2911 
3471 3324 MT 3485 3324 LS
2912 
3905 3324 MT 3919 3324 LS
2913 
4339 3324 MT 4353 3324 LS
2914 
4772 3324 MT 4786 3324 LS
2915 
5206 3324 MT 5220 3324 LS
2916 
5640 3324 MT 5654 3324 LS
2917 
6074 3324 MT 6088 3324 LS
2918 
3045 3434 MT 6298 3434 LS
2919 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) 3008 3577 WT TSE RSS
2920 
3471 3468 MT 3485 3468 LS
2921 
3905 3468 MT 3919 3468 LS
2922 
4339 3468 MT 4353 3468 LS
2923 
4772 3468 MT 4786 3468 LS
2924 
5206 3468 MT 5220 3468 LS
2925 
5640 3468 MT 5654 3468 LS
2926 
6074 3468 MT 6088 3468 LS
2927 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
2928 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
2929 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
2930 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) 3008 3721 WT TSE RSS
2931 
3471 3612 MT 3485 3612 LS
2932 
3905 3612 MT 3919 3612 LS
2933 
4339 3612 MT 4353 3612 LS
2934 
4772 3612 MT 4786 3612 LS
2935 
5206 3612 MT 5220 3612 LS
2936 
5640 3612 MT 5654 3612 LS
2937 
6074 3612 MT 6088 3612 LS
2938 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
2939 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
2940 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
2941 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) 3008 3865 WT TSE RSS
2942 
3471 3756 MT 3485 3756 LS
2943 
3905 3756 MT 3919 3756 LS
2944 
4339 3756 MT 4353 3756 LS
2945 
4772 3756 MT 4786 3756 LS
2946 
5206 3756 MT 5220 3756 LS
2947 
5640 3756 MT 5654 3756 LS
2948 
6074 3756 MT 6088 3756 LS
2949 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
2950 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
2951 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
2952 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) 3008 4009 WT TSE RSS
2953 
3471 3900 MT 3485 3900 LS
2954 
3905 3900 MT 3919 3900 LS
2955 
4339 3900 MT 4353 3900 LS
2956 
4772 3900 MT 4786 3900 LS
2957 
5206 3900 MT 5220 3900 LS
2958 
5640 3900 MT 5654 3900 LS
2959 
6074 3900 MT 6088 3900 LS
2960 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
2961 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
2962 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
2963 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) 3008 4153 WT TSE RSS
2964 
3471 4044 MT 3485 4044 LS
2965 
3905 4044 MT 3919 4044 LS
2966 
4339 4044 MT 4353 4044 LS
2967 
4772 4044 MT 4786 4044 LS
2968 
5206 4044 MT 5220 4044 LS
2969 
5640 4044 MT 5654 4044 LS
2970 
6074 4044 MT 6088 4044 LS
2971 
3045 4154 MT 6298 4154 LS
2972 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) 3008 4297 WT TSE RSS
2973 
3471 4188 MT 3485 4188 LS
2974 
3905 4188 MT 3919 4188 LS
2975 
4339 4188 MT 4353 4188 LS
2976 
4772 4188 MT 4786 4188 LS
2977 
5206 4188 MT 5220 4188 LS
2978 
5640 4188 MT 5654 4188 LS
2979 
6074 4188 MT 6088 4188 LS
2980 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
2981 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
2982 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
2983 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) 3008 4441 WT TSE RSS
2984 
3471 4332 MT 3485 4332 LS
2985 
3905 4332 MT 3919 4332 LS
2986 
4339 4332 MT 4353 4332 LS
2987 
4772 4332 MT 4786 4332 LS
2988 
5206 4332 MT 5220 4332 LS
2989 
5640 4332 MT 5654 4332 LS
2990 
6074 4332 MT 6088 4332 LS
2991 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
2992 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
2993 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
2994 
% draw footer
2995 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 3 Page: 5) 300 4799 WT TSW RSS
2996 
grestore
2997 
showpage
2998 
%%Page: 6 6
2999 
gsave
3000 
90 rotate 0.12 dup neg scale
3001 
% dump string table
3002 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
3003 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
3004 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
3005 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
3006 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
3007 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
3008 
/ARC {5 -2 roll SX 5 2 roll arc} def
3009 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
3010 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
3011 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
3012 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
3013 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
3014 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
3015 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
3016 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
3017 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
3018 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
3019 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
3020 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
3021 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
3022 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
3023 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
3024 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
3025 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
3026 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
3027 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
3028 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
3029 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
3030 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
3031 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
3032 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
3033 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
3034 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
3035 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
3036 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
3037 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
3038 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
3039 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
3040 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
3041 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
3042 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
3043 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
3044 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
3045 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
3046 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
3047 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
3048 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
3049 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
3050 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
3051 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
3052 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
3053 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
3054 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
3055 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
3056 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
3057 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
3058 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
3059 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
3060 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
3061 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
3062 
% draw waveform shading
3063 
[] 0 SD
3064 
2.995 setlinewidth
3065 
 
3066 
 
3067 
 
3068 
3045 329 MT 3045 329 LT 6298 329 LT ST
3069 
3045 410 MT 3045 410 LT 6298 410 LT ST
3070 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
3071 
3045 473 MT 3045 473 LT 6298 473 LT ST
3072 
3045 554 MT 3045 554 LT 6298 554 LT ST
3073 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
3074 
3045 698 MT 6298 698 LS
3075 
3045 842 MT 6298 842 LS
3076 
3045 986 MT 6298 986 LS
3077 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
3078 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
3079 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
3080 
3045 1274 MT 6298 1274 LS
3081 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
3082 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
3083 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
3084 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
3085 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
3086 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
3087 
3045 1706 MT 6298 1706 LS
3088 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
3089 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
3090 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
3091 
3045 1994 MT 6298 1994 LS
3092 
3045 2098 MT 6298 2098 LS
3093 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
3094 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
3095 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
3096 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
3097 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
3098 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
3099 
3045 2489 MT 3045 2489 LT 3254 2489 LT 3261 2530 LT ST
3100 
3045 2570 MT 3045 2570 LT 3254 2570 LT 3261 2530 LT ST
3101 
(4) 3059 2530 WT pop 0 originOffset 37 add RSS
3102 
3261 2530 MT 3261 2530 LT 3268 2489 LT 3688 2489 LT 3695 2530 LT ST
3103 
3261 2530 MT 3261 2530 LT 3268 2570 LT 3688 2570 LT 3695 2530 LT ST
3104 
(5) 3275 2530 WT pop 0 originOffset 37 add RSS
3105 
3695 2530 MT 3695 2530 LT 3702 2489 LT 4122 2489 LT 4129 2530 LT ST
3106 
3695 2530 MT 3695 2530 LT 3702 2570 LT 4122 2570 LT 4129 2530 LT ST
3107 
(6) 3709 2530 WT pop 0 originOffset 37 add RSS
3108 
4129 2530 MT 4129 2530 LT 4136 2489 LT 4556 2489 LT 4563 2530 LT ST
3109 
4129 2530 MT 4129 2530 LT 4136 2570 LT 4556 2570 LT 4563 2530 LT ST
3110 
(7) 4143 2530 WT pop 0 originOffset 37 add RSS
3111 
4563 2530 MT 4563 2530 LT 4570 2489 LT 4989 2489 LT 4996 2530 LT ST
3112 
4563 2530 MT 4563 2530 LT 4570 2570 LT 4989 2570 LT 4996 2530 LT ST
3113 
(0) 4577 2530 WT pop 0 originOffset 37 add RSS
3114 
4996 2530 MT 4996 2530 LT 5003 2489 LT 5423 2489 LT 5430 2530 LT ST
3115 
4996 2530 MT 4996 2530 LT 5003 2570 LT 5423 2570 LT 5430 2530 LT ST
3116 
(1) 5010 2530 WT pop 0 originOffset 37 add RSS
3117 
5430 2530 MT 5430 2530 LT 5437 2489 LT 5857 2489 LT 5864 2530 LT ST
3118 
5430 2530 MT 5430 2530 LT 5437 2570 LT 5857 2570 LT 5864 2530 LT ST
3119 
(2) 5444 2530 WT pop 0 originOffset 37 add RSS
3120 
5864 2530 MT 5864 2530 LT 5871 2489 LT 6298 2489 LT ST
3121 
5864 2530 MT 5864 2530 LT 5871 2570 LT 6298 2570 LT ST
3122 
(3) 5878 2530 WT pop 0 originOffset 37 add RSS
3123 
3045 2633 MT 3045 2633 LT 3254 2633 LT 3261 2674 LT ST
3124 
3045 2714 MT 3045 2714 LT 3254 2714 LT 3261 2674 LT ST
3125 
(3) 3059 2674 WT pop 0 originOffset 37 add RSS
3126 
3261 2674 MT 3261 2674 LT 3268 2633 LT 3688 2633 LT 3695 2674 LT ST
3127 
3261 2674 MT 3261 2674 LT 3268 2714 LT 3688 2714 LT 3695 2674 LT ST
3128 
(4) 3275 2674 WT pop 0 originOffset 37 add RSS
3129 
3695 2674 MT 3695 2674 LT 3702 2633 LT 4122 2633 LT 4129 2674 LT ST
3130 
3695 2674 MT 3695 2674 LT 3702 2714 LT 4122 2714 LT 4129 2674 LT ST
3131 
(5) 3709 2674 WT pop 0 originOffset 37 add RSS
3132 
4129 2674 MT 4129 2674 LT 4136 2633 LT 4556 2633 LT 4563 2674 LT ST
3133 
4129 2674 MT 4129 2674 LT 4136 2714 LT 4556 2714 LT 4563 2674 LT ST
3134 
(6) 4143 2674 WT pop 0 originOffset 37 add RSS
3135 
4563 2674 MT 4563 2674 LT 4570 2633 LT 4989 2633 LT 4996 2674 LT ST
3136 
4563 2674 MT 4563 2674 LT 4570 2714 LT 4989 2714 LT 4996 2674 LT ST
3137 
(7) 4577 2674 WT pop 0 originOffset 37 add RSS
3138 
4996 2674 MT 4996 2674 LT 5003 2633 LT 5423 2633 LT 5430 2674 LT ST
3139 
4996 2674 MT 4996 2674 LT 5003 2714 LT 5423 2714 LT 5430 2674 LT ST
3140 
(0) 5010 2674 WT pop 0 originOffset 37 add RSS
3141 
5430 2674 MT 5430 2674 LT 5437 2633 LT 5857 2633 LT 5864 2674 LT ST
3142 
5430 2674 MT 5430 2674 LT 5437 2714 LT 5857 2714 LT 5864 2674 LT ST
3143 
(1) 5444 2674 WT pop 0 originOffset 37 add RSS
3144 
5864 2674 MT 5864 2674 LT 5871 2633 LT 6298 2633 LT ST
3145 
5864 2674 MT 5864 2674 LT 5871 2714 LT 6298 2714 LT ST
3146 
(2) 5878 2674 WT pop 0 originOffset 37 add RSS
3147 
3045 2858 MT 6298 2858 LS
3148 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
3149 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
3150 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
3151 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
3152 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
3153 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
3154 
3045 3290 MT 6298 3290 LS
3155 
% draw timeline
3156 
3088 4533 MT 3088 4570 LS
3157 
3132 4533 MT 3132 4570 LS
3158 
3175 4533 MT 3175 4570 LS
3159 
3218 4533 MT 3218 4570 LS
3160 
3262 4533 MT 3262 4570 LS
3161 
3305 4533 MT 3305 4570 LS
3162 
3349 4533 MT 3349 4570 LS
3163 
3392 4533 MT 3392 4570 LS
3164 
3435 4533 MT 3435 4570 LS
3165 
3521 4533 MT 3521 4570 LS
3166 
3565 4533 MT 3565 4570 LS
3167 
3608 4533 MT 3608 4570 LS
3168 
3651 4533 MT 3651 4570 LS
3169 
3695 4533 MT 3695 4570 LS
3170 
3738 4533 MT 3738 4570 LS
3171 
3782 4533 MT 3782 4570 LS
3172 
3825 4533 MT 3825 4570 LS
3173 
3868 4533 MT 3868 4570 LS
3174 
3478 4506 MT 3478 4570 LS
3175 
(160) 3478 4649 WT TS RSS
3176 
3955 4533 MT 3955 4570 LS
3177 
3999 4533 MT 3999 4570 LS
3178 
4042 4533 MT 4042 4570 LS
3179 
4085 4533 MT 4085 4570 LS
3180 
4129 4533 MT 4129 4570 LS
3181 
4172 4533 MT 4172 4570 LS
3182 
4216 4533 MT 4216 4570 LS
3183 
4259 4533 MT 4259 4570 LS
3184 
4302 4533 MT 4302 4570 LS
3185 
3912 4506 MT 3912 4570 LS
3186 
4389 4533 MT 4389 4570 LS
3187 
4433 4533 MT 4433 4570 LS
3188 
4476 4533 MT 4476 4570 LS
3189 
4519 4533 MT 4519 4570 LS
3190 
4563 4533 MT 4563 4570 LS
3191 
4606 4533 MT 4606 4570 LS
3192 
4650 4533 MT 4650 4570 LS
3193 
4693 4533 MT 4693 4570 LS
3194 
4736 4533 MT 4736 4570 LS
3195 
4346 4506 MT 4346 4570 LS
3196 
(180) 4346 4649 WT TS RSS
3197 
4822 4533 MT 4822 4570 LS
3198 
4866 4533 MT 4866 4570 LS
3199 
4909 4533 MT 4909 4570 LS
3200 
4952 4533 MT 4952 4570 LS
3201 
4996 4533 MT 4996 4570 LS
3202 
5039 4533 MT 5039 4570 LS
3203 
5083 4533 MT 5083 4570 LS
3204 
5126 4533 MT 5126 4570 LS
3205 
5169 4533 MT 5169 4570 LS
3206 
4779 4506 MT 4779 4570 LS
3207 
5256 4533 MT 5256 4570 LS
3208 
5300 4533 MT 5300 4570 LS
3209 
5343 4533 MT 5343 4570 LS
3210 
5386 4533 MT 5386 4570 LS
3211 
5430 4533 MT 5430 4570 LS
3212 
5473 4533 MT 5473 4570 LS
3213 
5517 4533 MT 5517 4570 LS
3214 
5560 4533 MT 5560 4570 LS
3215 
5603 4533 MT 5603 4570 LS
3216 
5213 4506 MT 5213 4570 LS
3217 
(200) 5213 4649 WT TS RSS
3218 
5690 4533 MT 5690 4570 LS
3219 
5734 4533 MT 5734 4570 LS
3220 
5777 4533 MT 5777 4570 LS
3221 
5820 4533 MT 5820 4570 LS
3222 
5864 4533 MT 5864 4570 LS
3223 
5907 4533 MT 5907 4570 LS
3224 
5951 4533 MT 5951 4570 LS
3225 
5994 4533 MT 5994 4570 LS
3226 
6037 4533 MT 6037 4570 LS
3227 
5647 4506 MT 5647 4570 LS
3228 
6124 4533 MT 6124 4570 LS
3229 
6168 4533 MT 6168 4570 LS
3230 
6211 4533 MT 6211 4570 LS
3231 
6254 4533 MT 6254 4570 LS
3232 
6298 4533 MT 6298 4570 LS
3233 
6341 4533 MT 6341 4570 LS
3234 
6385 4533 MT 6385 4570 LS
3235 
6428 4533 MT 6428 4570 LS
3236 
6471 4533 MT 6471 4570 LS
3237 
6081 4506 MT 6081 4570 LS
3238 
(220) 6081 4649 WT TS RSS
3239 
% draw grid
3240 
3478 300 MT 3478 4506 LS
3241 
3912 300 MT 3912 4506 LS
3242 
4346 300 MT 4346 4506 LS
3243 
4779 300 MT 4779 4506 LS
3244 
5213 300 MT 5213 4506 LS
3245 
5647 300 MT 5647 4506 LS
3246 
6081 300 MT 6081 4506 LS
3247 
% draw waveforms
3248 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) 3008 409 WT TSE RSS
3249 
3471 300 MT 3485 300 LS
3250 
3905 300 MT 3919 300 LS
3251 
4339 300 MT 4353 300 LS
3252 
4772 300 MT 4786 300 LS
3253 
5206 300 MT 5220 300 LS
3254 
5640 300 MT 5654 300 LS
3255 
6074 300 MT 6088 300 LS
3256 
3045 329 MT 3045 329 LT 6298 329 LT ST
3257 
3045 410 MT 3045 410 LT 6298 410 LT ST
3258 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
3259 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) 3008 553 WT TSE RSS
3260 
3471 444 MT 3485 444 LS
3261 
3905 444 MT 3919 444 LS
3262 
4339 444 MT 4353 444 LS
3263 
4772 444 MT 4786 444 LS
3264 
5206 444 MT 5220 444 LS
3265 
5640 444 MT 5654 444 LS
3266 
6074 444 MT 6088 444 LS
3267 
3045 473 MT 3045 473 LT 6298 473 LT ST
3268 
3045 554 MT 3045 554 LT 6298 554 LT ST
3269 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
3270 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) 3008 697 WT TSE RSS
3271 
3471 588 MT 3485 588 LS
3272 
3905 588 MT 3919 588 LS
3273 
4339 588 MT 4353 588 LS
3274 
4772 588 MT 4786 588 LS
3275 
5206 588 MT 5220 588 LS
3276 
5640 588 MT 5654 588 LS
3277 
6074 588 MT 6088 588 LS
3278 
3045 698 MT 6298 698 LS
3279 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) 3008 841 WT TSE RSS
3280 
3471 732 MT 3485 732 LS
3281 
3905 732 MT 3919 732 LS
3282 
4339 732 MT 4353 732 LS
3283 
4772 732 MT 4786 732 LS
3284 
5206 732 MT 5220 732 LS
3285 
5640 732 MT 5654 732 LS
3286 
6074 732 MT 6088 732 LS
3287 
3045 842 MT 6298 842 LS
3288 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) 3008 985 WT TSE RSS
3289 
3471 876 MT 3485 876 LS
3290 
3905 876 MT 3919 876 LS
3291 
4339 876 MT 4353 876 LS
3292 
4772 876 MT 4786 876 LS
3293 
5206 876 MT 5220 876 LS
3294 
5640 876 MT 5654 876 LS
3295 
6074 876 MT 6088 876 LS
3296 
3045 986 MT 6298 986 LS
3297 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) 3008 1129 WT TSE RSS
3298 
3471 1020 MT 3485 1020 LS
3299 
3905 1020 MT 3919 1020 LS
3300 
4339 1020 MT 4353 1020 LS
3301 
4772 1020 MT 4786 1020 LS
3302 
5206 1020 MT 5220 1020 LS
3303 
5640 1020 MT 5654 1020 LS
3304 
6074 1020 MT 6088 1020 LS
3305 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
3306 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
3307 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
3308 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) 3008 1273 WT TSE RSS
3309 
3471 1164 MT 3485 1164 LS
3310 
3905 1164 MT 3919 1164 LS
3311 
4339 1164 MT 4353 1164 LS
3312 
4772 1164 MT 4786 1164 LS
3313 
5206 1164 MT 5220 1164 LS
3314 
5640 1164 MT 5654 1164 LS
3315 
6074 1164 MT 6088 1164 LS
3316 
3045 1274 MT 6298 1274 LS
3317 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) 3008 1417 WT TSE RSS
3318 
3471 1308 MT 3485 1308 LS
3319 
3905 1308 MT 3919 1308 LS
3320 
4339 1308 MT 4353 1308 LS
3321 
4772 1308 MT 4786 1308 LS
3322 
5206 1308 MT 5220 1308 LS
3323 
5640 1308 MT 5654 1308 LS
3324 
6074 1308 MT 6088 1308 LS
3325 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
3326 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
3327 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
3328 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) 3008 1561 WT TSE RSS
3329 
3471 1452 MT 3485 1452 LS
3330 
3905 1452 MT 3919 1452 LS
3331 
4339 1452 MT 4353 1452 LS
3332 
4772 1452 MT 4786 1452 LS
3333 
5206 1452 MT 5220 1452 LS
3334 
5640 1452 MT 5654 1452 LS
3335 
6074 1452 MT 6088 1452 LS
3336 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
3337 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
3338 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
3339 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) 3008 1705 WT TSE RSS
3340 
3471 1596 MT 3485 1596 LS
3341 
3905 1596 MT 3919 1596 LS
3342 
4339 1596 MT 4353 1596 LS
3343 
4772 1596 MT 4786 1596 LS
3344 
5206 1596 MT 5220 1596 LS
3345 
5640 1596 MT 5654 1596 LS
3346 
6074 1596 MT 6088 1596 LS
3347 
3045 1706 MT 6298 1706 LS
3348 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) 3008 1849 WT TSE RSS
3349 
3471 1740 MT 3485 1740 LS
3350 
3905 1740 MT 3919 1740 LS
3351 
4339 1740 MT 4353 1740 LS
3352 
4772 1740 MT 4786 1740 LS
3353 
5206 1740 MT 5220 1740 LS
3354 
5640 1740 MT 5654 1740 LS
3355 
6074 1740 MT 6088 1740 LS
3356 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
3357 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
3358 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
3359 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) 3008 1993 WT TSE RSS
3360 
3471 1884 MT 3485 1884 LS
3361 
3905 1884 MT 3919 1884 LS
3362 
4339 1884 MT 4353 1884 LS
3363 
4772 1884 MT 4786 1884 LS
3364 
5206 1884 MT 5220 1884 LS
3365 
5640 1884 MT 5654 1884 LS
3366 
6074 1884 MT 6088 1884 LS
3367 
3045 1994 MT 6298 1994 LS
3368 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) 3008 2137 WT TSE RSS
3369 
3471 2028 MT 3485 2028 LS
3370 
3905 2028 MT 3919 2028 LS
3371 
4339 2028 MT 4353 2028 LS
3372 
4772 2028 MT 4786 2028 LS
3373 
5206 2028 MT 5220 2028 LS
3374 
5640 2028 MT 5654 2028 LS
3375 
6074 2028 MT 6088 2028 LS
3376 
3045 2098 MT 6298 2098 LS
3377 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) 3008 2281 WT TSE RSS
3378 
3471 2172 MT 3485 2172 LS
3379 
3905 2172 MT 3919 2172 LS
3380 
4339 2172 MT 4353 2172 LS
3381 
4772 2172 MT 4786 2172 LS
3382 
5206 2172 MT 5220 2172 LS
3383 
5640 2172 MT 5654 2172 LS
3384 
6074 2172 MT 6088 2172 LS
3385 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
3386 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
3387 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
3388 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) 3008 2425 WT TSE RSS
3389 
3471 2316 MT 3485 2316 LS
3390 
3905 2316 MT 3919 2316 LS
3391 
4339 2316 MT 4353 2316 LS
3392 
4772 2316 MT 4786 2316 LS
3393 
5206 2316 MT 5220 2316 LS
3394 
5640 2316 MT 5654 2316 LS
3395 
6074 2316 MT 6088 2316 LS
3396 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
3397 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
3398 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
3399 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) 3008 2569 WT TSE RSS
3400 
3471 2460 MT 3485 2460 LS
3401 
3905 2460 MT 3919 2460 LS
3402 
4339 2460 MT 4353 2460 LS
3403 
4772 2460 MT 4786 2460 LS
3404 
5206 2460 MT 5220 2460 LS
3405 
5640 2460 MT 5654 2460 LS
3406 
6074 2460 MT 6088 2460 LS
3407 
3045 2489 MT 3045 2489 LT 3254 2489 LT 3261 2530 LT ST
3408 
3045 2570 MT 3045 2570 LT 3254 2570 LT 3261 2530 LT ST
3409 
(4) 3059 2530 WT pop 0 originOffset 37 add RSS
3410 
3261 2530 MT 3261 2530 LT 3268 2489 LT 3688 2489 LT 3695 2530 LT ST
3411 
3261 2530 MT 3261 2530 LT 3268 2570 LT 3688 2570 LT 3695 2530 LT ST
3412 
(5) 3275 2530 WT pop 0 originOffset 37 add RSS
3413 
3695 2530 MT 3695 2530 LT 3702 2489 LT 4122 2489 LT 4129 2530 LT ST
3414 
3695 2530 MT 3695 2530 LT 3702 2570 LT 4122 2570 LT 4129 2530 LT ST
3415 
(6) 3709 2530 WT pop 0 originOffset 37 add RSS
3416 
4129 2530 MT 4129 2530 LT 4136 2489 LT 4556 2489 LT 4563 2530 LT ST
3417 
4129 2530 MT 4129 2530 LT 4136 2570 LT 4556 2570 LT 4563 2530 LT ST
3418 
(7) 4143 2530 WT pop 0 originOffset 37 add RSS
3419 
4563 2530 MT 4563 2530 LT 4570 2489 LT 4989 2489 LT 4996 2530 LT ST
3420 
4563 2530 MT 4563 2530 LT 4570 2570 LT 4989 2570 LT 4996 2530 LT ST
3421 
(0) 4577 2530 WT pop 0 originOffset 37 add RSS
3422 
4996 2530 MT 4996 2530 LT 5003 2489 LT 5423 2489 LT 5430 2530 LT ST
3423 
4996 2530 MT 4996 2530 LT 5003 2570 LT 5423 2570 LT 5430 2530 LT ST
3424 
(1) 5010 2530 WT pop 0 originOffset 37 add RSS
3425 
5430 2530 MT 5430 2530 LT 5437 2489 LT 5857 2489 LT 5864 2530 LT ST
3426 
5430 2530 MT 5430 2530 LT 5437 2570 LT 5857 2570 LT 5864 2530 LT ST
3427 
(2) 5444 2530 WT pop 0 originOffset 37 add RSS
3428 
5864 2530 MT 5864 2530 LT 5871 2489 LT 6298 2489 LT ST
3429 
5864 2530 MT 5864 2530 LT 5871 2570 LT 6298 2570 LT ST
3430 
(3) 5878 2530 WT pop 0 originOffset 37 add RSS
3431 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) 3008 2713 WT TSE RSS
3432 
3471 2604 MT 3485 2604 LS
3433 
3905 2604 MT 3919 2604 LS
3434 
4339 2604 MT 4353 2604 LS
3435 
4772 2604 MT 4786 2604 LS
3436 
5206 2604 MT 5220 2604 LS
3437 
5640 2604 MT 5654 2604 LS
3438 
6074 2604 MT 6088 2604 LS
3439 
3045 2633 MT 3045 2633 LT 3254 2633 LT 3261 2674 LT ST
3440 
3045 2714 MT 3045 2714 LT 3254 2714 LT 3261 2674 LT ST
3441 
(3) 3059 2674 WT pop 0 originOffset 37 add RSS
3442 
3261 2674 MT 3261 2674 LT 3268 2633 LT 3688 2633 LT 3695 2674 LT ST
3443 
3261 2674 MT 3261 2674 LT 3268 2714 LT 3688 2714 LT 3695 2674 LT ST
3444 
(4) 3275 2674 WT pop 0 originOffset 37 add RSS
3445 
3695 2674 MT 3695 2674 LT 3702 2633 LT 4122 2633 LT 4129 2674 LT ST
3446 
3695 2674 MT 3695 2674 LT 3702 2714 LT 4122 2714 LT 4129 2674 LT ST
3447 
(5) 3709 2674 WT pop 0 originOffset 37 add RSS
3448 
4129 2674 MT 4129 2674 LT 4136 2633 LT 4556 2633 LT 4563 2674 LT ST
3449 
4129 2674 MT 4129 2674 LT 4136 2714 LT 4556 2714 LT 4563 2674 LT ST
3450 
(6) 4143 2674 WT pop 0 originOffset 37 add RSS
3451 
4563 2674 MT 4563 2674 LT 4570 2633 LT 4989 2633 LT 4996 2674 LT ST
3452 
4563 2674 MT 4563 2674 LT 4570 2714 LT 4989 2714 LT 4996 2674 LT ST
3453 
(7) 4577 2674 WT pop 0 originOffset 37 add RSS
3454 
4996 2674 MT 4996 2674 LT 5003 2633 LT 5423 2633 LT 5430 2674 LT ST
3455 
4996 2674 MT 4996 2674 LT 5003 2714 LT 5423 2714 LT 5430 2674 LT ST
3456 
(0) 5010 2674 WT pop 0 originOffset 37 add RSS
3457 
5430 2674 MT 5430 2674 LT 5437 2633 LT 5857 2633 LT 5864 2674 LT ST
3458 
5430 2674 MT 5430 2674 LT 5437 2714 LT 5857 2714 LT 5864 2674 LT ST
3459 
(1) 5444 2674 WT pop 0 originOffset 37 add RSS
3460 
5864 2674 MT 5864 2674 LT 5871 2633 LT 6298 2633 LT ST
3461 
5864 2674 MT 5864 2674 LT 5871 2714 LT 6298 2714 LT ST
3462 
(2) 5878 2674 WT pop 0 originOffset 37 add RSS
3463 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) 3008 2857 WT TSE RSS
3464 
3471 2748 MT 3485 2748 LS
3465 
3905 2748 MT 3919 2748 LS
3466 
4339 2748 MT 4353 2748 LS
3467 
4772 2748 MT 4786 2748 LS
3468 
5206 2748 MT 5220 2748 LS
3469 
5640 2748 MT 5654 2748 LS
3470 
6074 2748 MT 6088 2748 LS
3471 
3045 2858 MT 6298 2858 LS
3472 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) 3008 3001 WT TSE RSS
3473 
3471 2892 MT 3485 2892 LS
3474 
3905 2892 MT 3919 2892 LS
3475 
4339 2892 MT 4353 2892 LS
3476 
4772 2892 MT 4786 2892 LS
3477 
5206 2892 MT 5220 2892 LS
3478 
5640 2892 MT 5654 2892 LS
3479 
6074 2892 MT 6088 2892 LS
3480 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
3481 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
3482 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
3483 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) 3008 3145 WT TSE RSS
3484 
3471 3036 MT 3485 3036 LS
3485 
3905 3036 MT 3919 3036 LS
3486 
4339 3036 MT 4353 3036 LS
3487 
4772 3036 MT 4786 3036 LS
3488 
5206 3036 MT 5220 3036 LS
3489 
5640 3036 MT 5654 3036 LS
3490 
6074 3036 MT 6088 3036 LS
3491 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
3492 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
3493 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
3494 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) 3008 3289 WT TSE RSS
3495 
3471 3180 MT 3485 3180 LS
3496 
3905 3180 MT 3919 3180 LS
3497 
4339 3180 MT 4353 3180 LS
3498 
4772 3180 MT 4786 3180 LS
3499 
5206 3180 MT 5220 3180 LS
3500 
5640 3180 MT 5654 3180 LS
3501 
6074 3180 MT 6088 3180 LS
3502 
3045 3290 MT 6298 3290 LS
3503 
% draw footer
3504 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 3 Page: 6) 300 4799 WT TSW RSS
3505 
grestore
3506 
showpage
3507 
%%Page: 7 7
3508 
gsave
3509 
90 rotate 0.12 dup neg scale
3510 
% dump string table
3511 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
3512 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
3513 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
3514 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
3515 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
3516 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
3517 
/ARC {5 -2 roll SX 5 2 roll arc} def
3518 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
3519 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
3520 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
3521 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
3522 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
3523 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
3524 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
3525 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
3526 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
3527 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
3528 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
3529 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
3530 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
3531 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
3532 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
3533 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
3534 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
3535 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
3536 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
3537 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
3538 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
3539 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
3540 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
3541 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
3542 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
3543 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
3544 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
3545 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
3546 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
3547 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
3548 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
3549 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
3550 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
3551 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
3552 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
3553 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
3554 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
3555 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
3556 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
3557 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
3558 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
3559 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
3560 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
3561 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
3562 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
3563 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
3564 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
3565 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
3566 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
3567 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
3568 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
3569 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
3570 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
3571 
% draw waveform shading
3572 
[] 0 SD
3573 
2.995 setlinewidth
3574 
 
3575 
 
3576 
 
3577 
3045 329 MT 3045 329 LT 6298 329 LT ST
3578 
3045 410 MT 3045 410 LT 6298 410 LT ST
3579 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
3580 
3045 473 MT 3045 473 LT 6298 473 LT ST
3581 
3045 554 MT 3045 554 LT 6298 554 LT ST
3582 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
3583 
3045 617 MT 3045 617 LT 6298 617 LT ST
3584 
3045 698 MT 3045 698 LT 6298 698 LT ST
3585 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
3586 
3045 842 MT 6298 842 LS
3587 
3045 986 MT 3045 906 LS
3588 
3045 906 MT 3261 906 LS
3589 
3261 906 MT 3261 986 LS
3590 
3261 986 MT 3478 986 LS
3591 
3478 986 MT 3478 906 LS
3592 
3478 906 MT 3695 906 LS
3593 
3695 906 MT 3695 986 LS
3594 
3695 986 MT 3912 986 LS
3595 
3912 986 MT 3912 906 LS
3596 
3912 906 MT 4129 906 LS
3597 
4129 906 MT 4129 986 LS
3598 
4129 986 MT 4346 986 LS
3599 
4346 986 MT 4346 906 LS
3600 
4346 906 MT 4563 906 LS
3601 
4563 906 MT 4563 986 LS
3602 
4563 986 MT 4779 986 LS
3603 
4779 986 MT 4779 906 LS
3604 
4779 906 MT 4996 906 LS
3605 
4996 906 MT 4996 986 LS
3606 
4996 986 MT 5213 986 LS
3607 
5213 986 MT 5213 906 LS
3608 
5213 906 MT 5430 906 LS
3609 
5430 906 MT 5430 986 LS
3610 
5430 986 MT 5647 986 LS
3611 
5647 986 MT 5647 906 LS
3612 
5647 906 MT 5864 906 LS
3613 
5864 906 MT 5864 986 LS
3614 
5864 986 MT 6081 986 LS
3615 
6081 986 MT 6081 906 LS
3616 
6081 906 MT 6298 906 LS
3617 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
3618 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
3619 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
3620 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
3621 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
3622 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
3623 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
3624 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
3625 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
3626 
3045 1522 MT 6298 1522 LS
3627 
3045 1706 MT 6298 1706 LS
3628 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
3629 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
3630 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
3631 
3045 1994 MT 6298 1994 LS
3632 
3045 2058 MT 6298 2058 LS
3633 
3045 2282 MT 6298 2282 LS
3634 
3045 2386 MT 6298 2386 LS
3635 
3045 2570 MT 6298 2570 LS
3636 
3045 2714 MT 6298 2714 LS
3637 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
3638 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
3639 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
3640 
3045 3002 MT 6298 3002 LS
3641 
3045 3066 MT 6298 3066 LS
3642 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
3643 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
3644 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
3645 
3045 3434 MT 6298 3434 LS
3646 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
3647 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
3648 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
3649 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
3650 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
3651 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
3652 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
3653 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
3654 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
3655 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
3656 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
3657 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
3658 
3045 4154 MT 6298 4154 LS
3659 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
3660 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
3661 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
3662 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
3663 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
3664 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
3665 
% draw timeline
3666 
3088 4533 MT 3088 4570 LS
3667 
3132 4533 MT 3132 4570 LS
3668 
3175 4533 MT 3175 4570 LS
3669 
3218 4533 MT 3218 4570 LS
3670 
3304 4533 MT 3304 4570 LS
3671 
3348 4533 MT 3348 4570 LS
3672 
3391 4533 MT 3391 4570 LS
3673 
3434 4533 MT 3434 4570 LS
3674 
3478 4533 MT 3478 4570 LS
3675 
3521 4533 MT 3521 4570 LS
3676 
3565 4533 MT 3565 4570 LS
3677 
3608 4533 MT 3608 4570 LS
3678 
3651 4533 MT 3651 4570 LS
3679 
3261 4506 MT 3261 4570 LS
3680 
3738 4533 MT 3738 4570 LS
3681 
3782 4533 MT 3782 4570 LS
3682 
3825 4533 MT 3825 4570 LS
3683 
3868 4533 MT 3868 4570 LS
3684 
3912 4533 MT 3912 4570 LS
3685 
3955 4533 MT 3955 4570 LS
3686 
3999 4533 MT 3999 4570 LS
3687 
4042 4533 MT 4042 4570 LS
3688 
4085 4533 MT 4085 4570 LS
3689 
3695 4506 MT 3695 4570 LS
3690 
(240) 3695 4649 WT TS RSS
3691 
4172 4533 MT 4172 4570 LS
3692 
4216 4533 MT 4216 4570 LS
3693 
4259 4533 MT 4259 4570 LS
3694 
4302 4533 MT 4302 4570 LS
3695 
4346 4533 MT 4346 4570 LS
3696 
4389 4533 MT 4389 4570 LS
3697 
4433 4533 MT 4433 4570 LS
3698 
4476 4533 MT 4476 4570 LS
3699 
4519 4533 MT 4519 4570 LS
3700 
4129 4506 MT 4129 4570 LS
3701 
4606 4533 MT 4606 4570 LS
3702 
4650 4533 MT 4650 4570 LS
3703 
4693 4533 MT 4693 4570 LS
3704 
4736 4533 MT 4736 4570 LS
3705 
4780 4533 MT 4780 4570 LS
3706 
4823 4533 MT 4823 4570 LS
3707 
4867 4533 MT 4867 4570 LS
3708 
4910 4533 MT 4910 4570 LS
3709 
4953 4533 MT 4953 4570 LS
3710 
4563 4506 MT 4563 4570 LS
3711 
(260) 4563 4649 WT TS RSS
3712 
5039 4533 MT 5039 4570 LS
3713 
5083 4533 MT 5083 4570 LS
3714 
5126 4533 MT 5126 4570 LS
3715 
5169 4533 MT 5169 4570 LS
3716 
5213 4533 MT 5213 4570 LS
3717 
5256 4533 MT 5256 4570 LS
3718 
5300 4533 MT 5300 4570 LS
3719 
5343 4533 MT 5343 4570 LS
3720 
5386 4533 MT 5386 4570 LS
3721 
4996 4506 MT 4996 4570 LS
3722 
5473 4533 MT 5473 4570 LS
3723 
5517 4533 MT 5517 4570 LS
3724 
5560 4533 MT 5560 4570 LS
3725 
5603 4533 MT 5603 4570 LS
3726 
5647 4533 MT 5647 4570 LS
3727 
5690 4533 MT 5690 4570 LS
3728 
5734 4533 MT 5734 4570 LS
3729 
5777 4533 MT 5777 4570 LS
3730 
5820 4533 MT 5820 4570 LS
3731 
5430 4506 MT 5430 4570 LS
3732 
(280) 5430 4649 WT TS RSS
3733 
5907 4533 MT 5907 4570 LS
3734 
5951 4533 MT 5951 4570 LS
3735 
5994 4533 MT 5994 4570 LS
3736 
6037 4533 MT 6037 4570 LS
3737 
6081 4533 MT 6081 4570 LS
3738 
6124 4533 MT 6124 4570 LS
3739 
6168 4533 MT 6168 4570 LS
3740 
6211 4533 MT 6211 4570 LS
3741 
6254 4533 MT 6254 4570 LS
3742 
5864 4506 MT 5864 4570 LS
3743 
6341 4533 MT 6341 4570 LS
3744 
6385 4533 MT 6385 4570 LS
3745 
6428 4533 MT 6428 4570 LS
3746 
6471 4533 MT 6471 4570 LS
3747 
6515 4533 MT 6515 4570 LS
3748 
6558 4533 MT 6558 4570 LS
3749 
6602 4533 MT 6602 4570 LS
3750 
6645 4533 MT 6645 4570 LS
3751 
6688 4533 MT 6688 4570 LS
3752 
6298 4506 MT 6298 4570 LS
3753 
(300) 6298 4649 WT TS RSS
3754 
% draw grid
3755 
3261 300 MT 3261 4506 LS
3756 
3695 300 MT 3695 4506 LS
3757 
4129 300 MT 4129 4506 LS
3758 
4563 300 MT 4563 4506 LS
3759 
4996 300 MT 4996 4506 LS
3760 
5430 300 MT 5430 4506 LS
3761 
5864 300 MT 5864 4506 LS
3762 
6298 300 MT 6298 4506 LS
3763 
% draw waveforms
3764 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) 3008 409 WT TSE RSS
3765 
3254 300 MT 3268 300 LS
3766 
3688 300 MT 3702 300 LS
3767 
4122 300 MT 4136 300 LS
3768 
4556 300 MT 4570 300 LS
3769 
4989 300 MT 5003 300 LS
3770 
5423 300 MT 5437 300 LS
3771 
5857 300 MT 5871 300 LS
3772 
6291 300 MT 6305 300 LS
3773 
3045 329 MT 3045 329 LT 6298 329 LT ST
3774 
3045 410 MT 3045 410 LT 6298 410 LT ST
3775 
(4) 3059 370 WT pop 0 originOffset 37 add RSS
3776 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) 3008 553 WT TSE RSS
3777 
3254 444 MT 3268 444 LS
3778 
3688 444 MT 3702 444 LS
3779 
4122 444 MT 4136 444 LS
3780 
4556 444 MT 4570 444 LS
3781 
4989 444 MT 5003 444 LS
3782 
5423 444 MT 5437 444 LS
3783 
5857 444 MT 5871 444 LS
3784 
6291 444 MT 6305 444 LS
3785 
3045 473 MT 3045 473 LT 6298 473 LT ST
3786 
3045 554 MT 3045 554 LT 6298 554 LT ST
3787 
(00610000) 3059 514 WT pop 0 originOffset 37 add RSS
3788 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) 3008 697 WT TSE RSS
3789 
3254 588 MT 3268 588 LS
3790 
3688 588 MT 3702 588 LS
3791 
4122 588 MT 4136 588 LS
3792 
4556 588 MT 4570 588 LS
3793 
4989 588 MT 5003 588 LS
3794 
5423 588 MT 5437 588 LS
3795 
5857 588 MT 5871 588 LS
3796 
6291 588 MT 6305 588 LS
3797 
3045 617 MT 3045 617 LT 6298 617 LT ST
3798 
3045 698 MT 3045 698 LT 6298 698 LT ST
3799 
(0) 3059 658 WT pop 0 originOffset 37 add RSS
3800 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) 3008 841 WT TSE RSS
3801 
3254 732 MT 3268 732 LS
3802 
3688 732 MT 3702 732 LS
3803 
4122 732 MT 4136 732 LS
3804 
4556 732 MT 4570 732 LS
3805 
4989 732 MT 5003 732 LS
3806 
5423 732 MT 5437 732 LS
3807 
5857 732 MT 5871 732 LS
3808 
6291 732 MT 6305 732 LS
3809 
3045 842 MT 6298 842 LS
3810 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) 3008 985 WT TSE RSS
3811 
3254 876 MT 3268 876 LS
3812 
3688 876 MT 3702 876 LS
3813 
4122 876 MT 4136 876 LS
3814 
4556 876 MT 4570 876 LS
3815 
4989 876 MT 5003 876 LS
3816 
5423 876 MT 5437 876 LS
3817 
5857 876 MT 5871 876 LS
3818 
6291 876 MT 6305 876 LS
3819 
3045 986 MT 3045 906 LS
3820 
3045 906 MT 3261 906 LS
3821 
3261 906 MT 3261 986 LS
3822 
3261 986 MT 3478 986 LS
3823 
3478 986 MT 3478 906 LS
3824 
3478 906 MT 3695 906 LS
3825 
3695 906 MT 3695 986 LS
3826 
3695 986 MT 3912 986 LS
3827 
3912 986 MT 3912 906 LS
3828 
3912 906 MT 4129 906 LS
3829 
4129 906 MT 4129 986 LS
3830 
4129 986 MT 4346 986 LS
3831 
4346 986 MT 4346 906 LS
3832 
4346 906 MT 4563 906 LS
3833 
4563 906 MT 4563 986 LS
3834 
4563 986 MT 4779 986 LS
3835 
4779 986 MT 4779 906 LS
3836 
4779 906 MT 4996 906 LS
3837 
4996 906 MT 4996 986 LS
3838 
4996 986 MT 5213 986 LS
3839 
5213 986 MT 5213 906 LS
3840 
5213 906 MT 5430 906 LS
3841 
5430 906 MT 5430 986 LS
3842 
5430 986 MT 5647 986 LS
3843 
5647 986 MT 5647 906 LS
3844 
5647 906 MT 5864 906 LS
3845 
5864 906 MT 5864 986 LS
3846 
5864 986 MT 6081 986 LS
3847 
6081 986 MT 6081 906 LS
3848 
6081 906 MT 6298 906 LS
3849 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) 3008 1129 WT TSE RSS
3850 
3254 1020 MT 3268 1020 LS
3851 
3688 1020 MT 3702 1020 LS
3852 
4122 1020 MT 4136 1020 LS
3853 
4556 1020 MT 4570 1020 LS
3854 
4989 1020 MT 5003 1020 LS
3855 
5423 1020 MT 5437 1020 LS
3856 
5857 1020 MT 5871 1020 LS
3857 
6291 1020 MT 6305 1020 LS
3858 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
3859 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
3860 
(3) 3059 1090 WT pop 0 originOffset 37 add RSS
3861 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) 3008 1273 WT TSE RSS
3862 
3254 1164 MT 3268 1164 LS
3863 
3688 1164 MT 3702 1164 LS
3864 
4122 1164 MT 4136 1164 LS
3865 
4556 1164 MT 4570 1164 LS
3866 
4989 1164 MT 5003 1164 LS
3867 
5423 1164 MT 5437 1164 LS
3868 
5857 1164 MT 5871 1164 LS
3869 
6291 1164 MT 6305 1164 LS
3870 
3045 1193 MT 3045 1193 LT 6298 1193 LT ST
3871 
3045 1274 MT 3045 1274 LT 6298 1274 LT ST
3872 
(00) 3059 1234 WT pop 0 originOffset 37 add RSS
3873 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) 3008 1417 WT TSE RSS
3874 
3254 1308 MT 3268 1308 LS
3875 
3688 1308 MT 3702 1308 LS
3876 
4122 1308 MT 4136 1308 LS
3877 
4556 1308 MT 4570 1308 LS
3878 
4989 1308 MT 5003 1308 LS
3879 
5423 1308 MT 5437 1308 LS
3880 
5857 1308 MT 5871 1308 LS
3881 
6291 1308 MT 6305 1308 LS
3882 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
3883 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
3884 
(00) 3059 1378 WT pop 0 originOffset 37 add RSS
3885 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) 3008 1561 WT TSE RSS
3886 
3254 1452 MT 3268 1452 LS
3887 
3688 1452 MT 3702 1452 LS
3888 
4122 1452 MT 4136 1452 LS
3889 
4556 1452 MT 4570 1452 LS
3890 
4989 1452 MT 5003 1452 LS
3891 
5423 1452 MT 5437 1452 LS
3892 
5857 1452 MT 5871 1452 LS
3893 
6291 1452 MT 6305 1452 LS
3894 
3045 1522 MT 6298 1522 LS
3895 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) 3008 1705 WT TSE RSS
3896 
3254 1596 MT 3268 1596 LS
3897 
3688 1596 MT 3702 1596 LS
3898 
4122 1596 MT 4136 1596 LS
3899 
4556 1596 MT 4570 1596 LS
3900 
4989 1596 MT 5003 1596 LS
3901 
5423 1596 MT 5437 1596 LS
3902 
5857 1596 MT 5871 1596 LS
3903 
6291 1596 MT 6305 1596 LS
3904 
3045 1706 MT 6298 1706 LS
3905 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) 3008 1849 WT TSE RSS
3906 
3254 1740 MT 3268 1740 LS
3907 
3688 1740 MT 3702 1740 LS
3908 
4122 1740 MT 4136 1740 LS
3909 
4556 1740 MT 4570 1740 LS
3910 
4989 1740 MT 5003 1740 LS
3911 
5423 1740 MT 5437 1740 LS
3912 
5857 1740 MT 5871 1740 LS
3913 
6291 1740 MT 6305 1740 LS
3914 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
3915 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
3916 
(14610000) 3059 1810 WT pop 0 originOffset 37 add RSS
3917 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) 3008 1993 WT TSE RSS
3918 
3254 1884 MT 3268 1884 LS
3919 
3688 1884 MT 3702 1884 LS
3920 
4122 1884 MT 4136 1884 LS
3921 
4556 1884 MT 4570 1884 LS
3922 
4989 1884 MT 5003 1884 LS
3923 
5423 1884 MT 5437 1884 LS
3924 
5857 1884 MT 5871 1884 LS
3925 
6291 1884 MT 6305 1884 LS
3926 
3045 1994 MT 6298 1994 LS
3927 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) 3008 2137 WT TSE RSS
3928 
3254 2028 MT 3268 2028 LS
3929 
3688 2028 MT 3702 2028 LS
3930 
4122 2028 MT 4136 2028 LS
3931 
4556 2028 MT 4570 2028 LS
3932 
4989 2028 MT 5003 2028 LS
3933 
5423 2028 MT 5437 2028 LS
3934 
5857 2028 MT 5871 2028 LS
3935 
6291 2028 MT 6305 2028 LS
3936 
3045 2058 MT 6298 2058 LS
3937 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) 3008 2281 WT TSE RSS
3938 
3254 2172 MT 3268 2172 LS
3939 
3688 2172 MT 3702 2172 LS
3940 
4122 2172 MT 4136 2172 LS
3941 
4556 2172 MT 4570 2172 LS
3942 
4989 2172 MT 5003 2172 LS
3943 
5423 2172 MT 5437 2172 LS
3944 
5857 2172 MT 5871 2172 LS
3945 
6291 2172 MT 6305 2172 LS
3946 
3045 2282 MT 6298 2282 LS
3947 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) 3008 2425 WT TSE RSS
3948 
3254 2316 MT 3268 2316 LS
3949 
3688 2316 MT 3702 2316 LS
3950 
4122 2316 MT 4136 2316 LS
3951 
4556 2316 MT 4570 2316 LS
3952 
4989 2316 MT 5003 2316 LS
3953 
5423 2316 MT 5437 2316 LS
3954 
5857 2316 MT 5871 2316 LS
3955 
6291 2316 MT 6305 2316 LS
3956 
3045 2386 MT 6298 2386 LS
3957 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) 3008 2569 WT TSE RSS
3958 
3254 2460 MT 3268 2460 LS
3959 
3688 2460 MT 3702 2460 LS
3960 
4122 2460 MT 4136 2460 LS
3961 
4556 2460 MT 4570 2460 LS
3962 
4989 2460 MT 5003 2460 LS
3963 
5423 2460 MT 5437 2460 LS
3964 
5857 2460 MT 5871 2460 LS
3965 
6291 2460 MT 6305 2460 LS
3966 
3045 2570 MT 6298 2570 LS
3967 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) 3008 2713 WT TSE RSS
3968 
3254 2604 MT 3268 2604 LS
3969 
3688 2604 MT 3702 2604 LS
3970 
4122 2604 MT 4136 2604 LS
3971 
4556 2604 MT 4570 2604 LS
3972 
4989 2604 MT 5003 2604 LS
3973 
5423 2604 MT 5437 2604 LS
3974 
5857 2604 MT 5871 2604 LS
3975 
6291 2604 MT 6305 2604 LS
3976 
3045 2714 MT 6298 2714 LS
3977 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) 3008 2857 WT TSE RSS
3978 
3254 2748 MT 3268 2748 LS
3979 
3688 2748 MT 3702 2748 LS
3980 
4122 2748 MT 4136 2748 LS
3981 
4556 2748 MT 4570 2748 LS
3982 
4989 2748 MT 5003 2748 LS
3983 
5423 2748 MT 5437 2748 LS
3984 
5857 2748 MT 5871 2748 LS
3985 
6291 2748 MT 6305 2748 LS
3986 
3045 2777 MT 3045 2777 LT 6298 2777 LT ST
3987 
3045 2858 MT 3045 2858 LT 6298 2858 LT ST
3988 
(14610000) 3059 2818 WT pop 0 originOffset 37 add RSS
3989 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) 3008 3001 WT TSE RSS
3990 
3254 2892 MT 3268 2892 LS
3991 
3688 2892 MT 3702 2892 LS
3992 
4122 2892 MT 4136 2892 LS
3993 
4556 2892 MT 4570 2892 LS
3994 
4989 2892 MT 5003 2892 LS
3995 
5423 2892 MT 5437 2892 LS
3996 
5857 2892 MT 5871 2892 LS
3997 
6291 2892 MT 6305 2892 LS
3998 
3045 3002 MT 6298 3002 LS
3999 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) 3008 3145 WT TSE RSS
4000 
3254 3036 MT 3268 3036 LS
4001 
3688 3036 MT 3702 3036 LS
4002 
4122 3036 MT 4136 3036 LS
4003 
4556 3036 MT 4570 3036 LS
4004 
4989 3036 MT 5003 3036 LS
4005 
5423 3036 MT 5437 3036 LS
4006 
5857 3036 MT 5871 3036 LS
4007 
6291 3036 MT 6305 3036 LS
4008 
3045 3066 MT 6298 3066 LS
4009 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) 3008 3289 WT TSE RSS
4010 
3254 3180 MT 3268 3180 LS
4011 
3688 3180 MT 3702 3180 LS
4012 
4122 3180 MT 4136 3180 LS
4013 
4556 3180 MT 4570 3180 LS
4014 
4989 3180 MT 5003 3180 LS
4015 
5423 3180 MT 5437 3180 LS
4016 
5857 3180 MT 5871 3180 LS
4017 
6291 3180 MT 6305 3180 LS
4018 
3045 3209 MT 3045 3209 LT 6298 3209 LT ST
4019 
3045 3290 MT 3045 3290 LT 6298 3290 LT ST
4020 
(14610000) 3059 3250 WT pop 0 originOffset 37 add RSS
4021 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) 3008 3433 WT TSE RSS
4022 
3254 3324 MT 3268 3324 LS
4023 
3688 3324 MT 3702 3324 LS
4024 
4122 3324 MT 4136 3324 LS
4025 
4556 3324 MT 4570 3324 LS
4026 
4989 3324 MT 5003 3324 LS
4027 
5423 3324 MT 5437 3324 LS
4028 
5857 3324 MT 5871 3324 LS
4029 
6291 3324 MT 6305 3324 LS
4030 
3045 3434 MT 6298 3434 LS
4031 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) 3008 3577 WT TSE RSS
4032 
3254 3468 MT 3268 3468 LS
4033 
3688 3468 MT 3702 3468 LS
4034 
4122 3468 MT 4136 3468 LS
4035 
4556 3468 MT 4570 3468 LS
4036 
4989 3468 MT 5003 3468 LS
4037 
5423 3468 MT 5437 3468 LS
4038 
5857 3468 MT 5871 3468 LS
4039 
6291 3468 MT 6305 3468 LS
4040 
3045 3497 MT 3045 3497 LT 6298 3497 LT ST
4041 
3045 3578 MT 3045 3578 LT 6298 3578 LT ST
4042 
(00000000) 3059 3538 WT pop 0 originOffset 37 add RSS
4043 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) 3008 3721 WT TSE RSS
4044 
3254 3612 MT 3268 3612 LS
4045 
3688 3612 MT 3702 3612 LS
4046 
4122 3612 MT 4136 3612 LS
4047 
4556 3612 MT 4570 3612 LS
4048 
4989 3612 MT 5003 3612 LS
4049 
5423 3612 MT 5437 3612 LS
4050 
5857 3612 MT 5871 3612 LS
4051 
6291 3612 MT 6305 3612 LS
4052 
3045 3641 MT 3045 3641 LT 6298 3641 LT ST
4053 
3045 3722 MT 3045 3722 LT 6298 3722 LT ST
4054 
(0) 3059 3682 WT pop 0 originOffset 37 add RSS
4055 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) 3008 3865 WT TSE RSS
4056 
3254 3756 MT 3268 3756 LS
4057 
3688 3756 MT 3702 3756 LS
4058 
4122 3756 MT 4136 3756 LS
4059 
4556 3756 MT 4570 3756 LS
4060 
4989 3756 MT 5003 3756 LS
4061 
5423 3756 MT 5437 3756 LS
4062 
5857 3756 MT 5871 3756 LS
4063 
6291 3756 MT 6305 3756 LS
4064 
3045 3785 MT 3045 3785 LT 6298 3785 LT ST
4065 
3045 3866 MT 3045 3866 LT 6298 3866 LT ST
4066 
(0) 3059 3826 WT pop 0 originOffset 37 add RSS
4067 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) 3008 4009 WT TSE RSS
4068 
3254 3900 MT 3268 3900 LS
4069 
3688 3900 MT 3702 3900 LS
4070 
4122 3900 MT 4136 3900 LS
4071 
4556 3900 MT 4570 3900 LS
4072 
4989 3900 MT 5003 3900 LS
4073 
5423 3900 MT 5437 3900 LS
4074 
5857 3900 MT 5871 3900 LS
4075 
6291 3900 MT 6305 3900 LS
4076 
3045 3929 MT 3045 3929 LT 6298 3929 LT ST
4077 
3045 4010 MT 3045 4010 LT 6298 4010 LT ST
4078 
(0) 3059 3970 WT pop 0 originOffset 37 add RSS
4079 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) 3008 4153 WT TSE RSS
4080 
3254 4044 MT 3268 4044 LS
4081 
3688 4044 MT 3702 4044 LS
4082 
4122 4044 MT 4136 4044 LS
4083 
4556 4044 MT 4570 4044 LS
4084 
4989 4044 MT 5003 4044 LS
4085 
5423 4044 MT 5437 4044 LS
4086 
5857 4044 MT 5871 4044 LS
4087 
6291 4044 MT 6305 4044 LS
4088 
3045 4154 MT 6298 4154 LS
4089 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) 3008 4297 WT TSE RSS
4090 
3254 4188 MT 3268 4188 LS
4091 
3688 4188 MT 3702 4188 LS
4092 
4122 4188 MT 4136 4188 LS
4093 
4556 4188 MT 4570 4188 LS
4094 
4989 4188 MT 5003 4188 LS
4095 
5423 4188 MT 5437 4188 LS
4096 
5857 4188 MT 5871 4188 LS
4097 
6291 4188 MT 6305 4188 LS
4098 
3045 4217 MT 3045 4217 LT 6298 4217 LT ST
4099 
3045 4298 MT 3045 4298 LT 6298 4298 LT ST
4100 
(0) 3059 4258 WT pop 0 originOffset 37 add RSS
4101 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) 3008 4441 WT TSE RSS
4102 
3254 4332 MT 3268 4332 LS
4103 
3688 4332 MT 3702 4332 LS
4104 
4122 4332 MT 4136 4332 LS
4105 
4556 4332 MT 4570 4332 LS
4106 
4989 4332 MT 5003 4332 LS
4107 
5423 4332 MT 5437 4332 LS
4108 
5857 4332 MT 5871 4332 LS
4109 
6291 4332 MT 6305 4332 LS
4110 
3045 4361 MT 3045 4361 LT 6298 4361 LT ST
4111 
3045 4442 MT 3045 4442 LT 6298 4442 LT ST
4112 
(01) 3059 4402 WT pop 0 originOffset 37 add RSS
4113 
% draw footer
4114 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 4 Page: 7) 300 4799 WT TSW RSS
4115 
grestore
4116 
showpage
4117 
%%Page: 8 8
4118 
gsave
4119 
90 rotate 0.12 dup neg scale
4120 
% dump string table
4121 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
4122 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
4123 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
4124 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
4125 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
4126 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
4127 
/ARC {5 -2 roll SX 5 2 roll arc} def
4128 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3045 def/REdge 5699 def/LabelWidth 3008 def
4129 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
4130 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
4131 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/alu_op) MLW
4132 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_addrofs) MLW
4133 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_op) MLW
4134 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/branch_taken) MLW
4135 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/clk) MLW
4136 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/comp_op) MLW
4137 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_limm) MLW
4138 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/cust5_op) MLW
4139 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/du_hwbkpt) MLW
4140 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_freeze) MLW
4141 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_insn) MLW
4142 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_macrc_op) MLW
4143 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/ex_void) MLW
4144 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/except_illegal) MLW
4145 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/flushpipe) MLW
4146 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/force_dslot_fetch) MLW
4147 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_freeze) MLW
4148 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_insn) MLW
4149 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_macrc_op) MLW
4150 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/id_void) MLW
4151 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/if_insn) MLW
4152 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/imm_signextend) MLW
4153 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_addrofs) MLW
4154 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/lsu_op) MLW
4155 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/mac_op) MLW
4156 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/multicycle) MLW
4157 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/no_more_dslot) MLW
4158 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/pre_branch_op) MLW
4159 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addra) MLW
4160 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) MLW
4161 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) MLW
4162 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) MLW
4163 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) MLW
4164 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) MLW
4165 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) MLW
4166 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) MLW
4167 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) MLW
4168 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) MLW
4169 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) MLW
4170 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) MLW
4171 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) MLW
4172 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) MLW
4173 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) MLW
4174 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) MLW
4175 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) MLW
4176 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) MLW
4177 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) MLW
4178 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) MLW
4179 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) MLW
4180 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) MLW
4181 
% draw waveform shading
4182 
[] 0 SD
4183 
2.995 setlinewidth
4184 
 
4185 
 
4186 
 
4187 
3045 329 MT 3045 329 LT 6298 329 LT ST
4188 
3045 410 MT 3045 410 LT 6298 410 LT ST
4189 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
4190 
3045 473 MT 3045 473 LT 6298 473 LT ST
4191 
3045 554 MT 3045 554 LT 6298 554 LT ST
4192 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
4193 
3045 698 MT 6298 698 LS
4194 
3045 842 MT 6298 842 LS
4195 
3045 986 MT 6298 986 LS
4196 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
4197 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
4198 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
4199 
3045 1274 MT 6298 1274 LS
4200 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
4201 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
4202 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
4203 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
4204 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
4205 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
4206 
3045 1706 MT 6298 1706 LS
4207 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
4208 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
4209 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
4210 
3045 1994 MT 6298 1994 LS
4211 
3045 2098 MT 6298 2098 LS
4212 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
4213 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
4214 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
4215 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
4216 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
4217 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
4218 
3045 2489 MT 3045 2489 LT 3471 2489 LT 3478 2530 LT ST
4219 
3045 2570 MT 3045 2570 LT 3471 2570 LT 3478 2530 LT ST
4220 
(4) 3059 2530 WT pop 0 originOffset 37 add RSS
4221 
3478 2530 MT 3478 2530 LT 3485 2489 LT 3905 2489 LT 3912 2530 LT ST
4222 
3478 2530 MT 3478 2530 LT 3485 2570 LT 3905 2570 LT 3912 2530 LT ST
4223 
(5) 3492 2530 WT pop 0 originOffset 37 add RSS
4224 
3912 2530 MT 3912 2530 LT 3919 2489 LT 4339 2489 LT 4346 2530 LT ST
4225 
3912 2530 MT 3912 2530 LT 3919 2570 LT 4339 2570 LT 4346 2530 LT ST
4226 
(6) 3926 2530 WT pop 0 originOffset 37 add RSS
4227 
4346 2530 MT 4346 2530 LT 4353 2489 LT 4772 2489 LT 4779 2530 LT ST
4228 
4346 2530 MT 4346 2530 LT 4353 2570 LT 4772 2570 LT 4779 2530 LT ST
4229 
(7) 4360 2530 WT pop 0 originOffset 37 add RSS
4230 
4779 2530 MT 4779 2530 LT 4786 2489 LT 5206 2489 LT 5213 2530 LT ST
4231 
4779 2530 MT 4779 2530 LT 4786 2570 LT 5206 2570 LT 5213 2530 LT ST
4232 
(0) 4793 2530 WT pop 0 originOffset 37 add RSS
4233 
5213 2530 MT 5213 2530 LT 5220 2489 LT 5640 2489 LT 5647 2530 LT ST
4234 
5213 2530 MT 5213 2530 LT 5220 2570 LT 5640 2570 LT 5647 2530 LT ST
4235 
(1) 5227 2530 WT pop 0 originOffset 37 add RSS
4236 
5647 2530 MT 5647 2530 LT 5654 2489 LT 6074 2489 LT 6081 2530 LT ST
4237 
5647 2530 MT 5647 2530 LT 5654 2570 LT 6074 2570 LT 6081 2530 LT ST
4238 
(2) 5661 2530 WT pop 0 originOffset 37 add RSS
4239 
6081 2530 MT 6081 2530 LT 6088 2489 LT 6298 2489 LT ST
4240 
6081 2530 MT 6081 2530 LT 6088 2570 LT 6298 2570 LT ST
4241 
(3) 6095 2530 WT pop 0 originOffset 37 add RSS
4242 
3045 2633 MT 3045 2633 LT 3471 2633 LT 3478 2674 LT ST
4243 
3045 2714 MT 3045 2714 LT 3471 2714 LT 3478 2674 LT ST
4244 
(3) 3059 2674 WT pop 0 originOffset 37 add RSS
4245 
3478 2674 MT 3478 2674 LT 3485 2633 LT 3905 2633 LT 3912 2674 LT ST
4246 
3478 2674 MT 3478 2674 LT 3485 2714 LT 3905 2714 LT 3912 2674 LT ST
4247 
(4) 3492 2674 WT pop 0 originOffset 37 add RSS
4248 
3912 2674 MT 3912 2674 LT 3919 2633 LT 4339 2633 LT 4346 2674 LT ST
4249 
3912 2674 MT 3912 2674 LT 3919 2714 LT 4339 2714 LT 4346 2674 LT ST
4250 
(5) 3926 2674 WT pop 0 originOffset 37 add RSS
4251 
4346 2674 MT 4346 2674 LT 4353 2633 LT 4772 2633 LT 4779 2674 LT ST
4252 
4346 2674 MT 4346 2674 LT 4353 2714 LT 4772 2714 LT 4779 2674 LT ST
4253 
(6) 4360 2674 WT pop 0 originOffset 37 add RSS
4254 
4779 2674 MT 4779 2674 LT 4786 2633 LT 5206 2633 LT 5213 2674 LT ST
4255 
4779 2674 MT 4779 2674 LT 4786 2714 LT 5206 2714 LT 5213 2674 LT ST
4256 
(7) 4793 2674 WT pop 0 originOffset 37 add RSS
4257 
5213 2674 MT 5213 2674 LT 5220 2633 LT 5640 2633 LT 5647 2674 LT ST
4258 
5213 2674 MT 5213 2674 LT 5220 2714 LT 5640 2714 LT 5647 2674 LT ST
4259 
(0) 5227 2674 WT pop 0 originOffset 37 add RSS
4260 
5647 2674 MT 5647 2674 LT 5654 2633 LT 6074 2633 LT 6081 2674 LT ST
4261 
5647 2674 MT 5647 2674 LT 5654 2714 LT 6074 2714 LT 6081 2674 LT ST
4262 
(1) 5661 2674 WT pop 0 originOffset 37 add RSS
4263 
6081 2674 MT 6081 2674 LT 6088 2633 LT 6298 2633 LT ST
4264 
6081 2674 MT 6081 2674 LT 6088 2714 LT 6298 2714 LT ST
4265 
(2) 6095 2674 WT pop 0 originOffset 37 add RSS
4266 
3045 2858 MT 6298 2858 LS
4267 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
4268 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
4269 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
4270 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
4271 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
4272 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
4273 
3045 3290 MT 6298 3290 LS
4274 
% draw timeline
4275 
3088 4533 MT 3088 4570 LS
4276 
3132 4533 MT 3132 4570 LS
4277 
3175 4533 MT 3175 4570 LS
4278 
3218 4533 MT 3218 4570 LS
4279 
3304 4533 MT 3304 4570 LS
4280 
3348 4533 MT 3348 4570 LS
4281 
3391 4533 MT 3391 4570 LS
4282 
3434 4533 MT 3434 4570 LS
4283 
3478 4533 MT 3478 4570 LS
4284 
3521 4533 MT 3521 4570 LS
4285 
3565 4533 MT 3565 4570 LS
4286 
3608 4533 MT 3608 4570 LS
4287 
3651 4533 MT 3651 4570 LS
4288 
3261 4506 MT 3261 4570 LS
4289 
3738 4533 MT 3738 4570 LS
4290 
3782 4533 MT 3782 4570 LS
4291 
3825 4533 MT 3825 4570 LS
4292 
3868 4533 MT 3868 4570 LS
4293 
3912 4533 MT 3912 4570 LS
4294 
3955 4533 MT 3955 4570 LS
4295 
3999 4533 MT 3999 4570 LS
4296 
4042 4533 MT 4042 4570 LS
4297 
4085 4533 MT 4085 4570 LS
4298 
3695 4506 MT 3695 4570 LS
4299 
(240) 3695 4649 WT TS RSS
4300 
4172 4533 MT 4172 4570 LS
4301 
4216 4533 MT 4216 4570 LS
4302 
4259 4533 MT 4259 4570 LS
4303 
4302 4533 MT 4302 4570 LS
4304 
4346 4533 MT 4346 4570 LS
4305 
4389 4533 MT 4389 4570 LS
4306 
4433 4533 MT 4433 4570 LS
4307 
4476 4533 MT 4476 4570 LS
4308 
4519 4533 MT 4519 4570 LS
4309 
4129 4506 MT 4129 4570 LS
4310 
4606 4533 MT 4606 4570 LS
4311 
4650 4533 MT 4650 4570 LS
4312 
4693 4533 MT 4693 4570 LS
4313 
4736 4533 MT 4736 4570 LS
4314 
4780 4533 MT 4780 4570 LS
4315 
4823 4533 MT 4823 4570 LS
4316 
4867 4533 MT 4867 4570 LS
4317 
4910 4533 MT 4910 4570 LS
4318 
4953 4533 MT 4953 4570 LS
4319 
4563 4506 MT 4563 4570 LS
4320 
(260) 4563 4649 WT TS RSS
4321 
5039 4533 MT 5039 4570 LS
4322 
5083 4533 MT 5083 4570 LS
4323 
5126 4533 MT 5126 4570 LS
4324 
5169 4533 MT 5169 4570 LS
4325 
5213 4533 MT 5213 4570 LS
4326 
5256 4533 MT 5256 4570 LS
4327 
5300 4533 MT 5300 4570 LS
4328 
5343 4533 MT 5343 4570 LS
4329 
5386 4533 MT 5386 4570 LS
4330 
4996 4506 MT 4996 4570 LS
4331 
5473 4533 MT 5473 4570 LS
4332 
5517 4533 MT 5517 4570 LS
4333 
5560 4533 MT 5560 4570 LS
4334 
5603 4533 MT 5603 4570 LS
4335 
5647 4533 MT 5647 4570 LS
4336 
5690 4533 MT 5690 4570 LS
4337 
5734 4533 MT 5734 4570 LS
4338 
5777 4533 MT 5777 4570 LS
4339 
5820 4533 MT 5820 4570 LS
4340 
5430 4506 MT 5430 4570 LS
4341 
(280) 5430 4649 WT TS RSS
4342 
5907 4533 MT 5907 4570 LS
4343 
5951 4533 MT 5951 4570 LS
4344 
5994 4533 MT 5994 4570 LS
4345 
6037 4533 MT 6037 4570 LS
4346 
6081 4533 MT 6081 4570 LS
4347 
6124 4533 MT 6124 4570 LS
4348 
6168 4533 MT 6168 4570 LS
4349 
6211 4533 MT 6211 4570 LS
4350 
6254 4533 MT 6254 4570 LS
4351 
5864 4506 MT 5864 4570 LS
4352 
6341 4533 MT 6341 4570 LS
4353 
6385 4533 MT 6385 4570 LS
4354 
6428 4533 MT 6428 4570 LS
4355 
6471 4533 MT 6471 4570 LS
4356 
6515 4533 MT 6515 4570 LS
4357 
6558 4533 MT 6558 4570 LS
4358 
6602 4533 MT 6602 4570 LS
4359 
6645 4533 MT 6645 4570 LS
4360 
6688 4533 MT 6688 4570 LS
4361 
6298 4506 MT 6298 4570 LS
4362 
(300) 6298 4649 WT TS RSS
4363 
% draw grid
4364 
3261 300 MT 3261 4506 LS
4365 
3695 300 MT 3695 4506 LS
4366 
4129 300 MT 4129 4506 LS
4367 
4563 300 MT 4563 4506 LS
4368 
4996 300 MT 4996 4506 LS
4369 
5430 300 MT 5430 4506 LS
4370 
5864 300 MT 5864 4506 LS
4371 
6298 300 MT 6298 4506 LS
4372 
% draw waveforms
4373 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrb) 3008 409 WT TSE RSS
4374 
3254 300 MT 3268 300 LS
4375 
3688 300 MT 3702 300 LS
4376 
4122 300 MT 4136 300 LS
4377 
4556 300 MT 4570 300 LS
4378 
4989 300 MT 5003 300 LS
4379 
5423 300 MT 5437 300 LS
4380 
5857 300 MT 5871 300 LS
4381 
6291 300 MT 6305 300 LS
4382 
3045 329 MT 3045 329 LT 6298 329 LT ST
4383 
3045 410 MT 3045 410 LT 6298 410 LT ST
4384 
(00) 3059 370 WT pop 0 originOffset 37 add RSS
4385 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_addrw) 3008 553 WT TSE RSS
4386 
3254 444 MT 3268 444 LS
4387 
3688 444 MT 3702 444 LS
4388 
4122 444 MT 4136 444 LS
4389 
4556 444 MT 4570 444 LS
4390 
4989 444 MT 5003 444 LS
4391 
5423 444 MT 5437 444 LS
4392 
5857 444 MT 5871 444 LS
4393 
6291 444 MT 6305 444 LS
4394 
3045 473 MT 3045 473 LT 6298 473 LT ST
4395 
3045 554 MT 3045 554 LT 6298 554 LT ST
4396 
(03) 3059 514 WT pop 0 originOffset 37 add RSS
4397 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rda) 3008 697 WT TSE RSS
4398 
3254 588 MT 3268 588 LS
4399 
3688 588 MT 3702 588 LS
4400 
4122 588 MT 4136 588 LS
4401 
4556 588 MT 4570 588 LS
4402 
4989 588 MT 5003 588 LS
4403 
5423 588 MT 5437 588 LS
4404 
5857 588 MT 5871 588 LS
4405 
6291 588 MT 6305 588 LS
4406 
3045 698 MT 6298 698 LS
4407 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rf_rdb) 3008 841 WT TSE RSS
4408 
3254 732 MT 3268 732 LS
4409 
3688 732 MT 3702 732 LS
4410 
4122 732 MT 4136 732 LS
4411 
4556 732 MT 4570 732 LS
4412 
4989 732 MT 5003 732 LS
4413 
5423 732 MT 5437 732 LS
4414 
5857 732 MT 5871 732 LS
4415 
6291 732 MT 6305 732 LS
4416 
3045 842 MT 6298 842 LS
4417 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfe) 3008 985 WT TSE RSS
4418 
3254 876 MT 3268 876 LS
4419 
3688 876 MT 3702 876 LS
4420 
4122 876 MT 4136 876 LS
4421 
4556 876 MT 4570 876 LS
4422 
4989 876 MT 5003 876 LS
4423 
5423 876 MT 5437 876 LS
4424 
5857 876 MT 5871 876 LS
4425 
6291 876 MT 6305 876 LS
4426 
3045 986 MT 6298 986 LS
4427 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rfwb_op) 3008 1129 WT TSE RSS
4428 
3254 1020 MT 3268 1020 LS
4429 
3688 1020 MT 3702 1020 LS
4430 
4122 1020 MT 4136 1020 LS
4431 
4556 1020 MT 4570 1020 LS
4432 
4989 1020 MT 5003 1020 LS
4433 
5423 1020 MT 5437 1020 LS
4434 
5857 1020 MT 5871 1020 LS
4435 
6291 1020 MT 6305 1020 LS
4436 
3045 1049 MT 3045 1049 LT 6298 1049 LT ST
4437 
3045 1130 MT 3045 1130 LT 6298 1130 LT ST
4438 
(0) 3059 1090 WT pop 0 originOffset 37 add RSS
4439 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/rst) 3008 1273 WT TSE RSS
4440 
3254 1164 MT 3268 1164 LS
4441 
3688 1164 MT 3702 1164 LS
4442 
4122 1164 MT 4136 1164 LS
4443 
4556 1164 MT 4570 1164 LS
4444 
4989 1164 MT 5003 1164 LS
4445 
5423 1164 MT 5437 1164 LS
4446 
5857 1164 MT 5871 1164 LS
4447 
6291 1164 MT 6305 1164 LS
4448 
3045 1274 MT 6298 1274 LS
4449 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_a) 3008 1417 WT TSE RSS
4450 
3254 1308 MT 3268 1308 LS
4451 
3688 1308 MT 3702 1308 LS
4452 
4122 1308 MT 4136 1308 LS
4453 
4556 1308 MT 4570 1308 LS
4454 
4989 1308 MT 5003 1308 LS
4455 
5423 1308 MT 5437 1308 LS
4456 
5857 1308 MT 5871 1308 LS
4457 
6291 1308 MT 6305 1308 LS
4458 
3045 1337 MT 3045 1337 LT 6298 1337 LT ST
4459 
3045 1418 MT 3045 1418 LT 6298 1418 LT ST
4460 
(0) 3059 1378 WT pop 0 originOffset 37 add RSS
4461 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_b) 3008 1561 WT TSE RSS
4462 
3254 1452 MT 3268 1452 LS
4463 
3688 1452 MT 3702 1452 LS
4464 
4122 1452 MT 4136 1452 LS
4465 
4556 1452 MT 4570 1452 LS
4466 
4989 1452 MT 5003 1452 LS
4467 
5423 1452 MT 5437 1452 LS
4468 
5857 1452 MT 5871 1452 LS
4469 
6291 1452 MT 6305 1452 LS
4470 
3045 1481 MT 3045 1481 LT 6298 1481 LT ST
4471 
3045 1562 MT 3045 1562 LT 6298 1562 LT ST
4472 
(0) 3059 1522 WT pop 0 originOffset 37 add RSS
4473 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sel_imm) 3008 1705 WT TSE RSS
4474 
3254 1596 MT 3268 1596 LS
4475 
3688 1596 MT 3702 1596 LS
4476 
4122 1596 MT 4136 1596 LS
4477 
4556 1596 MT 4570 1596 LS
4478 
4989 1596 MT 5003 1596 LS
4479 
5423 1596 MT 5437 1596 LS
4480 
5857 1596 MT 5871 1596 LS
4481 
6291 1596 MT 6305 1596 LS
4482 
3045 1706 MT 6298 1706 LS
4483 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/shrot_op) 3008 1849 WT TSE RSS
4484 
3254 1740 MT 3268 1740 LS
4485 
3688 1740 MT 3702 1740 LS
4486 
4122 1740 MT 4136 1740 LS
4487 
4556 1740 MT 4570 1740 LS
4488 
4989 1740 MT 5003 1740 LS
4489 
5423 1740 MT 5437 1740 LS
4490 
5857 1740 MT 5871 1740 LS
4491 
6291 1740 MT 6305 1740 LS
4492 
3045 1769 MT 3045 1769 LT 6298 1769 LT ST
4493 
3045 1850 MT 3045 1850 LT 6298 1850 LT ST
4494 
(0) 3059 1810 WT pop 0 originOffset 37 add RSS
4495 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_syscall) 3008 1993 WT TSE RSS
4496 
3254 1884 MT 3268 1884 LS
4497 
3688 1884 MT 3702 1884 LS
4498 
4122 1884 MT 4136 1884 LS
4499 
4556 1884 MT 4570 1884 LS
4500 
4989 1884 MT 5003 1884 LS
4501 
5423 1884 MT 5437 1884 LS
4502 
5857 1884 MT 5871 1884 LS
4503 
6291 1884 MT 6305 1884 LS
4504 
3045 1994 MT 6298 1994 LS
4505 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/sig_trap) 3008 2137 WT TSE RSS
4506 
3254 2028 MT 3268 2028 LS
4507 
3688 2028 MT 3702 2028 LS
4508 
4122 2028 MT 4136 2028 LS
4509 
4556 2028 MT 4570 2028 LS
4510 
4989 2028 MT 5003 2028 LS
4511 
5423 2028 MT 5437 2028 LS
4512 
5857 2028 MT 5871 2028 LS
4513 
6291 2028 MT 6305 2028 LS
4514 
3045 2098 MT 6298 2098 LS
4515 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/simm) 3008 2281 WT TSE RSS
4516 
3254 2172 MT 3268 2172 LS
4517 
3688 2172 MT 3702 2172 LS
4518 
4122 2172 MT 4136 2172 LS
4519 
4556 2172 MT 4570 2172 LS
4520 
4989 2172 MT 5003 2172 LS
4521 
5423 2172 MT 5437 2172 LS
4522 
5857 2172 MT 5871 2172 LS
4523 
6291 2172 MT 6305 2172 LS
4524 
3045 2201 MT 3045 2201 LT 6298 2201 LT ST
4525 
3045 2282 MT 3045 2282 LT 6298 2282 LT ST
4526 
(00000000) 3059 2242 WT pop 0 originOffset 37 add RSS
4527 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/spr_addrimm) 3008 2425 WT TSE RSS
4528 
3254 2316 MT 3268 2316 LS
4529 
3688 2316 MT 3702 2316 LS
4530 
4122 2316 MT 4136 2316 LS
4531 
4556 2316 MT 4570 2316 LS
4532 
4989 2316 MT 5003 2316 LS
4533 
5423 2316 MT 5437 2316 LS
4534 
5857 2316 MT 5871 2316 LS
4535 
6291 2316 MT 6305 2316 LS
4536 
3045 2345 MT 3045 2345 LT 6298 2345 LT ST
4537 
3045 2426 MT 3045 2426 LT 6298 2426 LT ST
4538 
(1800) 3059 2386 WT pop 0 originOffset 37 add RSS
4539 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_in) 3008 2569 WT TSE RSS
4540 
3254 2460 MT 3268 2460 LS
4541 
3688 2460 MT 3702 2460 LS
4542 
4122 2460 MT 4136 2460 LS
4543 
4556 2460 MT 4570 2460 LS
4544 
4989 2460 MT 5003 2460 LS
4545 
5423 2460 MT 5437 2460 LS
4546 
5857 2460 MT 5871 2460 LS
4547 
6291 2460 MT 6305 2460 LS
4548 
3045 2489 MT 3045 2489 LT 3471 2489 LT 3478 2530 LT ST
4549 
3045 2570 MT 3045 2570 LT 3471 2570 LT 3478 2530 LT ST
4550 
(4) 3059 2530 WT pop 0 originOffset 37 add RSS
4551 
3478 2530 MT 3478 2530 LT 3485 2489 LT 3905 2489 LT 3912 2530 LT ST
4552 
3478 2530 MT 3478 2530 LT 3485 2570 LT 3905 2570 LT 3912 2530 LT ST
4553 
(5) 3492 2530 WT pop 0 originOffset 37 add RSS
4554 
3912 2530 MT 3912 2530 LT 3919 2489 LT 4339 2489 LT 4346 2530 LT ST
4555 
3912 2530 MT 3912 2530 LT 3919 2570 LT 4339 2570 LT 4346 2530 LT ST
4556 
(6) 3926 2530 WT pop 0 originOffset 37 add RSS
4557 
4346 2530 MT 4346 2530 LT 4353 2489 LT 4772 2489 LT 4779 2530 LT ST
4558 
4346 2530 MT 4346 2530 LT 4353 2570 LT 4772 2570 LT 4779 2530 LT ST
4559 
(7) 4360 2530 WT pop 0 originOffset 37 add RSS
4560 
4779 2530 MT 4779 2530 LT 4786 2489 LT 5206 2489 LT 5213 2530 LT ST
4561 
4779 2530 MT 4779 2530 LT 4786 2570 LT 5206 2570 LT 5213 2530 LT ST
4562 
(0) 4793 2530 WT pop 0 originOffset 37 add RSS
4563 
5213 2530 MT 5213 2530 LT 5220 2489 LT 5640 2489 LT 5647 2530 LT ST
4564 
5213 2530 MT 5213 2530 LT 5220 2570 LT 5640 2570 LT 5647 2530 LT ST
4565 
(1) 5227 2530 WT pop 0 originOffset 37 add RSS
4566 
5647 2530 MT 5647 2530 LT 5654 2489 LT 6074 2489 LT 6081 2530 LT ST
4567 
5647 2530 MT 5647 2530 LT 5654 2570 LT 6074 2570 LT 6081 2530 LT ST
4568 
(2) 5661 2530 WT pop 0 originOffset 37 add RSS
4569 
6081 2530 MT 6081 2530 LT 6088 2489 LT 6298 2489 LT ST
4570 
6081 2530 MT 6081 2530 LT 6088 2570 LT 6298 2570 LT ST
4571 
(3) 6095 2530 WT pop 0 originOffset 37 add RSS
4572 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/thread_out) 3008 2713 WT TSE RSS
4573 
3254 2604 MT 3268 2604 LS
4574 
3688 2604 MT 3702 2604 LS
4575 
4122 2604 MT 4136 2604 LS
4576 
4556 2604 MT 4570 2604 LS
4577 
4989 2604 MT 5003 2604 LS
4578 
5423 2604 MT 5437 2604 LS
4579 
5857 2604 MT 5871 2604 LS
4580 
6291 2604 MT 6305 2604 LS
4581 
3045 2633 MT 3045 2633 LT 3471 2633 LT 3478 2674 LT ST
4582 
3045 2714 MT 3045 2714 LT 3471 2714 LT 3478 2674 LT ST
4583 
(3) 3059 2674 WT pop 0 originOffset 37 add RSS
4584 
3478 2674 MT 3478 2674 LT 3485 2633 LT 3905 2633 LT 3912 2674 LT ST
4585 
3478 2674 MT 3478 2674 LT 3485 2714 LT 3905 2714 LT 3912 2674 LT ST
4586 
(4) 3492 2674 WT pop 0 originOffset 37 add RSS
4587 
3912 2674 MT 3912 2674 LT 3919 2633 LT 4339 2633 LT 4346 2674 LT ST
4588 
3912 2674 MT 3912 2674 LT 3919 2714 LT 4339 2714 LT 4346 2674 LT ST
4589 
(5) 3926 2674 WT pop 0 originOffset 37 add RSS
4590 
4346 2674 MT 4346 2674 LT 4353 2633 LT 4772 2633 LT 4779 2674 LT ST
4591 
4346 2674 MT 4346 2674 LT 4353 2714 LT 4772 2714 LT 4779 2674 LT ST
4592 
(6) 4360 2674 WT pop 0 originOffset 37 add RSS
4593 
4779 2674 MT 4779 2674 LT 4786 2633 LT 5206 2633 LT 5213 2674 LT ST
4594 
4779 2674 MT 4779 2674 LT 4786 2714 LT 5206 2714 LT 5213 2674 LT ST
4595 
(7) 4793 2674 WT pop 0 originOffset 37 add RSS
4596 
5213 2674 MT 5213 2674 LT 5220 2633 LT 5640 2633 LT 5647 2674 LT ST
4597 
5213 2674 MT 5213 2674 LT 5220 2714 LT 5640 2714 LT 5647 2674 LT ST
4598 
(0) 5227 2674 WT pop 0 originOffset 37 add RSS
4599 
5647 2674 MT 5647 2674 LT 5654 2633 LT 6074 2633 LT 6081 2674 LT ST
4600 
5647 2674 MT 5647 2674 LT 5654 2714 LT 6074 2714 LT 6081 2674 LT ST
4601 
(1) 5661 2674 WT pop 0 originOffset 37 add RSS
4602 
6081 2674 MT 6081 2674 LT 6088 2633 LT 6298 2633 LT ST
4603 
6081 2674 MT 6081 2674 LT 6088 2714 LT 6298 2714 LT ST
4604 
(2) 6095 2674 WT pop 0 originOffset 37 add RSS
4605 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_freeze) 3008 2857 WT TSE RSS
4606 
3254 2748 MT 3268 2748 LS
4607 
3688 2748 MT 3702 2748 LS
4608 
4122 2748 MT 4136 2748 LS
4609 
4556 2748 MT 4570 2748 LS
4610 
4989 2748 MT 5003 2748 LS
4611 
5423 2748 MT 5437 2748 LS
4612 
5857 2748 MT 5871 2748 LS
4613 
6291 2748 MT 6305 2748 LS
4614 
3045 2858 MT 6298 2858 LS
4615 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_insn) 3008 3001 WT TSE RSS
4616 
3254 2892 MT 3268 2892 LS
4617 
3688 2892 MT 3702 2892 LS
4618 
4122 2892 MT 4136 2892 LS
4619 
4556 2892 MT 4570 2892 LS
4620 
4989 2892 MT 5003 2892 LS
4621 
5423 2892 MT 5437 2892 LS
4622 
5857 2892 MT 5871 2892 LS
4623 
6291 2892 MT 6305 2892 LS
4624 
3045 2921 MT 3045 2921 LT 6298 2921 LT ST
4625 
3045 3002 MT 3045 3002 LT 6298 3002 LT ST
4626 
(14610000) 3059 2962 WT pop 0 originOffset 37 add RSS
4627 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wb_rfaddrw) 3008 3145 WT TSE RSS
4628 
3254 3036 MT 3268 3036 LS
4629 
3688 3036 MT 3702 3036 LS
4630 
4122 3036 MT 4136 3036 LS
4631 
4556 3036 MT 4570 3036 LS
4632 
4989 3036 MT 5003 3036 LS
4633 
5423 3036 MT 5437 3036 LS
4634 
5857 3036 MT 5871 3036 LS
4635 
6291 3036 MT 6305 3036 LS
4636 
3045 3065 MT 3045 3065 LT 6298 3065 LT ST
4637 
3045 3146 MT 3045 3146 LT 6298 3146 LT ST
4638 
(03) 3059 3106 WT pop 0 originOffset 37 add RSS
4639 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl/wbforw_valid) 3008 3289 WT TSE RSS
4640 
3254 3180 MT 3268 3180 LS
4641 
3688 3180 MT 3702 3180 LS
4642 
4122 3180 MT 4136 3180 LS
4643 
4556 3180 MT 4570 3180 LS
4644 
4989 3180 MT 5003 3180 LS
4645 
5423 3180 MT 5437 3180 LS
4646 
5857 3180 MT 5871 3180 LS
4647 
6291 3180 MT 6305 3180 LS
4648 
3045 3290 MT 6298 3290 LS
4649 
% draw footer
4650 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:23:51 EDT 2004   Row: 4 Page: 8) 300 4799 WT TSW RSS
4651 
grestore
4652 
showpage
4653 
%%EOF

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.