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[/] [claw/] [trunk/] [or1200_cpu/] [Wave_Forms_For_The_Whole_Thing/] [ctrl2_module.ps] - Blame information for rev 4

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1 2 conte 
%!PS-Adobe-3.0
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%%Creator: Model Technology ModelSim SE vsim 5.7e Simulator 2003.07 Jul  8 2003
3 
%%Title: /afs/eos.ncsu.edu/service/ece/research/tinker/bviyer/vol1/OR_1200_Multithreading_Implementation/verilog_with_my_changes/or1200_cpu/Wave_Forms_For_The_Whole_Thing/ctrl2_module.ps
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%%CreationDate: 2004-08-14 12:33:37 AM
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%%DocumentData: Clean8Bit
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%%DocumentNeededResources: font Helvetica
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%%Orientation: Landscape
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%%PageOrder: ascend
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%%Pages: 8
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%%EndComments
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%%Page: 1 1
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gsave
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90 rotate 0.12 dup neg scale
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% dump string table
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/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
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/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
17 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
18 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
19 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
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/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
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/ARC {5 -2 roll SX 5 2 roll arc} def
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/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
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/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
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/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
46 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
47 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
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% draw waveform shading
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[] 0 SD
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2.995 setlinewidth
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79 
 
80 
 
81 
3103 370 MT 3955 370 LS
82 
3955 370 MT 3955 410 LS
83 
3955 410 MT 4168 410 LS
84 
4168 410 MT 4168 370 LS
85 
4168 370 MT 6298 370 LS
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3103 514 MT 3103 554 LS
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3103 554 MT 6298 554 LS
88 
3103 658 MT 3955 658 LS
89 
3955 658 MT 3955 698 LS
90 
3955 698 MT 6298 698 LS
91 
3103 802 MT 3316 802 LS
92 
3316 802 MT 3316 802 LT 3323 761 LT 4161 761 LT 4168 802 LT ST
93 
3316 802 MT 3316 802 LT 3323 842 LT 4161 842 LT 4168 802 LT ST
94 
(14410000) 3330 802 WT pop 0 originOffset 37 add RSS
95 
4168 802 MT 4168 802 LT 4175 761 LT 6298 761 LT ST
96 
4168 802 MT 4168 802 LT 4175 842 LT 6298 842 LT ST
97 
(14610000) 4182 802 WT pop 0 originOffset 37 add RSS
98 
3103 946 MT 3316 946 LS
99 
3316 946 MT 3316 986 LS
100 
3316 986 MT 6298 986 LS
101 
3103 1090 MT 3316 1090 LS
102 
3316 1090 MT 3316 1050 LS
103 
3316 1050 MT 6298 1050 LS
104 
3103 1234 MT 3955 1234 LS
105 
3955 1234 MT 3955 1234 LT 3962 1193 LT 6298 1193 LT ST
106 
3955 1234 MT 3955 1234 LT 3962 1274 LT 6298 1274 LT ST
107 
(14610000) 3969 1234 WT pop 0 originOffset 37 add RSS
108 
3103 1378 MT 3316 1378 LS
109 
3316 1378 MT 3316 1418 LS
110 
3316 1418 MT 6298 1418 LS
111 
3103 1522 MT 3316 1522 LS
112 
3316 1522 MT 3316 1522 LT 3323 1481 LT 6298 1481 LT ST
113 
3316 1522 MT 3316 1522 LT 3323 1562 LT 6298 1562 LT ST
114 
(00000000) 3330 1522 WT pop 0 originOffset 37 add RSS
115 
3103 1666 MT 3316 1666 LS
116 
3316 1666 MT 3316 1666 LT 3323 1625 LT 6298 1625 LT ST
117 
3316 1666 MT 3316 1666 LT 3323 1706 LT 6298 1706 LT ST
118 
(0) 3330 1666 WT pop 0 originOffset 37 add RSS
119 
3103 1810 MT 3316 1810 LS
120 
3316 1810 MT 3316 1810 LT 3323 1769 LT 6298 1769 LT ST
121 
3316 1810 MT 3316 1810 LT 3323 1850 LT 6298 1850 LT ST
122 
(0) 3330 1810 WT pop 0 originOffset 37 add RSS
123 
3103 1954 MT 3316 1954 LS
124 
3316 1954 MT 3316 1954 LT 3323 1913 LT 6298 1913 LT ST
125 
3316 1954 MT 3316 1954 LT 3323 1994 LT 6298 1994 LT ST
126 
(0) 3330 1954 WT pop 0 originOffset 37 add RSS
127 
3103 2098 MT 3316 2098 LS
128 
3316 2098 MT 3316 2138 LS
129 
3316 2138 MT 6298 2138 LS
130 
3103 2242 MT 3316 2242 LS
131 
3316 2242 MT 3316 2242 LT 3323 2201 LT 6298 2201 LT ST
132 
3316 2242 MT 3316 2242 LT 3323 2282 LT 6298 2282 LT ST
133 
(0) 3330 2242 WT pop 0 originOffset 37 add RSS
134 
3103 2386 MT 3955 2386 LS
135 
3955 2386 MT 3955 2386 LT 3962 2345 LT 6298 2345 LT ST
136 
3955 2386 MT 3955 2386 LT 3962 2426 LT 6298 2426 LT ST
137 
(01) 3969 2386 WT pop 0 originOffset 37 add RSS
138 
3103 2530 MT 3955 2530 LS
139 
3955 2530 MT 3955 2530 LT 3962 2489 LT 6298 2489 LT ST
140 
3955 2530 MT 3955 2530 LT 3962 2570 LT 6298 2570 LT ST
141 
(00) 3969 2530 WT pop 0 originOffset 37 add RSS
142 
3103 2674 MT 3316 2674 LS
143 
3316 2674 MT 3316 2674 LT 3323 2633 LT 4161 2633 LT 4168 2674 LT ST
144 
3316 2674 MT 3316 2674 LT 3323 2714 LT 4161 2714 LT 4168 2674 LT ST
145 
(00) 3330 2674 WT pop 0 originOffset 37 add RSS
146 
4168 2674 MT 4168 2674 LT 4175 2633 LT 4587 2633 LT 4594 2674 LT ST
147 
4168 2674 MT 4168 2674 LT 4175 2714 LT 4587 2714 LT 4594 2674 LT ST
148 
(02) 4182 2674 WT pop 0 originOffset 37 add RSS
149 
4594 2674 MT 4594 2674 LT 4601 2633 LT 6298 2633 LT ST
150 
4594 2674 MT 4594 2674 LT 4601 2714 LT 6298 2714 LT ST
151 
(03) 4608 2674 WT pop 0 originOffset 37 add RSS
152 
3103 2818 MT 3955 2818 LS
153 
3955 2818 MT 3955 2858 LS
154 
3955 2858 MT 6298 2858 LS
155 
3103 2962 MT 3955 2962 LS
156 
3955 2962 MT 3955 3002 LS
157 
3955 3002 MT 6298 3002 LS
158 
3103 3106 MT 3316 3106 LS
159 
3316 3106 MT 3316 3146 LS
160 
3316 3146 MT 6298 3146 LS
161 
3103 3250 MT 3316 3250 LS
162 
3316 3250 MT 3316 3250 LT 3323 3209 LT 6298 3209 LT ST
163 
3316 3250 MT 3316 3250 LT 3323 3290 LT 6298 3290 LT ST
164 
(0) 3330 3250 WT pop 0 originOffset 37 add RSS
165 
3103 3394 MT 3103 3434 LS
166 
3103 3434 MT 3316 3434 LS
167 
3316 3434 MT 3316 3354 LS
168 
3316 3354 MT 3529 3354 LS
169 
3529 3354 MT 3529 3434 LS
170 
3529 3434 MT 6298 3434 LS
171 
3103 3538 MT 3316 3538 LS
172 
3316 3538 MT 3316 3538 LT 3323 3497 LT 6298 3497 LT ST
173 
3316 3538 MT 3316 3538 LT 3323 3578 LT 6298 3578 LT ST
174 
(0) 3330 3538 WT pop 0 originOffset 37 add RSS
175 
3103 3682 MT 3316 3682 LS
176 
3316 3682 MT 3316 3682 LT 3323 3641 LT 6298 3641 LT ST
177 
3316 3682 MT 3316 3682 LT 3323 3722 LT 6298 3722 LT ST
178 
(0) 3330 3682 WT pop 0 originOffset 37 add RSS
179 
3103 3826 MT 3316 3826 LS
180 
3316 3826 MT 3316 3866 LS
181 
3316 3866 MT 6298 3866 LS
182 
3103 3970 MT 3316 3970 LS
183 
3316 3970 MT 3316 3970 LT 3323 3929 LT 6298 3929 LT ST
184 
3316 3970 MT 3316 3970 LT 3323 4010 LT 6298 4010 LT ST
185 
(0) 3330 3970 WT pop 0 originOffset 37 add RSS
186 
3103 4114 MT 3316 4114 LS
187 
3316 4114 MT 3316 4154 LS
188 
3316 4154 MT 6298 4154 LS
189 
3103 4258 MT 3316 4258 LS
190 
3316 4258 MT 3316 4298 LS
191 
3316 4298 MT 4168 4298 LS
192 
4168 4298 MT 4168 4258 LS
193 
4168 4258 MT 6298 4258 LS
194 
3103 4402 MT 3316 4402 LS
195 
3316 4402 MT 3316 4402 LT 3323 4361 LT 6298 4361 LT ST
196 
3316 4402 MT 3316 4402 LT 3323 4442 LT 6298 4442 LT ST
197 
(00000000) 3330 4402 WT pop 0 originOffset 37 add RSS
198 
% draw timeline
199 
3146 4533 MT 3146 4570 LS
200 
3188 4533 MT 3188 4570 LS
201 
3231 4533 MT 3231 4570 LS
202 
3273 4533 MT 3273 4570 LS
203 
3316 4533 MT 3316 4570 LS
204 
3359 4533 MT 3359 4570 LS
205 
3401 4533 MT 3401 4570 LS
206 
3444 4533 MT 3444 4570 LS
207 
3486 4533 MT 3486 4570 LS
208 
(0) 3103 4649 WT TS RSS
209 
3572 4533 MT 3572 4570 LS
210 
3614 4533 MT 3614 4570 LS
211 
3657 4533 MT 3657 4570 LS
212 
3699 4533 MT 3699 4570 LS
213 
3742 4533 MT 3742 4570 LS
214 
3785 4533 MT 3785 4570 LS
215 
3827 4533 MT 3827 4570 LS
216 
3870 4533 MT 3870 4570 LS
217 
3912 4533 MT 3912 4570 LS
218 
3529 4506 MT 3529 4570 LS
219 
3998 4533 MT 3998 4570 LS
220 
4040 4533 MT 4040 4570 LS
221 
4083 4533 MT 4083 4570 LS
222 
4125 4533 MT 4125 4570 LS
223 
4168 4533 MT 4168 4570 LS
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4211 4533 MT 4211 4570 LS
225 
4253 4533 MT 4253 4570 LS
226 
4296 4533 MT 4296 4570 LS
227 
4338 4533 MT 4338 4570 LS
228 
3955 4506 MT 3955 4570 LS
229 
(20) 3955 4649 WT TS RSS
230 
4424 4533 MT 4424 4570 LS
231 
4466 4533 MT 4466 4570 LS
232 
4509 4533 MT 4509 4570 LS
233 
4551 4533 MT 4551 4570 LS
234 
4594 4533 MT 4594 4570 LS
235 
4637 4533 MT 4637 4570 LS
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4679 4533 MT 4679 4570 LS
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4722 4533 MT 4722 4570 LS
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4764 4533 MT 4764 4570 LS
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4381 4506 MT 4381 4570 LS
240 
4850 4533 MT 4850 4570 LS
241 
4892 4533 MT 4892 4570 LS
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4935 4533 MT 4935 4570 LS
243 
4977 4533 MT 4977 4570 LS
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5020 4533 MT 5020 4570 LS
245 
5063 4533 MT 5063 4570 LS
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5105 4533 MT 5105 4570 LS
247 
5148 4533 MT 5148 4570 LS
248 
5190 4533 MT 5190 4570 LS
249 
4807 4506 MT 4807 4570 LS
250 
(40) 4807 4649 WT TS RSS
251 
5276 4533 MT 5276 4570 LS
252 
5318 4533 MT 5318 4570 LS
253 
5361 4533 MT 5361 4570 LS
254 
5403 4533 MT 5403 4570 LS
255 
5446 4533 MT 5446 4570 LS
256 
5489 4533 MT 5489 4570 LS
257 
5531 4533 MT 5531 4570 LS
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5574 4533 MT 5574 4570 LS
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5616 4533 MT 5616 4570 LS
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5233 4506 MT 5233 4570 LS
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5702 4533 MT 5702 4570 LS
262 
5744 4533 MT 5744 4570 LS
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5787 4533 MT 5787 4570 LS
264 
5829 4533 MT 5829 4570 LS
265 
5872 4533 MT 5872 4570 LS
266 
5915 4533 MT 5915 4570 LS
267 
5957 4533 MT 5957 4570 LS
268 
6000 4533 MT 6000 4570 LS
269 
6042 4533 MT 6042 4570 LS
270 
5659 4506 MT 5659 4570 LS
271 
(60) 5659 4649 WT TS RSS
272 
6128 4533 MT 6128 4570 LS
273 
6170 4533 MT 6170 4570 LS
274 
6213 4533 MT 6213 4570 LS
275 
6255 4533 MT 6255 4570 LS
276 
6298 4533 MT 6298 4570 LS
277 
6341 4533 MT 6341 4570 LS
278 
6383 4533 MT 6383 4570 LS
279 
6426 4533 MT 6426 4570 LS
280 
6468 4533 MT 6468 4570 LS
281 
6085 4506 MT 6085 4570 LS
282 
% draw grid
283 
3529 300 MT 3529 4506 LS
284 
3955 300 MT 3955 4506 LS
285 
4381 300 MT 4381 4506 LS
286 
4807 300 MT 4807 4506 LS
287 
5233 300 MT 5233 4506 LS
288 
5659 300 MT 5659 4506 LS
289 
6085 300 MT 6085 4506 LS
290 
% draw waveforms
291 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) 3066 409 WT TSE RSS
292 
3522 300 MT 3536 300 LS
293 
3948 300 MT 3962 300 LS
294 
4374 300 MT 4388 300 LS
295 
4800 300 MT 4814 300 LS
296 
5226 300 MT 5240 300 LS
297 
5652 300 MT 5666 300 LS
298 
6078 300 MT 6092 300 LS
299 
3103 370 MT 3955 370 LS
300 
3955 370 MT 3955 410 LS
301 
3955 410 MT 4168 410 LS
302 
4168 410 MT 4168 370 LS
303 
4168 370 MT 6298 370 LS
304 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) 3066 553 WT TSE RSS
305 
3522 444 MT 3536 444 LS
306 
3948 444 MT 3962 444 LS
307 
4374 444 MT 4388 444 LS
308 
4800 444 MT 4814 444 LS
309 
5226 444 MT 5240 444 LS
310 
5652 444 MT 5666 444 LS
311 
6078 444 MT 6092 444 LS
312 
3103 514 MT 3103 554 LS
313 
3103 554 MT 6298 554 LS
314 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) 3066 697 WT TSE RSS
315 
3522 588 MT 3536 588 LS
316 
3948 588 MT 3962 588 LS
317 
4374 588 MT 4388 588 LS
318 
4800 588 MT 4814 588 LS
319 
5226 588 MT 5240 588 LS
320 
5652 588 MT 5666 588 LS
321 
6078 588 MT 6092 588 LS
322 
3103 658 MT 3955 658 LS
323 
3955 658 MT 3955 698 LS
324 
3955 698 MT 6298 698 LS
325 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) 3066 841 WT TSE RSS
326 
3522 732 MT 3536 732 LS
327 
3948 732 MT 3962 732 LS
328 
4374 732 MT 4388 732 LS
329 
4800 732 MT 4814 732 LS
330 
5226 732 MT 5240 732 LS
331 
5652 732 MT 5666 732 LS
332 
6078 732 MT 6092 732 LS
333 
3103 802 MT 3316 802 LS
334 
3316 802 MT 3316 802 LT 3323 761 LT 4161 761 LT 4168 802 LT ST
335 
3316 802 MT 3316 802 LT 3323 842 LT 4161 842 LT 4168 802 LT ST
336 
(14410000) 3330 802 WT pop 0 originOffset 37 add RSS
337 
4168 802 MT 4168 802 LT 4175 761 LT 6298 761 LT ST
338 
4168 802 MT 4168 802 LT 4175 842 LT 6298 842 LT ST
339 
(14610000) 4182 802 WT pop 0 originOffset 37 add RSS
340 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) 3066 985 WT TSE RSS
341 
3522 876 MT 3536 876 LS
342 
3948 876 MT 3962 876 LS
343 
4374 876 MT 4388 876 LS
344 
4800 876 MT 4814 876 LS
345 
5226 876 MT 5240 876 LS
346 
5652 876 MT 5666 876 LS
347 
6078 876 MT 6092 876 LS
348 
3103 946 MT 3316 946 LS
349 
3316 946 MT 3316 986 LS
350 
3316 986 MT 6298 986 LS
351 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) 3066 1129 WT TSE RSS
352 
3522 1020 MT 3536 1020 LS
353 
3948 1020 MT 3962 1020 LS
354 
4374 1020 MT 4388 1020 LS
355 
4800 1020 MT 4814 1020 LS
356 
5226 1020 MT 5240 1020 LS
357 
5652 1020 MT 5666 1020 LS
358 
6078 1020 MT 6092 1020 LS
359 
3103 1090 MT 3316 1090 LS
360 
3316 1090 MT 3316 1050 LS
361 
3316 1050 MT 6298 1050 LS
362 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) 3066 1273 WT TSE RSS
363 
3522 1164 MT 3536 1164 LS
364 
3948 1164 MT 3962 1164 LS
365 
4374 1164 MT 4388 1164 LS
366 
4800 1164 MT 4814 1164 LS
367 
5226 1164 MT 5240 1164 LS
368 
5652 1164 MT 5666 1164 LS
369 
6078 1164 MT 6092 1164 LS
370 
3103 1234 MT 3955 1234 LS
371 
3955 1234 MT 3955 1234 LT 3962 1193 LT 6298 1193 LT ST
372 
3955 1234 MT 3955 1234 LT 3962 1274 LT 6298 1274 LT ST
373 
(14610000) 3969 1234 WT pop 0 originOffset 37 add RSS
374 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) 3066 1417 WT TSE RSS
375 
3522 1308 MT 3536 1308 LS
376 
3948 1308 MT 3962 1308 LS
377 
4374 1308 MT 4388 1308 LS
378 
4800 1308 MT 4814 1308 LS
379 
5226 1308 MT 5240 1308 LS
380 
5652 1308 MT 5666 1308 LS
381 
6078 1308 MT 6092 1308 LS
382 
3103 1378 MT 3316 1378 LS
383 
3316 1378 MT 3316 1418 LS
384 
3316 1418 MT 6298 1418 LS
385 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) 3066 1561 WT TSE RSS
386 
3522 1452 MT 3536 1452 LS
387 
3948 1452 MT 3962 1452 LS
388 
4374 1452 MT 4388 1452 LS
389 
4800 1452 MT 4814 1452 LS
390 
5226 1452 MT 5240 1452 LS
391 
5652 1452 MT 5666 1452 LS
392 
6078 1452 MT 6092 1452 LS
393 
3103 1522 MT 3316 1522 LS
394 
3316 1522 MT 3316 1522 LT 3323 1481 LT 6298 1481 LT ST
395 
3316 1522 MT 3316 1522 LT 3323 1562 LT 6298 1562 LT ST
396 
(00000000) 3330 1522 WT pop 0 originOffset 37 add RSS
397 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) 3066 1705 WT TSE RSS
398 
3522 1596 MT 3536 1596 LS
399 
3948 1596 MT 3962 1596 LS
400 
4374 1596 MT 4388 1596 LS
401 
4800 1596 MT 4814 1596 LS
402 
5226 1596 MT 5240 1596 LS
403 
5652 1596 MT 5666 1596 LS
404 
6078 1596 MT 6092 1596 LS
405 
3103 1666 MT 3316 1666 LS
406 
3316 1666 MT 3316 1666 LT 3323 1625 LT 6298 1625 LT ST
407 
3316 1666 MT 3316 1666 LT 3323 1706 LT 6298 1706 LT ST
408 
(0) 3330 1666 WT pop 0 originOffset 37 add RSS
409 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) 3066 1849 WT TSE RSS
410 
3522 1740 MT 3536 1740 LS
411 
3948 1740 MT 3962 1740 LS
412 
4374 1740 MT 4388 1740 LS
413 
4800 1740 MT 4814 1740 LS
414 
5226 1740 MT 5240 1740 LS
415 
5652 1740 MT 5666 1740 LS
416 
6078 1740 MT 6092 1740 LS
417 
3103 1810 MT 3316 1810 LS
418 
3316 1810 MT 3316 1810 LT 3323 1769 LT 6298 1769 LT ST
419 
3316 1810 MT 3316 1810 LT 3323 1850 LT 6298 1850 LT ST
420 
(0) 3330 1810 WT pop 0 originOffset 37 add RSS
421 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) 3066 1993 WT TSE RSS
422 
3522 1884 MT 3536 1884 LS
423 
3948 1884 MT 3962 1884 LS
424 
4374 1884 MT 4388 1884 LS
425 
4800 1884 MT 4814 1884 LS
426 
5226 1884 MT 5240 1884 LS
427 
5652 1884 MT 5666 1884 LS
428 
6078 1884 MT 6092 1884 LS
429 
3103 1954 MT 3316 1954 LS
430 
3316 1954 MT 3316 1954 LT 3323 1913 LT 6298 1913 LT ST
431 
3316 1954 MT 3316 1954 LT 3323 1994 LT 6298 1994 LT ST
432 
(0) 3330 1954 WT pop 0 originOffset 37 add RSS
433 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) 3066 2137 WT TSE RSS
434 
3522 2028 MT 3536 2028 LS
435 
3948 2028 MT 3962 2028 LS
436 
4374 2028 MT 4388 2028 LS
437 
4800 2028 MT 4814 2028 LS
438 
5226 2028 MT 5240 2028 LS
439 
5652 2028 MT 5666 2028 LS
440 
6078 2028 MT 6092 2028 LS
441 
3103 2098 MT 3316 2098 LS
442 
3316 2098 MT 3316 2138 LS
443 
3316 2138 MT 6298 2138 LS
444 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) 3066 2281 WT TSE RSS
445 
3522 2172 MT 3536 2172 LS
446 
3948 2172 MT 3962 2172 LS
447 
4374 2172 MT 4388 2172 LS
448 
4800 2172 MT 4814 2172 LS
449 
5226 2172 MT 5240 2172 LS
450 
5652 2172 MT 5666 2172 LS
451 
6078 2172 MT 6092 2172 LS
452 
3103 2242 MT 3316 2242 LS
453 
3316 2242 MT 3316 2242 LT 3323 2201 LT 6298 2201 LT ST
454 
3316 2242 MT 3316 2242 LT 3323 2282 LT 6298 2282 LT ST
455 
(0) 3330 2242 WT pop 0 originOffset 37 add RSS
456 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) 3066 2425 WT TSE RSS
457 
3522 2316 MT 3536 2316 LS
458 
3948 2316 MT 3962 2316 LS
459 
4374 2316 MT 4388 2316 LS
460 
4800 2316 MT 4814 2316 LS
461 
5226 2316 MT 5240 2316 LS
462 
5652 2316 MT 5666 2316 LS
463 
6078 2316 MT 6092 2316 LS
464 
3103 2386 MT 3955 2386 LS
465 
3955 2386 MT 3955 2386 LT 3962 2345 LT 6298 2345 LT ST
466 
3955 2386 MT 3955 2386 LT 3962 2426 LT 6298 2426 LT ST
467 
(01) 3969 2386 WT pop 0 originOffset 37 add RSS
468 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) 3066 2569 WT TSE RSS
469 
3522 2460 MT 3536 2460 LS
470 
3948 2460 MT 3962 2460 LS
471 
4374 2460 MT 4388 2460 LS
472 
4800 2460 MT 4814 2460 LS
473 
5226 2460 MT 5240 2460 LS
474 
5652 2460 MT 5666 2460 LS
475 
6078 2460 MT 6092 2460 LS
476 
3103 2530 MT 3955 2530 LS
477 
3955 2530 MT 3955 2530 LT 3962 2489 LT 6298 2489 LT ST
478 
3955 2530 MT 3955 2530 LT 3962 2570 LT 6298 2570 LT ST
479 
(00) 3969 2530 WT pop 0 originOffset 37 add RSS
480 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) 3066 2713 WT TSE RSS
481 
3522 2604 MT 3536 2604 LS
482 
3948 2604 MT 3962 2604 LS
483 
4374 2604 MT 4388 2604 LS
484 
4800 2604 MT 4814 2604 LS
485 
5226 2604 MT 5240 2604 LS
486 
5652 2604 MT 5666 2604 LS
487 
6078 2604 MT 6092 2604 LS
488 
3103 2674 MT 3316 2674 LS
489 
3316 2674 MT 3316 2674 LT 3323 2633 LT 4161 2633 LT 4168 2674 LT ST
490 
3316 2674 MT 3316 2674 LT 3323 2714 LT 4161 2714 LT 4168 2674 LT ST
491 
(00) 3330 2674 WT pop 0 originOffset 37 add RSS
492 
4168 2674 MT 4168 2674 LT 4175 2633 LT 4587 2633 LT 4594 2674 LT ST
493 
4168 2674 MT 4168 2674 LT 4175 2714 LT 4587 2714 LT 4594 2674 LT ST
494 
(02) 4182 2674 WT pop 0 originOffset 37 add RSS
495 
4594 2674 MT 4594 2674 LT 4601 2633 LT 6298 2633 LT ST
496 
4594 2674 MT 4594 2674 LT 4601 2714 LT 6298 2714 LT ST
497 
(03) 4608 2674 WT pop 0 originOffset 37 add RSS
498 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) 3066 2857 WT TSE RSS
499 
3522 2748 MT 3536 2748 LS
500 
3948 2748 MT 3962 2748 LS
501 
4374 2748 MT 4388 2748 LS
502 
4800 2748 MT 4814 2748 LS
503 
5226 2748 MT 5240 2748 LS
504 
5652 2748 MT 5666 2748 LS
505 
6078 2748 MT 6092 2748 LS
506 
3103 2818 MT 3955 2818 LS
507 
3955 2818 MT 3955 2858 LS
508 
3955 2858 MT 6298 2858 LS
509 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) 3066 3001 WT TSE RSS
510 
3522 2892 MT 3536 2892 LS
511 
3948 2892 MT 3962 2892 LS
512 
4374 2892 MT 4388 2892 LS
513 
4800 2892 MT 4814 2892 LS
514 
5226 2892 MT 5240 2892 LS
515 
5652 2892 MT 5666 2892 LS
516 
6078 2892 MT 6092 2892 LS
517 
3103 2962 MT 3955 2962 LS
518 
3955 2962 MT 3955 3002 LS
519 
3955 3002 MT 6298 3002 LS
520 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) 3066 3145 WT TSE RSS
521 
3522 3036 MT 3536 3036 LS
522 
3948 3036 MT 3962 3036 LS
523 
4374 3036 MT 4388 3036 LS
524 
4800 3036 MT 4814 3036 LS
525 
5226 3036 MT 5240 3036 LS
526 
5652 3036 MT 5666 3036 LS
527 
6078 3036 MT 6092 3036 LS
528 
3103 3106 MT 3316 3106 LS
529 
3316 3106 MT 3316 3146 LS
530 
3316 3146 MT 6298 3146 LS
531 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) 3066 3289 WT TSE RSS
532 
3522 3180 MT 3536 3180 LS
533 
3948 3180 MT 3962 3180 LS
534 
4374 3180 MT 4388 3180 LS
535 
4800 3180 MT 4814 3180 LS
536 
5226 3180 MT 5240 3180 LS
537 
5652 3180 MT 5666 3180 LS
538 
6078 3180 MT 6092 3180 LS
539 
3103 3250 MT 3316 3250 LS
540 
3316 3250 MT 3316 3250 LT 3323 3209 LT 6298 3209 LT ST
541 
3316 3250 MT 3316 3250 LT 3323 3290 LT 6298 3290 LT ST
542 
(0) 3330 3250 WT pop 0 originOffset 37 add RSS
543 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) 3066 3433 WT TSE RSS
544 
3522 3324 MT 3536 3324 LS
545 
3948 3324 MT 3962 3324 LS
546 
4374 3324 MT 4388 3324 LS
547 
4800 3324 MT 4814 3324 LS
548 
5226 3324 MT 5240 3324 LS
549 
5652 3324 MT 5666 3324 LS
550 
6078 3324 MT 6092 3324 LS
551 
3103 3394 MT 3103 3434 LS
552 
3103 3434 MT 3316 3434 LS
553 
3316 3434 MT 3316 3354 LS
554 
3316 3354 MT 3529 3354 LS
555 
3529 3354 MT 3529 3434 LS
556 
3529 3434 MT 6298 3434 LS
557 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) 3066 3577 WT TSE RSS
558 
3522 3468 MT 3536 3468 LS
559 
3948 3468 MT 3962 3468 LS
560 
4374 3468 MT 4388 3468 LS
561 
4800 3468 MT 4814 3468 LS
562 
5226 3468 MT 5240 3468 LS
563 
5652 3468 MT 5666 3468 LS
564 
6078 3468 MT 6092 3468 LS
565 
3103 3538 MT 3316 3538 LS
566 
3316 3538 MT 3316 3538 LT 3323 3497 LT 6298 3497 LT ST
567 
3316 3538 MT 3316 3538 LT 3323 3578 LT 6298 3578 LT ST
568 
(0) 3330 3538 WT pop 0 originOffset 37 add RSS
569 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) 3066 3721 WT TSE RSS
570 
3522 3612 MT 3536 3612 LS
571 
3948 3612 MT 3962 3612 LS
572 
4374 3612 MT 4388 3612 LS
573 
4800 3612 MT 4814 3612 LS
574 
5226 3612 MT 5240 3612 LS
575 
5652 3612 MT 5666 3612 LS
576 
6078 3612 MT 6092 3612 LS
577 
3103 3682 MT 3316 3682 LS
578 
3316 3682 MT 3316 3682 LT 3323 3641 LT 6298 3641 LT ST
579 
3316 3682 MT 3316 3682 LT 3323 3722 LT 6298 3722 LT ST
580 
(0) 3330 3682 WT pop 0 originOffset 37 add RSS
581 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) 3066 3865 WT TSE RSS
582 
3522 3756 MT 3536 3756 LS
583 
3948 3756 MT 3962 3756 LS
584 
4374 3756 MT 4388 3756 LS
585 
4800 3756 MT 4814 3756 LS
586 
5226 3756 MT 5240 3756 LS
587 
5652 3756 MT 5666 3756 LS
588 
6078 3756 MT 6092 3756 LS
589 
3103 3826 MT 3316 3826 LS
590 
3316 3826 MT 3316 3866 LS
591 
3316 3866 MT 6298 3866 LS
592 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) 3066 4009 WT TSE RSS
593 
3522 3900 MT 3536 3900 LS
594 
3948 3900 MT 3962 3900 LS
595 
4374 3900 MT 4388 3900 LS
596 
4800 3900 MT 4814 3900 LS
597 
5226 3900 MT 5240 3900 LS
598 
5652 3900 MT 5666 3900 LS
599 
6078 3900 MT 6092 3900 LS
600 
3103 3970 MT 3316 3970 LS
601 
3316 3970 MT 3316 3970 LT 3323 3929 LT 6298 3929 LT ST
602 
3316 3970 MT 3316 3970 LT 3323 4010 LT 6298 4010 LT ST
603 
(0) 3330 3970 WT pop 0 originOffset 37 add RSS
604 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) 3066 4153 WT TSE RSS
605 
3522 4044 MT 3536 4044 LS
606 
3948 4044 MT 3962 4044 LS
607 
4374 4044 MT 4388 4044 LS
608 
4800 4044 MT 4814 4044 LS
609 
5226 4044 MT 5240 4044 LS
610 
5652 4044 MT 5666 4044 LS
611 
6078 4044 MT 6092 4044 LS
612 
3103 4114 MT 3316 4114 LS
613 
3316 4114 MT 3316 4154 LS
614 
3316 4154 MT 6298 4154 LS
615 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) 3066 4297 WT TSE RSS
616 
3522 4188 MT 3536 4188 LS
617 
3948 4188 MT 3962 4188 LS
618 
4374 4188 MT 4388 4188 LS
619 
4800 4188 MT 4814 4188 LS
620 
5226 4188 MT 5240 4188 LS
621 
5652 4188 MT 5666 4188 LS
622 
6078 4188 MT 6092 4188 LS
623 
3103 4258 MT 3316 4258 LS
624 
3316 4258 MT 3316 4298 LS
625 
3316 4298 MT 4168 4298 LS
626 
4168 4298 MT 4168 4258 LS
627 
4168 4258 MT 6298 4258 LS
628 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) 3066 4441 WT TSE RSS
629 
3522 4332 MT 3536 4332 LS
630 
3948 4332 MT 3962 4332 LS
631 
4374 4332 MT 4388 4332 LS
632 
4800 4332 MT 4814 4332 LS
633 
5226 4332 MT 5240 4332 LS
634 
5652 4332 MT 5666 4332 LS
635 
6078 4332 MT 6092 4332 LS
636 
3103 4402 MT 3316 4402 LS
637 
3316 4402 MT 3316 4402 LT 3323 4361 LT 6298 4361 LT ST
638 
3316 4402 MT 3316 4402 LT 3323 4442 LT 6298 4442 LT ST
639 
(00000000) 3330 4402 WT pop 0 originOffset 37 add RSS
640 
% draw footer
641 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 1 Page: 1) 300 4799 WT TSW RSS
642 
grestore
643 
showpage
644 
%%Page: 2 2
645 
gsave
646 
90 rotate 0.12 dup neg scale
647 
% dump string table
648 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
649 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
650 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
651 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
652 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
653 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
654 
/ARC {5 -2 roll SX 5 2 roll arc} def
655 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
656 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
657 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
658 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
659 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
660 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
661 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
662 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
663 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
664 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
665 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
666 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
667 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
668 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
669 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
670 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
671 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
672 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
673 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
674 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
675 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
676 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
677 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
678 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
679 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
680 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
681 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
682 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
683 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
684 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
685 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
686 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
687 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
688 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
689 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
690 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
691 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
692 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
693 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
694 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
695 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
696 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
697 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
698 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
699 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
700 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
701 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
702 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
703 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
704 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
705 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
706 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
707 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
708 
% draw waveform shading
709 
[] 0 SD
710 
2.995 setlinewidth
711 
 
712 
 
713 
 
714 
3103 370 MT 3316 370 LS
715 
3316 370 MT 3316 370 LT 3323 329 LT 4161 329 LT 4168 370 LT ST
716 
3316 370 MT 3316 370 LT 3323 410 LT 4161 410 LT 4168 370 LT ST
717 
(0000) 3330 370 WT pop 0 originOffset 37 add RSS
718 
4168 370 MT 4168 370 LT 4175 329 LT 4587 329 LT 4594 370 LT ST
719 
4168 370 MT 4168 370 LT 4175 410 LT 4587 410 LT 4594 370 LT ST
720 
(1000) 4182 370 WT pop 0 originOffset 37 add RSS
721 
4594 370 MT 4594 370 LT 4601 329 LT 6298 329 LT ST
722 
4594 370 MT 4594 370 LT 4601 410 LT 6298 410 LT ST
723 
(1800) 4608 370 WT pop 0 originOffset 37 add RSS
724 
3103 514 MT 3316 514 LS
725 
3316 514 MT 3316 514 LT 3323 473 LT 4587 473 LT 4594 514 LT ST
726 
3316 514 MT 3316 514 LT 3323 554 LT 4587 554 LT 4594 514 LT ST
727 
(0) 3330 514 WT pop 0 originOffset 37 add RSS
728 
4594 514 MT 4594 514 LT 4601 473 LT 5013 473 LT 5020 514 LT ST
729 
4594 514 MT 4594 514 LT 4601 554 LT 5013 554 LT 5020 514 LT ST
730 
(1) 4608 514 WT pop 0 originOffset 37 add RSS
731 
5020 514 MT 5020 514 LT 5027 473 LT 5439 473 LT 5446 514 LT ST
732 
5020 514 MT 5020 514 LT 5027 554 LT 5439 554 LT 5446 514 LT ST
733 
(2) 5034 514 WT pop 0 originOffset 37 add RSS
734 
5446 514 MT 5446 514 LT 5453 473 LT 5865 473 LT 5872 514 LT ST
735 
5446 514 MT 5446 514 LT 5453 554 LT 5865 554 LT 5872 514 LT ST
736 
(3) 5460 514 WT pop 0 originOffset 37 add RSS
737 
5872 514 MT 5872 514 LT 5879 473 LT 6298 473 LT ST
738 
5872 514 MT 5872 514 LT 5879 554 LT 6298 554 LT ST
739 
(4) 5886 514 WT pop 0 originOffset 37 add RSS
740 
3103 658 MT 3316 658 LS
741 
3316 658 MT 3316 658 LT 3323 617 LT 5013 617 LT 5020 658 LT ST
742 
3316 658 MT 3316 658 LT 3323 698 LT 5013 698 LT 5020 658 LT ST
743 
(0) 3330 658 WT pop 0 originOffset 37 add RSS
744 
5020 658 MT 5020 658 LT 5027 617 LT 5439 617 LT 5446 658 LT ST
745 
5020 658 MT 5020 658 LT 5027 698 LT 5439 698 LT 5446 658 LT ST
746 
(1) 5034 658 WT pop 0 originOffset 37 add RSS
747 
5446 658 MT 5446 658 LT 5453 617 LT 5865 617 LT 5872 658 LT ST
748 
5446 658 MT 5446 658 LT 5453 698 LT 5865 698 LT 5872 658 LT ST
749 
(2) 5460 658 WT pop 0 originOffset 37 add RSS
750 
5872 658 MT 5872 658 LT 5879 617 LT 6298 617 LT ST
751 
5872 658 MT 5872 658 LT 5879 698 LT 6298 698 LT ST
752 
(3) 5886 658 WT pop 0 originOffset 37 add RSS
753 
3103 802 MT 3955 802 LS
754 
3955 802 MT 3955 842 LS
755 
3955 842 MT 6298 842 LS
756 
3103 946 MT 3316 946 LS
757 
3316 946 MT 3316 946 LT 3323 905 LT 5013 905 LT 5020 946 LT ST
758 
3316 946 MT 3316 946 LT 3323 986 LT 5013 986 LT 5020 946 LT ST
759 
(14410000) 3330 946 WT pop 0 originOffset 37 add RSS
760 
5020 946 MT 5020 946 LT 5027 905 LT 6298 905 LT ST
761 
5020 946 MT 5020 946 LT 5027 986 LT 6298 986 LT ST
762 
(14610000) 5034 946 WT pop 0 originOffset 37 add RSS
763 
3103 1090 MT 3316 1090 LS
764 
3316 1090 MT 3316 1090 LT 3323 1049 LT 4587 1049 LT 4594 1090 LT ST
765 
3316 1090 MT 3316 1090 LT 3323 1130 LT 4587 1130 LT 4594 1090 LT ST
766 
(00) 3330 1090 WT pop 0 originOffset 37 add RSS
767 
4594 1090 MT 4594 1090 LT 4601 1049 LT 5013 1049 LT 5020 1090 LT ST
768 
4594 1090 MT 4594 1090 LT 4601 1130 LT 5013 1130 LT 5020 1090 LT ST
769 
(02) 4608 1090 WT pop 0 originOffset 37 add RSS
770 
5020 1090 MT 5020 1090 LT 5027 1049 LT 6298 1049 LT ST
771 
5020 1090 MT 5020 1090 LT 5027 1130 LT 6298 1130 LT ST
772 
(03) 5034 1090 WT pop 0 originOffset 37 add RSS
773 
3103 1234 MT 3316 1234 LS
774 
3316 1234 MT 3316 1274 LS
775 
3316 1274 MT 6298 1274 LS
776 
% draw timeline
777 
3146 4533 MT 3146 4570 LS
778 
3188 4533 MT 3188 4570 LS
779 
3231 4533 MT 3231 4570 LS
780 
3273 4533 MT 3273 4570 LS
781 
3316 4533 MT 3316 4570 LS
782 
3359 4533 MT 3359 4570 LS
783 
3401 4533 MT 3401 4570 LS
784 
3444 4533 MT 3444 4570 LS
785 
3486 4533 MT 3486 4570 LS
786 
(0) 3103 4649 WT TS RSS
787 
3572 4533 MT 3572 4570 LS
788 
3614 4533 MT 3614 4570 LS
789 
3657 4533 MT 3657 4570 LS
790 
3699 4533 MT 3699 4570 LS
791 
3742 4533 MT 3742 4570 LS
792 
3785 4533 MT 3785 4570 LS
793 
3827 4533 MT 3827 4570 LS
794 
3870 4533 MT 3870 4570 LS
795 
3912 4533 MT 3912 4570 LS
796 
3529 4506 MT 3529 4570 LS
797 
3998 4533 MT 3998 4570 LS
798 
4040 4533 MT 4040 4570 LS
799 
4083 4533 MT 4083 4570 LS
800 
4125 4533 MT 4125 4570 LS
801 
4168 4533 MT 4168 4570 LS
802 
4211 4533 MT 4211 4570 LS
803 
4253 4533 MT 4253 4570 LS
804 
4296 4533 MT 4296 4570 LS
805 
4338 4533 MT 4338 4570 LS
806 
3955 4506 MT 3955 4570 LS
807 
(20) 3955 4649 WT TS RSS
808 
4424 4533 MT 4424 4570 LS
809 
4466 4533 MT 4466 4570 LS
810 
4509 4533 MT 4509 4570 LS
811 
4551 4533 MT 4551 4570 LS
812 
4594 4533 MT 4594 4570 LS
813 
4637 4533 MT 4637 4570 LS
814 
4679 4533 MT 4679 4570 LS
815 
4722 4533 MT 4722 4570 LS
816 
4764 4533 MT 4764 4570 LS
817 
4381 4506 MT 4381 4570 LS
818 
4850 4533 MT 4850 4570 LS
819 
4892 4533 MT 4892 4570 LS
820 
4935 4533 MT 4935 4570 LS
821 
4977 4533 MT 4977 4570 LS
822 
5020 4533 MT 5020 4570 LS
823 
5063 4533 MT 5063 4570 LS
824 
5105 4533 MT 5105 4570 LS
825 
5148 4533 MT 5148 4570 LS
826 
5190 4533 MT 5190 4570 LS
827 
4807 4506 MT 4807 4570 LS
828 
(40) 4807 4649 WT TS RSS
829 
5276 4533 MT 5276 4570 LS
830 
5318 4533 MT 5318 4570 LS
831 
5361 4533 MT 5361 4570 LS
832 
5403 4533 MT 5403 4570 LS
833 
5446 4533 MT 5446 4570 LS
834 
5489 4533 MT 5489 4570 LS
835 
5531 4533 MT 5531 4570 LS
836 
5574 4533 MT 5574 4570 LS
837 
5616 4533 MT 5616 4570 LS
838 
5233 4506 MT 5233 4570 LS
839 
5702 4533 MT 5702 4570 LS
840 
5744 4533 MT 5744 4570 LS
841 
5787 4533 MT 5787 4570 LS
842 
5829 4533 MT 5829 4570 LS
843 
5872 4533 MT 5872 4570 LS
844 
5915 4533 MT 5915 4570 LS
845 
5957 4533 MT 5957 4570 LS
846 
6000 4533 MT 6000 4570 LS
847 
6042 4533 MT 6042 4570 LS
848 
5659 4506 MT 5659 4570 LS
849 
(60) 5659 4649 WT TS RSS
850 
6128 4533 MT 6128 4570 LS
851 
6170 4533 MT 6170 4570 LS
852 
6213 4533 MT 6213 4570 LS
853 
6255 4533 MT 6255 4570 LS
854 
6298 4533 MT 6298 4570 LS
855 
6341 4533 MT 6341 4570 LS
856 
6383 4533 MT 6383 4570 LS
857 
6426 4533 MT 6426 4570 LS
858 
6468 4533 MT 6468 4570 LS
859 
6085 4506 MT 6085 4570 LS
860 
% draw grid
861 
3529 300 MT 3529 4506 LS
862 
3955 300 MT 3955 4506 LS
863 
4381 300 MT 4381 4506 LS
864 
4807 300 MT 4807 4506 LS
865 
5233 300 MT 5233 4506 LS
866 
5659 300 MT 5659 4506 LS
867 
6085 300 MT 6085 4506 LS
868 
% draw waveforms
869 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) 3066 409 WT TSE RSS
870 
3522 300 MT 3536 300 LS
871 
3948 300 MT 3962 300 LS
872 
4374 300 MT 4388 300 LS
873 
4800 300 MT 4814 300 LS
874 
5226 300 MT 5240 300 LS
875 
5652 300 MT 5666 300 LS
876 
6078 300 MT 6092 300 LS
877 
3103 370 MT 3316 370 LS
878 
3316 370 MT 3316 370 LT 3323 329 LT 4161 329 LT 4168 370 LT ST
879 
3316 370 MT 3316 370 LT 3323 410 LT 4161 410 LT 4168 370 LT ST
880 
(0000) 3330 370 WT pop 0 originOffset 37 add RSS
881 
4168 370 MT 4168 370 LT 4175 329 LT 4587 329 LT 4594 370 LT ST
882 
4168 370 MT 4168 370 LT 4175 410 LT 4587 410 LT 4594 370 LT ST
883 
(1000) 4182 370 WT pop 0 originOffset 37 add RSS
884 
4594 370 MT 4594 370 LT 4601 329 LT 6298 329 LT ST
885 
4594 370 MT 4594 370 LT 4601 410 LT 6298 410 LT ST
886 
(1800) 4608 370 WT pop 0 originOffset 37 add RSS
887 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) 3066 553 WT TSE RSS
888 
3522 444 MT 3536 444 LS
889 
3948 444 MT 3962 444 LS
890 
4374 444 MT 4388 444 LS
891 
4800 444 MT 4814 444 LS
892 
5226 444 MT 5240 444 LS
893 
5652 444 MT 5666 444 LS
894 
6078 444 MT 6092 444 LS
895 
3103 514 MT 3316 514 LS
896 
3316 514 MT 3316 514 LT 3323 473 LT 4587 473 LT 4594 514 LT ST
897 
3316 514 MT 3316 514 LT 3323 554 LT 4587 554 LT 4594 514 LT ST
898 
(0) 3330 514 WT pop 0 originOffset 37 add RSS
899 
4594 514 MT 4594 514 LT 4601 473 LT 5013 473 LT 5020 514 LT ST
900 
4594 514 MT 4594 514 LT 4601 554 LT 5013 554 LT 5020 514 LT ST
901 
(1) 4608 514 WT pop 0 originOffset 37 add RSS
902 
5020 514 MT 5020 514 LT 5027 473 LT 5439 473 LT 5446 514 LT ST
903 
5020 514 MT 5020 514 LT 5027 554 LT 5439 554 LT 5446 514 LT ST
904 
(2) 5034 514 WT pop 0 originOffset 37 add RSS
905 
5446 514 MT 5446 514 LT 5453 473 LT 5865 473 LT 5872 514 LT ST
906 
5446 514 MT 5446 514 LT 5453 554 LT 5865 554 LT 5872 514 LT ST
907 
(3) 5460 514 WT pop 0 originOffset 37 add RSS
908 
5872 514 MT 5872 514 LT 5879 473 LT 6298 473 LT ST
909 
5872 514 MT 5872 514 LT 5879 554 LT 6298 554 LT ST
910 
(4) 5886 514 WT pop 0 originOffset 37 add RSS
911 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) 3066 697 WT TSE RSS
912 
3522 588 MT 3536 588 LS
913 
3948 588 MT 3962 588 LS
914 
4374 588 MT 4388 588 LS
915 
4800 588 MT 4814 588 LS
916 
5226 588 MT 5240 588 LS
917 
5652 588 MT 5666 588 LS
918 
6078 588 MT 6092 588 LS
919 
3103 658 MT 3316 658 LS
920 
3316 658 MT 3316 658 LT 3323 617 LT 5013 617 LT 5020 658 LT ST
921 
3316 658 MT 3316 658 LT 3323 698 LT 5013 698 LT 5020 658 LT ST
922 
(0) 3330 658 WT pop 0 originOffset 37 add RSS
923 
5020 658 MT 5020 658 LT 5027 617 LT 5439 617 LT 5446 658 LT ST
924 
5020 658 MT 5020 658 LT 5027 698 LT 5439 698 LT 5446 658 LT ST
925 
(1) 5034 658 WT pop 0 originOffset 37 add RSS
926 
5446 658 MT 5446 658 LT 5453 617 LT 5865 617 LT 5872 658 LT ST
927 
5446 658 MT 5446 658 LT 5453 698 LT 5865 698 LT 5872 658 LT ST
928 
(2) 5460 658 WT pop 0 originOffset 37 add RSS
929 
5872 658 MT 5872 658 LT 5879 617 LT 6298 617 LT ST
930 
5872 658 MT 5872 658 LT 5879 698 LT 6298 698 LT ST
931 
(3) 5886 658 WT pop 0 originOffset 37 add RSS
932 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) 3066 841 WT TSE RSS
933 
3522 732 MT 3536 732 LS
934 
3948 732 MT 3962 732 LS
935 
4374 732 MT 4388 732 LS
936 
4800 732 MT 4814 732 LS
937 
5226 732 MT 5240 732 LS
938 
5652 732 MT 5666 732 LS
939 
6078 732 MT 6092 732 LS
940 
3103 802 MT 3955 802 LS
941 
3955 802 MT 3955 842 LS
942 
3955 842 MT 6298 842 LS
943 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) 3066 985 WT TSE RSS
944 
3522 876 MT 3536 876 LS
945 
3948 876 MT 3962 876 LS
946 
4374 876 MT 4388 876 LS
947 
4800 876 MT 4814 876 LS
948 
5226 876 MT 5240 876 LS
949 
5652 876 MT 5666 876 LS
950 
6078 876 MT 6092 876 LS
951 
3103 946 MT 3316 946 LS
952 
3316 946 MT 3316 946 LT 3323 905 LT 5013 905 LT 5020 946 LT ST
953 
3316 946 MT 3316 946 LT 3323 986 LT 5013 986 LT 5020 946 LT ST
954 
(14410000) 3330 946 WT pop 0 originOffset 37 add RSS
955 
5020 946 MT 5020 946 LT 5027 905 LT 6298 905 LT ST
956 
5020 946 MT 5020 946 LT 5027 986 LT 6298 986 LT ST
957 
(14610000) 5034 946 WT pop 0 originOffset 37 add RSS
958 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) 3066 1129 WT TSE RSS
959 
3522 1020 MT 3536 1020 LS
960 
3948 1020 MT 3962 1020 LS
961 
4374 1020 MT 4388 1020 LS
962 
4800 1020 MT 4814 1020 LS
963 
5226 1020 MT 5240 1020 LS
964 
5652 1020 MT 5666 1020 LS
965 
6078 1020 MT 6092 1020 LS
966 
3103 1090 MT 3316 1090 LS
967 
3316 1090 MT 3316 1090 LT 3323 1049 LT 4587 1049 LT 4594 1090 LT ST
968 
3316 1090 MT 3316 1090 LT 3323 1130 LT 4587 1130 LT 4594 1090 LT ST
969 
(00) 3330 1090 WT pop 0 originOffset 37 add RSS
970 
4594 1090 MT 4594 1090 LT 4601 1049 LT 5013 1049 LT 5020 1090 LT ST
971 
4594 1090 MT 4594 1090 LT 4601 1130 LT 5013 1130 LT 5020 1090 LT ST
972 
(02) 4608 1090 WT pop 0 originOffset 37 add RSS
973 
5020 1090 MT 5020 1090 LT 5027 1049 LT 6298 1049 LT ST
974 
5020 1090 MT 5020 1090 LT 5027 1130 LT 6298 1130 LT ST
975 
(03) 5034 1090 WT pop 0 originOffset 37 add RSS
976 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) 3066 1273 WT TSE RSS
977 
3522 1164 MT 3536 1164 LS
978 
3948 1164 MT 3962 1164 LS
979 
4374 1164 MT 4388 1164 LS
980 
4800 1164 MT 4814 1164 LS
981 
5226 1164 MT 5240 1164 LS
982 
5652 1164 MT 5666 1164 LS
983 
6078 1164 MT 6092 1164 LS
984 
3103 1234 MT 3316 1234 LS
985 
3316 1234 MT 3316 1274 LS
986 
3316 1274 MT 6298 1274 LS
987 
% draw footer
988 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 1 Page: 2) 300 4799 WT TSW RSS
989 
grestore
990 
showpage
991 
%%Page: 3 3
992 
gsave
993 
90 rotate 0.12 dup neg scale
994 
% dump string table
995 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
996 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
997 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
998 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
999 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
1000 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
1001 
/ARC {5 -2 roll SX 5 2 roll arc} def
1002 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
1003 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
1004 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
1005 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
1006 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
1007 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
1008 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
1009 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
1010 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
1011 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
1012 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
1013 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
1014 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
1015 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
1016 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
1017 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
1018 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
1019 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
1020 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
1021 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
1022 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
1023 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
1024 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
1025 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
1026 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
1027 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
1028 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
1029 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
1030 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
1031 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
1032 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
1033 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
1034 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
1035 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
1036 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
1037 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
1038 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
1039 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
1040 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
1041 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
1042 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
1043 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
1044 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
1045 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
1046 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
1047 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
1048 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
1049 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
1050 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
1051 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
1052 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
1053 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
1054 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
1055 
% draw waveform shading
1056 
[] 0 SD
1057 
2.995 setlinewidth
1058 
 
1059 
 
1060 
 
1061 
3103 370 MT 6298 370 LS
1062 
3103 554 MT 6298 554 LS
1063 
3103 698 MT 6298 698 LS
1064 
3103 761 MT 3103 761 LT 6298 761 LT ST
1065 
3103 842 MT 3103 842 LT 6298 842 LT ST
1066 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
1067 
3103 986 MT 6298 986 LS
1068 
3103 1050 MT 6298 1050 LS
1069 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
1070 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
1071 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
1072 
3103 1418 MT 6298 1418 LS
1073 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
1074 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
1075 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
1076 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
1077 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
1078 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
1079 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
1080 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
1081 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
1082 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
1083 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
1084 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
1085 
3103 2138 MT 6298 2138 LS
1086 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
1087 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
1088 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
1089 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
1090 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
1091 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
1092 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
1093 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
1094 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
1095 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
1096 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
1097 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
1098 
3103 2858 MT 6298 2858 LS
1099 
3103 3002 MT 6298 3002 LS
1100 
3103 3146 MT 6298 3146 LS
1101 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
1102 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
1103 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
1104 
3103 3434 MT 6298 3434 LS
1105 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
1106 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
1107 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
1108 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
1109 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
1110 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
1111 
3103 3866 MT 6298 3866 LS
1112 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
1113 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
1114 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
1115 
3103 4154 MT 6298 4154 LS
1116 
3103 4258 MT 6298 4258 LS
1117 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
1118 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
1119 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
1120 
% draw timeline
1121 
3145 4533 MT 3145 4570 LS
1122 
3187 4533 MT 3187 4570 LS
1123 
3230 4533 MT 3230 4570 LS
1124 
3272 4533 MT 3272 4570 LS
1125 
3359 4533 MT 3359 4570 LS
1126 
3401 4533 MT 3401 4570 LS
1127 
3444 4533 MT 3444 4570 LS
1128 
3486 4533 MT 3486 4570 LS
1129 
3529 4533 MT 3529 4570 LS
1130 
3572 4533 MT 3572 4570 LS
1131 
3614 4533 MT 3614 4570 LS
1132 
3657 4533 MT 3657 4570 LS
1133 
3699 4533 MT 3699 4570 LS
1134 
3316 4506 MT 3316 4570 LS
1135 
(80) 3316 4649 WT TS RSS
1136 
3785 4533 MT 3785 4570 LS
1137 
3827 4533 MT 3827 4570 LS
1138 
3870 4533 MT 3870 4570 LS
1139 
3912 4533 MT 3912 4570 LS
1140 
3955 4533 MT 3955 4570 LS
1141 
3998 4533 MT 3998 4570 LS
1142 
4040 4533 MT 4040 4570 LS
1143 
4083 4533 MT 4083 4570 LS
1144 
4125 4533 MT 4125 4570 LS
1145 
3742 4506 MT 3742 4570 LS
1146 
4211 4533 MT 4211 4570 LS
1147 
4253 4533 MT 4253 4570 LS
1148 
4296 4533 MT 4296 4570 LS
1149 
4338 4533 MT 4338 4570 LS
1150 
4381 4533 MT 4381 4570 LS
1151 
4424 4533 MT 4424 4570 LS
1152 
4466 4533 MT 4466 4570 LS
1153 
4509 4533 MT 4509 4570 LS
1154 
4551 4533 MT 4551 4570 LS
1155 
4168 4506 MT 4168 4570 LS
1156 
(100) 4168 4649 WT TS RSS
1157 
4637 4533 MT 4637 4570 LS
1158 
4679 4533 MT 4679 4570 LS
1159 
4722 4533 MT 4722 4570 LS
1160 
4764 4533 MT 4764 4570 LS
1161 
4807 4533 MT 4807 4570 LS
1162 
4850 4533 MT 4850 4570 LS
1163 
4892 4533 MT 4892 4570 LS
1164 
4935 4533 MT 4935 4570 LS
1165 
4977 4533 MT 4977 4570 LS
1166 
4594 4506 MT 4594 4570 LS
1167 
5063 4533 MT 5063 4570 LS
1168 
5105 4533 MT 5105 4570 LS
1169 
5148 4533 MT 5148 4570 LS
1170 
5190 4533 MT 5190 4570 LS
1171 
5233 4533 MT 5233 4570 LS
1172 
5276 4533 MT 5276 4570 LS
1173 
5318 4533 MT 5318 4570 LS
1174 
5361 4533 MT 5361 4570 LS
1175 
5403 4533 MT 5403 4570 LS
1176 
5020 4506 MT 5020 4570 LS
1177 
(120) 5020 4649 WT TS RSS
1178 
5489 4533 MT 5489 4570 LS
1179 
5531 4533 MT 5531 4570 LS
1180 
5574 4533 MT 5574 4570 LS
1181 
5616 4533 MT 5616 4570 LS
1182 
5659 4533 MT 5659 4570 LS
1183 
5702 4533 MT 5702 4570 LS
1184 
5744 4533 MT 5744 4570 LS
1185 
5787 4533 MT 5787 4570 LS
1186 
5829 4533 MT 5829 4570 LS
1187 
5446 4506 MT 5446 4570 LS
1188 
5915 4533 MT 5915 4570 LS
1189 
5957 4533 MT 5957 4570 LS
1190 
6000 4533 MT 6000 4570 LS
1191 
6042 4533 MT 6042 4570 LS
1192 
6085 4533 MT 6085 4570 LS
1193 
6128 4533 MT 6128 4570 LS
1194 
6170 4533 MT 6170 4570 LS
1195 
6213 4533 MT 6213 4570 LS
1196 
6255 4533 MT 6255 4570 LS
1197 
5872 4506 MT 5872 4570 LS
1198 
(140) 5872 4649 WT TS RSS
1199 
6341 4533 MT 6341 4570 LS
1200 
6383 4533 MT 6383 4570 LS
1201 
6426 4533 MT 6426 4570 LS
1202 
6468 4533 MT 6468 4570 LS
1203 
6511 4533 MT 6511 4570 LS
1204 
6554 4533 MT 6554 4570 LS
1205 
6596 4533 MT 6596 4570 LS
1206 
6639 4533 MT 6639 4570 LS
1207 
6681 4533 MT 6681 4570 LS
1208 
6298 4506 MT 6298 4570 LS
1209 
% draw grid
1210 
3316 300 MT 3316 4506 LS
1211 
3742 300 MT 3742 4506 LS
1212 
4168 300 MT 4168 4506 LS
1213 
4594 300 MT 4594 4506 LS
1214 
5020 300 MT 5020 4506 LS
1215 
5446 300 MT 5446 4506 LS
1216 
5872 300 MT 5872 4506 LS
1217 
6298 300 MT 6298 4506 LS
1218 
% draw waveforms
1219 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) 3066 409 WT TSE RSS
1220 
3309 300 MT 3323 300 LS
1221 
3735 300 MT 3749 300 LS
1222 
4161 300 MT 4175 300 LS
1223 
4587 300 MT 4601 300 LS
1224 
5013 300 MT 5027 300 LS
1225 
5439 300 MT 5453 300 LS
1226 
5865 300 MT 5879 300 LS
1227 
6291 300 MT 6305 300 LS
1228 
3103 370 MT 6298 370 LS
1229 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) 3066 553 WT TSE RSS
1230 
3309 444 MT 3323 444 LS
1231 
3735 444 MT 3749 444 LS
1232 
4161 444 MT 4175 444 LS
1233 
4587 444 MT 4601 444 LS
1234 
5013 444 MT 5027 444 LS
1235 
5439 444 MT 5453 444 LS
1236 
5865 444 MT 5879 444 LS
1237 
6291 444 MT 6305 444 LS
1238 
3103 554 MT 6298 554 LS
1239 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) 3066 697 WT TSE RSS
1240 
3309 588 MT 3323 588 LS
1241 
3735 588 MT 3749 588 LS
1242 
4161 588 MT 4175 588 LS
1243 
4587 588 MT 4601 588 LS
1244 
5013 588 MT 5027 588 LS
1245 
5439 588 MT 5453 588 LS
1246 
5865 588 MT 5879 588 LS
1247 
6291 588 MT 6305 588 LS
1248 
3103 698 MT 6298 698 LS
1249 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) 3066 841 WT TSE RSS
1250 
3309 732 MT 3323 732 LS
1251 
3735 732 MT 3749 732 LS
1252 
4161 732 MT 4175 732 LS
1253 
4587 732 MT 4601 732 LS
1254 
5013 732 MT 5027 732 LS
1255 
5439 732 MT 5453 732 LS
1256 
5865 732 MT 5879 732 LS
1257 
6291 732 MT 6305 732 LS
1258 
3103 761 MT 3103 761 LT 6298 761 LT ST
1259 
3103 842 MT 3103 842 LT 6298 842 LT ST
1260 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
1261 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) 3066 985 WT TSE RSS
1262 
3309 876 MT 3323 876 LS
1263 
3735 876 MT 3749 876 LS
1264 
4161 876 MT 4175 876 LS
1265 
4587 876 MT 4601 876 LS
1266 
5013 876 MT 5027 876 LS
1267 
5439 876 MT 5453 876 LS
1268 
5865 876 MT 5879 876 LS
1269 
6291 876 MT 6305 876 LS
1270 
3103 986 MT 6298 986 LS
1271 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) 3066 1129 WT TSE RSS
1272 
3309 1020 MT 3323 1020 LS
1273 
3735 1020 MT 3749 1020 LS
1274 
4161 1020 MT 4175 1020 LS
1275 
4587 1020 MT 4601 1020 LS
1276 
5013 1020 MT 5027 1020 LS
1277 
5439 1020 MT 5453 1020 LS
1278 
5865 1020 MT 5879 1020 LS
1279 
6291 1020 MT 6305 1020 LS
1280 
3103 1050 MT 6298 1050 LS
1281 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) 3066 1273 WT TSE RSS
1282 
3309 1164 MT 3323 1164 LS
1283 
3735 1164 MT 3749 1164 LS
1284 
4161 1164 MT 4175 1164 LS
1285 
4587 1164 MT 4601 1164 LS
1286 
5013 1164 MT 5027 1164 LS
1287 
5439 1164 MT 5453 1164 LS
1288 
5865 1164 MT 5879 1164 LS
1289 
6291 1164 MT 6305 1164 LS
1290 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
1291 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
1292 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
1293 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) 3066 1417 WT TSE RSS
1294 
3309 1308 MT 3323 1308 LS
1295 
3735 1308 MT 3749 1308 LS
1296 
4161 1308 MT 4175 1308 LS
1297 
4587 1308 MT 4601 1308 LS
1298 
5013 1308 MT 5027 1308 LS
1299 
5439 1308 MT 5453 1308 LS
1300 
5865 1308 MT 5879 1308 LS
1301 
6291 1308 MT 6305 1308 LS
1302 
3103 1418 MT 6298 1418 LS
1303 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) 3066 1561 WT TSE RSS
1304 
3309 1452 MT 3323 1452 LS
1305 
3735 1452 MT 3749 1452 LS
1306 
4161 1452 MT 4175 1452 LS
1307 
4587 1452 MT 4601 1452 LS
1308 
5013 1452 MT 5027 1452 LS
1309 
5439 1452 MT 5453 1452 LS
1310 
5865 1452 MT 5879 1452 LS
1311 
6291 1452 MT 6305 1452 LS
1312 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
1313 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
1314 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
1315 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) 3066 1705 WT TSE RSS
1316 
3309 1596 MT 3323 1596 LS
1317 
3735 1596 MT 3749 1596 LS
1318 
4161 1596 MT 4175 1596 LS
1319 
4587 1596 MT 4601 1596 LS
1320 
5013 1596 MT 5027 1596 LS
1321 
5439 1596 MT 5453 1596 LS
1322 
5865 1596 MT 5879 1596 LS
1323 
6291 1596 MT 6305 1596 LS
1324 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
1325 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
1326 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
1327 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) 3066 1849 WT TSE RSS
1328 
3309 1740 MT 3323 1740 LS
1329 
3735 1740 MT 3749 1740 LS
1330 
4161 1740 MT 4175 1740 LS
1331 
4587 1740 MT 4601 1740 LS
1332 
5013 1740 MT 5027 1740 LS
1333 
5439 1740 MT 5453 1740 LS
1334 
5865 1740 MT 5879 1740 LS
1335 
6291 1740 MT 6305 1740 LS
1336 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
1337 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
1338 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
1339 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) 3066 1993 WT TSE RSS
1340 
3309 1884 MT 3323 1884 LS
1341 
3735 1884 MT 3749 1884 LS
1342 
4161 1884 MT 4175 1884 LS
1343 
4587 1884 MT 4601 1884 LS
1344 
5013 1884 MT 5027 1884 LS
1345 
5439 1884 MT 5453 1884 LS
1346 
5865 1884 MT 5879 1884 LS
1347 
6291 1884 MT 6305 1884 LS
1348 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
1349 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
1350 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
1351 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) 3066 2137 WT TSE RSS
1352 
3309 2028 MT 3323 2028 LS
1353 
3735 2028 MT 3749 2028 LS
1354 
4161 2028 MT 4175 2028 LS
1355 
4587 2028 MT 4601 2028 LS
1356 
5013 2028 MT 5027 2028 LS
1357 
5439 2028 MT 5453 2028 LS
1358 
5865 2028 MT 5879 2028 LS
1359 
6291 2028 MT 6305 2028 LS
1360 
3103 2138 MT 6298 2138 LS
1361 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) 3066 2281 WT TSE RSS
1362 
3309 2172 MT 3323 2172 LS
1363 
3735 2172 MT 3749 2172 LS
1364 
4161 2172 MT 4175 2172 LS
1365 
4587 2172 MT 4601 2172 LS
1366 
5013 2172 MT 5027 2172 LS
1367 
5439 2172 MT 5453 2172 LS
1368 
5865 2172 MT 5879 2172 LS
1369 
6291 2172 MT 6305 2172 LS
1370 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
1371 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
1372 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
1373 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) 3066 2425 WT TSE RSS
1374 
3309 2316 MT 3323 2316 LS
1375 
3735 2316 MT 3749 2316 LS
1376 
4161 2316 MT 4175 2316 LS
1377 
4587 2316 MT 4601 2316 LS
1378 
5013 2316 MT 5027 2316 LS
1379 
5439 2316 MT 5453 2316 LS
1380 
5865 2316 MT 5879 2316 LS
1381 
6291 2316 MT 6305 2316 LS
1382 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
1383 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
1384 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
1385 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) 3066 2569 WT TSE RSS
1386 
3309 2460 MT 3323 2460 LS
1387 
3735 2460 MT 3749 2460 LS
1388 
4161 2460 MT 4175 2460 LS
1389 
4587 2460 MT 4601 2460 LS
1390 
5013 2460 MT 5027 2460 LS
1391 
5439 2460 MT 5453 2460 LS
1392 
5865 2460 MT 5879 2460 LS
1393 
6291 2460 MT 6305 2460 LS
1394 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
1395 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
1396 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
1397 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) 3066 2713 WT TSE RSS
1398 
3309 2604 MT 3323 2604 LS
1399 
3735 2604 MT 3749 2604 LS
1400 
4161 2604 MT 4175 2604 LS
1401 
4587 2604 MT 4601 2604 LS
1402 
5013 2604 MT 5027 2604 LS
1403 
5439 2604 MT 5453 2604 LS
1404 
5865 2604 MT 5879 2604 LS
1405 
6291 2604 MT 6305 2604 LS
1406 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
1407 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
1408 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
1409 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) 3066 2857 WT TSE RSS
1410 
3309 2748 MT 3323 2748 LS
1411 
3735 2748 MT 3749 2748 LS
1412 
4161 2748 MT 4175 2748 LS
1413 
4587 2748 MT 4601 2748 LS
1414 
5013 2748 MT 5027 2748 LS
1415 
5439 2748 MT 5453 2748 LS
1416 
5865 2748 MT 5879 2748 LS
1417 
6291 2748 MT 6305 2748 LS
1418 
3103 2858 MT 6298 2858 LS
1419 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) 3066 3001 WT TSE RSS
1420 
3309 2892 MT 3323 2892 LS
1421 
3735 2892 MT 3749 2892 LS
1422 
4161 2892 MT 4175 2892 LS
1423 
4587 2892 MT 4601 2892 LS
1424 
5013 2892 MT 5027 2892 LS
1425 
5439 2892 MT 5453 2892 LS
1426 
5865 2892 MT 5879 2892 LS
1427 
6291 2892 MT 6305 2892 LS
1428 
3103 3002 MT 6298 3002 LS
1429 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) 3066 3145 WT TSE RSS
1430 
3309 3036 MT 3323 3036 LS
1431 
3735 3036 MT 3749 3036 LS
1432 
4161 3036 MT 4175 3036 LS
1433 
4587 3036 MT 4601 3036 LS
1434 
5013 3036 MT 5027 3036 LS
1435 
5439 3036 MT 5453 3036 LS
1436 
5865 3036 MT 5879 3036 LS
1437 
6291 3036 MT 6305 3036 LS
1438 
3103 3146 MT 6298 3146 LS
1439 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) 3066 3289 WT TSE RSS
1440 
3309 3180 MT 3323 3180 LS
1441 
3735 3180 MT 3749 3180 LS
1442 
4161 3180 MT 4175 3180 LS
1443 
4587 3180 MT 4601 3180 LS
1444 
5013 3180 MT 5027 3180 LS
1445 
5439 3180 MT 5453 3180 LS
1446 
5865 3180 MT 5879 3180 LS
1447 
6291 3180 MT 6305 3180 LS
1448 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
1449 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
1450 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
1451 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) 3066 3433 WT TSE RSS
1452 
3309 3324 MT 3323 3324 LS
1453 
3735 3324 MT 3749 3324 LS
1454 
4161 3324 MT 4175 3324 LS
1455 
4587 3324 MT 4601 3324 LS
1456 
5013 3324 MT 5027 3324 LS
1457 
5439 3324 MT 5453 3324 LS
1458 
5865 3324 MT 5879 3324 LS
1459 
6291 3324 MT 6305 3324 LS
1460 
3103 3434 MT 6298 3434 LS
1461 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) 3066 3577 WT TSE RSS
1462 
3309 3468 MT 3323 3468 LS
1463 
3735 3468 MT 3749 3468 LS
1464 
4161 3468 MT 4175 3468 LS
1465 
4587 3468 MT 4601 3468 LS
1466 
5013 3468 MT 5027 3468 LS
1467 
5439 3468 MT 5453 3468 LS
1468 
5865 3468 MT 5879 3468 LS
1469 
6291 3468 MT 6305 3468 LS
1470 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
1471 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
1472 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
1473 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) 3066 3721 WT TSE RSS
1474 
3309 3612 MT 3323 3612 LS
1475 
3735 3612 MT 3749 3612 LS
1476 
4161 3612 MT 4175 3612 LS
1477 
4587 3612 MT 4601 3612 LS
1478 
5013 3612 MT 5027 3612 LS
1479 
5439 3612 MT 5453 3612 LS
1480 
5865 3612 MT 5879 3612 LS
1481 
6291 3612 MT 6305 3612 LS
1482 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
1483 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
1484 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
1485 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) 3066 3865 WT TSE RSS
1486 
3309 3756 MT 3323 3756 LS
1487 
3735 3756 MT 3749 3756 LS
1488 
4161 3756 MT 4175 3756 LS
1489 
4587 3756 MT 4601 3756 LS
1490 
5013 3756 MT 5027 3756 LS
1491 
5439 3756 MT 5453 3756 LS
1492 
5865 3756 MT 5879 3756 LS
1493 
6291 3756 MT 6305 3756 LS
1494 
3103 3866 MT 6298 3866 LS
1495 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) 3066 4009 WT TSE RSS
1496 
3309 3900 MT 3323 3900 LS
1497 
3735 3900 MT 3749 3900 LS
1498 
4161 3900 MT 4175 3900 LS
1499 
4587 3900 MT 4601 3900 LS
1500 
5013 3900 MT 5027 3900 LS
1501 
5439 3900 MT 5453 3900 LS
1502 
5865 3900 MT 5879 3900 LS
1503 
6291 3900 MT 6305 3900 LS
1504 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
1505 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
1506 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
1507 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) 3066 4153 WT TSE RSS
1508 
3309 4044 MT 3323 4044 LS
1509 
3735 4044 MT 3749 4044 LS
1510 
4161 4044 MT 4175 4044 LS
1511 
4587 4044 MT 4601 4044 LS
1512 
5013 4044 MT 5027 4044 LS
1513 
5439 4044 MT 5453 4044 LS
1514 
5865 4044 MT 5879 4044 LS
1515 
6291 4044 MT 6305 4044 LS
1516 
3103 4154 MT 6298 4154 LS
1517 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) 3066 4297 WT TSE RSS
1518 
3309 4188 MT 3323 4188 LS
1519 
3735 4188 MT 3749 4188 LS
1520 
4161 4188 MT 4175 4188 LS
1521 
4587 4188 MT 4601 4188 LS
1522 
5013 4188 MT 5027 4188 LS
1523 
5439 4188 MT 5453 4188 LS
1524 
5865 4188 MT 5879 4188 LS
1525 
6291 4188 MT 6305 4188 LS
1526 
3103 4258 MT 6298 4258 LS
1527 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) 3066 4441 WT TSE RSS
1528 
3309 4332 MT 3323 4332 LS
1529 
3735 4332 MT 3749 4332 LS
1530 
4161 4332 MT 4175 4332 LS
1531 
4587 4332 MT 4601 4332 LS
1532 
5013 4332 MT 5027 4332 LS
1533 
5439 4332 MT 5453 4332 LS
1534 
5865 4332 MT 5879 4332 LS
1535 
6291 4332 MT 6305 4332 LS
1536 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
1537 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
1538 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
1539 
% draw footer
1540 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 2 Page: 3) 300 4799 WT TSW RSS
1541 
grestore
1542 
showpage
1543 
%%Page: 4 4
1544 
gsave
1545 
90 rotate 0.12 dup neg scale
1546 
% dump string table
1547 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
1548 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
1549 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
1550 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
1551 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
1552 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
1553 
/ARC {5 -2 roll SX 5 2 roll arc} def
1554 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
1555 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
1556 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
1557 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
1558 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
1559 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
1560 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
1561 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
1562 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
1563 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
1564 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
1565 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
1566 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
1567 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
1568 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
1569 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
1570 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
1571 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
1572 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
1573 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
1574 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
1575 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
1576 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
1577 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
1578 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
1579 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
1580 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
1581 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
1582 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
1583 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
1584 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
1585 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
1586 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
1587 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
1588 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
1589 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
1590 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
1591 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
1592 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
1593 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
1594 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
1595 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
1596 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
1597 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
1598 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
1599 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
1600 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
1601 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
1602 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
1603 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
1604 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
1605 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
1606 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
1607 
% draw waveform shading
1608 
[] 0 SD
1609 
2.995 setlinewidth
1610 
 
1611 
 
1612 
 
1613 
3103 329 MT 3103 329 LT 6298 329 LT ST
1614 
3103 410 MT 3103 410 LT 6298 410 LT ST
1615 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
1616 
3103 473 MT 3103 473 LT 3522 473 LT 3529 514 LT ST
1617 
3103 554 MT 3103 554 LT 3522 554 LT 3529 514 LT ST
1618 
(5) 3117 514 WT pop 0 originOffset 37 add RSS
1619 
3529 514 MT 3529 514 LT 3536 473 LT 3948 473 LT 3955 514 LT ST
1620 
3529 514 MT 3529 514 LT 3536 554 LT 3948 554 LT 3955 514 LT ST
1621 
(6) 3543 514 WT pop 0 originOffset 37 add RSS
1622 
3955 514 MT 3955 514 LT 3962 473 LT 4374 473 LT 4381 514 LT ST
1623 
3955 514 MT 3955 514 LT 3962 554 LT 4374 554 LT 4381 514 LT ST
1624 
(7) 3969 514 WT pop 0 originOffset 37 add RSS
1625 
4381 514 MT 4381 514 LT 4388 473 LT 4800 473 LT 4807 514 LT ST
1626 
4381 514 MT 4381 514 LT 4388 554 LT 4800 554 LT 4807 514 LT ST
1627 
(0) 4395 514 WT pop 0 originOffset 37 add RSS
1628 
4807 514 MT 4807 514 LT 4814 473 LT 5226 473 LT 5233 514 LT ST
1629 
4807 514 MT 4807 514 LT 4814 554 LT 5226 554 LT 5233 514 LT ST
1630 
(1) 4821 514 WT pop 0 originOffset 37 add RSS
1631 
5233 514 MT 5233 514 LT 5240 473 LT 5652 473 LT 5659 514 LT ST
1632 
5233 514 MT 5233 514 LT 5240 554 LT 5652 554 LT 5659 514 LT ST
1633 
(2) 5247 514 WT pop 0 originOffset 37 add RSS
1634 
5659 514 MT 5659 514 LT 5666 473 LT 6078 473 LT 6085 514 LT ST
1635 
5659 514 MT 5659 514 LT 5666 554 LT 6078 554 LT 6085 514 LT ST
1636 
(3) 5673 514 WT pop 0 originOffset 37 add RSS
1637 
6085 514 MT 6085 514 LT 6092 473 LT 6298 473 LT ST
1638 
6085 514 MT 6085 514 LT 6092 554 LT 6298 554 LT ST
1639 
(4) 6099 514 WT pop 0 originOffset 37 add RSS
1640 
3103 617 MT 3103 617 LT 3522 617 LT 3529 658 LT ST
1641 
3103 698 MT 3103 698 LT 3522 698 LT 3529 658 LT ST
1642 
(4) 3117 658 WT pop 0 originOffset 37 add RSS
1643 
3529 658 MT 3529 658 LT 3536 617 LT 3948 617 LT 3955 658 LT ST
1644 
3529 658 MT 3529 658 LT 3536 698 LT 3948 698 LT 3955 658 LT ST
1645 
(5) 3543 658 WT pop 0 originOffset 37 add RSS
1646 
3955 658 MT 3955 658 LT 3962 617 LT 4374 617 LT 4381 658 LT ST
1647 
3955 658 MT 3955 658 LT 3962 698 LT 4374 698 LT 4381 658 LT ST
1648 
(6) 3969 658 WT pop 0 originOffset 37 add RSS
1649 
4381 658 MT 4381 658 LT 4388 617 LT 4800 617 LT 4807 658 LT ST
1650 
4381 658 MT 4381 658 LT 4388 698 LT 4800 698 LT 4807 658 LT ST
1651 
(7) 4395 658 WT pop 0 originOffset 37 add RSS
1652 
4807 658 MT 4807 658 LT 4814 617 LT 5226 617 LT 5233 658 LT ST
1653 
4807 658 MT 4807 658 LT 4814 698 LT 5226 698 LT 5233 658 LT ST
1654 
(0) 4821 658 WT pop 0 originOffset 37 add RSS
1655 
5233 658 MT 5233 658 LT 5240 617 LT 5652 617 LT 5659 658 LT ST
1656 
5233 658 MT 5233 658 LT 5240 698 LT 5652 698 LT 5659 658 LT ST
1657 
(1) 5247 658 WT pop 0 originOffset 37 add RSS
1658 
5659 658 MT 5659 658 LT 5666 617 LT 6078 617 LT 6085 658 LT ST
1659 
5659 658 MT 5659 658 LT 5666 698 LT 6078 698 LT 6085 658 LT ST
1660 
(2) 5673 658 WT pop 0 originOffset 37 add RSS
1661 
6085 658 MT 6085 658 LT 6092 617 LT 6298 617 LT ST
1662 
6085 658 MT 6085 658 LT 6092 698 LT 6298 698 LT ST
1663 
(3) 6099 658 WT pop 0 originOffset 37 add RSS
1664 
3103 842 MT 6298 842 LS
1665 
3103 905 MT 3103 905 LT 6298 905 LT ST
1666 
3103 986 MT 3103 986 LT 6298 986 LT ST
1667 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
1668 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
1669 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
1670 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
1671 
3103 1274 MT 6298 1274 LS
1672 
% draw timeline
1673 
3145 4533 MT 3145 4570 LS
1674 
3187 4533 MT 3187 4570 LS
1675 
3230 4533 MT 3230 4570 LS
1676 
3272 4533 MT 3272 4570 LS
1677 
3359 4533 MT 3359 4570 LS
1678 
3401 4533 MT 3401 4570 LS
1679 
3444 4533 MT 3444 4570 LS
1680 
3486 4533 MT 3486 4570 LS
1681 
3529 4533 MT 3529 4570 LS
1682 
3572 4533 MT 3572 4570 LS
1683 
3614 4533 MT 3614 4570 LS
1684 
3657 4533 MT 3657 4570 LS
1685 
3699 4533 MT 3699 4570 LS
1686 
3316 4506 MT 3316 4570 LS
1687 
(80) 3316 4649 WT TS RSS
1688 
3785 4533 MT 3785 4570 LS
1689 
3827 4533 MT 3827 4570 LS
1690 
3870 4533 MT 3870 4570 LS
1691 
3912 4533 MT 3912 4570 LS
1692 
3955 4533 MT 3955 4570 LS
1693 
3998 4533 MT 3998 4570 LS
1694 
4040 4533 MT 4040 4570 LS
1695 
4083 4533 MT 4083 4570 LS
1696 
4125 4533 MT 4125 4570 LS
1697 
3742 4506 MT 3742 4570 LS
1698 
4211 4533 MT 4211 4570 LS
1699 
4253 4533 MT 4253 4570 LS
1700 
4296 4533 MT 4296 4570 LS
1701 
4338 4533 MT 4338 4570 LS
1702 
4381 4533 MT 4381 4570 LS
1703 
4424 4533 MT 4424 4570 LS
1704 
4466 4533 MT 4466 4570 LS
1705 
4509 4533 MT 4509 4570 LS
1706 
4551 4533 MT 4551 4570 LS
1707 
4168 4506 MT 4168 4570 LS
1708 
(100) 4168 4649 WT TS RSS
1709 
4637 4533 MT 4637 4570 LS
1710 
4679 4533 MT 4679 4570 LS
1711 
4722 4533 MT 4722 4570 LS
1712 
4764 4533 MT 4764 4570 LS
1713 
4807 4533 MT 4807 4570 LS
1714 
4850 4533 MT 4850 4570 LS
1715 
4892 4533 MT 4892 4570 LS
1716 
4935 4533 MT 4935 4570 LS
1717 
4977 4533 MT 4977 4570 LS
1718 
4594 4506 MT 4594 4570 LS
1719 
5063 4533 MT 5063 4570 LS
1720 
5105 4533 MT 5105 4570 LS
1721 
5148 4533 MT 5148 4570 LS
1722 
5190 4533 MT 5190 4570 LS
1723 
5233 4533 MT 5233 4570 LS
1724 
5276 4533 MT 5276 4570 LS
1725 
5318 4533 MT 5318 4570 LS
1726 
5361 4533 MT 5361 4570 LS
1727 
5403 4533 MT 5403 4570 LS
1728 
5020 4506 MT 5020 4570 LS
1729 
(120) 5020 4649 WT TS RSS
1730 
5489 4533 MT 5489 4570 LS
1731 
5531 4533 MT 5531 4570 LS
1732 
5574 4533 MT 5574 4570 LS
1733 
5616 4533 MT 5616 4570 LS
1734 
5659 4533 MT 5659 4570 LS
1735 
5702 4533 MT 5702 4570 LS
1736 
5744 4533 MT 5744 4570 LS
1737 
5787 4533 MT 5787 4570 LS
1738 
5829 4533 MT 5829 4570 LS
1739 
5446 4506 MT 5446 4570 LS
1740 
5915 4533 MT 5915 4570 LS
1741 
5957 4533 MT 5957 4570 LS
1742 
6000 4533 MT 6000 4570 LS
1743 
6042 4533 MT 6042 4570 LS
1744 
6085 4533 MT 6085 4570 LS
1745 
6128 4533 MT 6128 4570 LS
1746 
6170 4533 MT 6170 4570 LS
1747 
6213 4533 MT 6213 4570 LS
1748 
6255 4533 MT 6255 4570 LS
1749 
5872 4506 MT 5872 4570 LS
1750 
(140) 5872 4649 WT TS RSS
1751 
6341 4533 MT 6341 4570 LS
1752 
6383 4533 MT 6383 4570 LS
1753 
6426 4533 MT 6426 4570 LS
1754 
6468 4533 MT 6468 4570 LS
1755 
6511 4533 MT 6511 4570 LS
1756 
6554 4533 MT 6554 4570 LS
1757 
6596 4533 MT 6596 4570 LS
1758 
6639 4533 MT 6639 4570 LS
1759 
6681 4533 MT 6681 4570 LS
1760 
6298 4506 MT 6298 4570 LS
1761 
% draw grid
1762 
3316 300 MT 3316 4506 LS
1763 
3742 300 MT 3742 4506 LS
1764 
4168 300 MT 4168 4506 LS
1765 
4594 300 MT 4594 4506 LS
1766 
5020 300 MT 5020 4506 LS
1767 
5446 300 MT 5446 4506 LS
1768 
5872 300 MT 5872 4506 LS
1769 
6298 300 MT 6298 4506 LS
1770 
% draw waveforms
1771 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) 3066 409 WT TSE RSS
1772 
3309 300 MT 3323 300 LS
1773 
3735 300 MT 3749 300 LS
1774 
4161 300 MT 4175 300 LS
1775 
4587 300 MT 4601 300 LS
1776 
5013 300 MT 5027 300 LS
1777 
5439 300 MT 5453 300 LS
1778 
5865 300 MT 5879 300 LS
1779 
6291 300 MT 6305 300 LS
1780 
3103 329 MT 3103 329 LT 6298 329 LT ST
1781 
3103 410 MT 3103 410 LT 6298 410 LT ST
1782 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
1783 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) 3066 553 WT TSE RSS
1784 
3309 444 MT 3323 444 LS
1785 
3735 444 MT 3749 444 LS
1786 
4161 444 MT 4175 444 LS
1787 
4587 444 MT 4601 444 LS
1788 
5013 444 MT 5027 444 LS
1789 
5439 444 MT 5453 444 LS
1790 
5865 444 MT 5879 444 LS
1791 
6291 444 MT 6305 444 LS
1792 
3103 473 MT 3103 473 LT 3522 473 LT 3529 514 LT ST
1793 
3103 554 MT 3103 554 LT 3522 554 LT 3529 514 LT ST
1794 
(5) 3117 514 WT pop 0 originOffset 37 add RSS
1795 
3529 514 MT 3529 514 LT 3536 473 LT 3948 473 LT 3955 514 LT ST
1796 
3529 514 MT 3529 514 LT 3536 554 LT 3948 554 LT 3955 514 LT ST
1797 
(6) 3543 514 WT pop 0 originOffset 37 add RSS
1798 
3955 514 MT 3955 514 LT 3962 473 LT 4374 473 LT 4381 514 LT ST
1799 
3955 514 MT 3955 514 LT 3962 554 LT 4374 554 LT 4381 514 LT ST
1800 
(7) 3969 514 WT pop 0 originOffset 37 add RSS
1801 
4381 514 MT 4381 514 LT 4388 473 LT 4800 473 LT 4807 514 LT ST
1802 
4381 514 MT 4381 514 LT 4388 554 LT 4800 554 LT 4807 514 LT ST
1803 
(0) 4395 514 WT pop 0 originOffset 37 add RSS
1804 
4807 514 MT 4807 514 LT 4814 473 LT 5226 473 LT 5233 514 LT ST
1805 
4807 514 MT 4807 514 LT 4814 554 LT 5226 554 LT 5233 514 LT ST
1806 
(1) 4821 514 WT pop 0 originOffset 37 add RSS
1807 
5233 514 MT 5233 514 LT 5240 473 LT 5652 473 LT 5659 514 LT ST
1808 
5233 514 MT 5233 514 LT 5240 554 LT 5652 554 LT 5659 514 LT ST
1809 
(2) 5247 514 WT pop 0 originOffset 37 add RSS
1810 
5659 514 MT 5659 514 LT 5666 473 LT 6078 473 LT 6085 514 LT ST
1811 
5659 514 MT 5659 514 LT 5666 554 LT 6078 554 LT 6085 514 LT ST
1812 
(3) 5673 514 WT pop 0 originOffset 37 add RSS
1813 
6085 514 MT 6085 514 LT 6092 473 LT 6298 473 LT ST
1814 
6085 514 MT 6085 514 LT 6092 554 LT 6298 554 LT ST
1815 
(4) 6099 514 WT pop 0 originOffset 37 add RSS
1816 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) 3066 697 WT TSE RSS
1817 
3309 588 MT 3323 588 LS
1818 
3735 588 MT 3749 588 LS
1819 
4161 588 MT 4175 588 LS
1820 
4587 588 MT 4601 588 LS
1821 
5013 588 MT 5027 588 LS
1822 
5439 588 MT 5453 588 LS
1823 
5865 588 MT 5879 588 LS
1824 
6291 588 MT 6305 588 LS
1825 
3103 617 MT 3103 617 LT 3522 617 LT 3529 658 LT ST
1826 
3103 698 MT 3103 698 LT 3522 698 LT 3529 658 LT ST
1827 
(4) 3117 658 WT pop 0 originOffset 37 add RSS
1828 
3529 658 MT 3529 658 LT 3536 617 LT 3948 617 LT 3955 658 LT ST
1829 
3529 658 MT 3529 658 LT 3536 698 LT 3948 698 LT 3955 658 LT ST
1830 
(5) 3543 658 WT pop 0 originOffset 37 add RSS
1831 
3955 658 MT 3955 658 LT 3962 617 LT 4374 617 LT 4381 658 LT ST
1832 
3955 658 MT 3955 658 LT 3962 698 LT 4374 698 LT 4381 658 LT ST
1833 
(6) 3969 658 WT pop 0 originOffset 37 add RSS
1834 
4381 658 MT 4381 658 LT 4388 617 LT 4800 617 LT 4807 658 LT ST
1835 
4381 658 MT 4381 658 LT 4388 698 LT 4800 698 LT 4807 658 LT ST
1836 
(7) 4395 658 WT pop 0 originOffset 37 add RSS
1837 
4807 658 MT 4807 658 LT 4814 617 LT 5226 617 LT 5233 658 LT ST
1838 
4807 658 MT 4807 658 LT 4814 698 LT 5226 698 LT 5233 658 LT ST
1839 
(0) 4821 658 WT pop 0 originOffset 37 add RSS
1840 
5233 658 MT 5233 658 LT 5240 617 LT 5652 617 LT 5659 658 LT ST
1841 
5233 658 MT 5233 658 LT 5240 698 LT 5652 698 LT 5659 658 LT ST
1842 
(1) 5247 658 WT pop 0 originOffset 37 add RSS
1843 
5659 658 MT 5659 658 LT 5666 617 LT 6078 617 LT 6085 658 LT ST
1844 
5659 658 MT 5659 658 LT 5666 698 LT 6078 698 LT 6085 658 LT ST
1845 
(2) 5673 658 WT pop 0 originOffset 37 add RSS
1846 
6085 658 MT 6085 658 LT 6092 617 LT 6298 617 LT ST
1847 
6085 658 MT 6085 658 LT 6092 698 LT 6298 698 LT ST
1848 
(3) 6099 658 WT pop 0 originOffset 37 add RSS
1849 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) 3066 841 WT TSE RSS
1850 
3309 732 MT 3323 732 LS
1851 
3735 732 MT 3749 732 LS
1852 
4161 732 MT 4175 732 LS
1853 
4587 732 MT 4601 732 LS
1854 
5013 732 MT 5027 732 LS
1855 
5439 732 MT 5453 732 LS
1856 
5865 732 MT 5879 732 LS
1857 
6291 732 MT 6305 732 LS
1858 
3103 842 MT 6298 842 LS
1859 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) 3066 985 WT TSE RSS
1860 
3309 876 MT 3323 876 LS
1861 
3735 876 MT 3749 876 LS
1862 
4161 876 MT 4175 876 LS
1863 
4587 876 MT 4601 876 LS
1864 
5013 876 MT 5027 876 LS
1865 
5439 876 MT 5453 876 LS
1866 
5865 876 MT 5879 876 LS
1867 
6291 876 MT 6305 876 LS
1868 
3103 905 MT 3103 905 LT 6298 905 LT ST
1869 
3103 986 MT 3103 986 LT 6298 986 LT ST
1870 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
1871 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) 3066 1129 WT TSE RSS
1872 
3309 1020 MT 3323 1020 LS
1873 
3735 1020 MT 3749 1020 LS
1874 
4161 1020 MT 4175 1020 LS
1875 
4587 1020 MT 4601 1020 LS
1876 
5013 1020 MT 5027 1020 LS
1877 
5439 1020 MT 5453 1020 LS
1878 
5865 1020 MT 5879 1020 LS
1879 
6291 1020 MT 6305 1020 LS
1880 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
1881 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
1882 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
1883 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) 3066 1273 WT TSE RSS
1884 
3309 1164 MT 3323 1164 LS
1885 
3735 1164 MT 3749 1164 LS
1886 
4161 1164 MT 4175 1164 LS
1887 
4587 1164 MT 4601 1164 LS
1888 
5013 1164 MT 5027 1164 LS
1889 
5439 1164 MT 5453 1164 LS
1890 
5865 1164 MT 5879 1164 LS
1891 
6291 1164 MT 6305 1164 LS
1892 
3103 1274 MT 6298 1274 LS
1893 
% draw footer
1894 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 2 Page: 4) 300 4799 WT TSW RSS
1895 
grestore
1896 
showpage
1897 
%%Page: 5 5
1898 
gsave
1899 
90 rotate 0.12 dup neg scale
1900 
% dump string table
1901 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
1902 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
1903 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
1904 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
1905 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
1906 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
1907 
/ARC {5 -2 roll SX 5 2 roll arc} def
1908 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
1909 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
1910 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
1911 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
1912 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
1913 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
1914 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
1915 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
1916 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
1917 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
1918 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
1919 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
1920 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
1921 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
1922 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
1923 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
1924 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
1925 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
1926 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
1927 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
1928 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
1929 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
1930 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
1931 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
1932 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
1933 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
1934 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
1935 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
1936 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
1937 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
1938 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
1939 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
1940 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
1941 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
1942 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
1943 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
1944 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
1945 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
1946 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
1947 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
1948 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
1949 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
1950 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
1951 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
1952 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
1953 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
1954 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
1955 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
1956 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
1957 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
1958 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
1959 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
1960 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
1961 
% draw waveform shading
1962 
[] 0 SD
1963 
2.995 setlinewidth
1964 
 
1965 
 
1966 
 
1967 
3103 370 MT 6298 370 LS
1968 
3103 554 MT 6298 554 LS
1969 
3103 698 MT 6298 698 LS
1970 
3103 761 MT 3103 761 LT 6298 761 LT ST
1971 
3103 842 MT 3103 842 LT 6298 842 LT ST
1972 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
1973 
3103 986 MT 6298 986 LS
1974 
3103 1050 MT 6298 1050 LS
1975 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
1976 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
1977 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
1978 
3103 1418 MT 6298 1418 LS
1979 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
1980 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
1981 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
1982 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
1983 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
1984 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
1985 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
1986 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
1987 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
1988 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
1989 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
1990 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
1991 
3103 2138 MT 6298 2138 LS
1992 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
1993 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
1994 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
1995 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
1996 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
1997 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
1998 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
1999 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
2000 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
2001 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
2002 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
2003 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
2004 
3103 2858 MT 6298 2858 LS
2005 
3103 3002 MT 6298 3002 LS
2006 
3103 3146 MT 6298 3146 LS
2007 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
2008 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
2009 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
2010 
3103 3434 MT 6298 3434 LS
2011 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
2012 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
2013 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
2014 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
2015 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
2016 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
2017 
3103 3866 MT 6298 3866 LS
2018 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
2019 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
2020 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
2021 
3103 4154 MT 6298 4154 LS
2022 
3103 4258 MT 6298 4258 LS
2023 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
2024 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
2025 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
2026 
% draw timeline
2027 
3146 4533 MT 3146 4570 LS
2028 
3188 4533 MT 3188 4570 LS
2029 
3231 4533 MT 3231 4570 LS
2030 
3273 4533 MT 3273 4570 LS
2031 
3316 4533 MT 3316 4570 LS
2032 
3359 4533 MT 3359 4570 LS
2033 
3401 4533 MT 3401 4570 LS
2034 
3444 4533 MT 3444 4570 LS
2035 
3486 4533 MT 3486 4570 LS
2036 
3572 4533 MT 3572 4570 LS
2037 
3614 4533 MT 3614 4570 LS
2038 
3657 4533 MT 3657 4570 LS
2039 
3699 4533 MT 3699 4570 LS
2040 
3742 4533 MT 3742 4570 LS
2041 
3785 4533 MT 3785 4570 LS
2042 
3827 4533 MT 3827 4570 LS
2043 
3870 4533 MT 3870 4570 LS
2044 
3912 4533 MT 3912 4570 LS
2045 
3529 4506 MT 3529 4570 LS
2046 
(160) 3529 4649 WT TS RSS
2047 
3998 4533 MT 3998 4570 LS
2048 
4040 4533 MT 4040 4570 LS
2049 
4083 4533 MT 4083 4570 LS
2050 
4125 4533 MT 4125 4570 LS
2051 
4168 4533 MT 4168 4570 LS
2052 
4211 4533 MT 4211 4570 LS
2053 
4253 4533 MT 4253 4570 LS
2054 
4296 4533 MT 4296 4570 LS
2055 
4338 4533 MT 4338 4570 LS
2056 
3955 4506 MT 3955 4570 LS
2057 
4424 4533 MT 4424 4570 LS
2058 
4466 4533 MT 4466 4570 LS
2059 
4509 4533 MT 4509 4570 LS
2060 
4551 4533 MT 4551 4570 LS
2061 
4594 4533 MT 4594 4570 LS
2062 
4637 4533 MT 4637 4570 LS
2063 
4679 4533 MT 4679 4570 LS
2064 
4722 4533 MT 4722 4570 LS
2065 
4764 4533 MT 4764 4570 LS
2066 
4381 4506 MT 4381 4570 LS
2067 
(180) 4381 4649 WT TS RSS
2068 
4850 4533 MT 4850 4570 LS
2069 
4892 4533 MT 4892 4570 LS
2070 
4935 4533 MT 4935 4570 LS
2071 
4977 4533 MT 4977 4570 LS
2072 
5020 4533 MT 5020 4570 LS
2073 
5063 4533 MT 5063 4570 LS
2074 
5105 4533 MT 5105 4570 LS
2075 
5148 4533 MT 5148 4570 LS
2076 
5190 4533 MT 5190 4570 LS
2077 
4807 4506 MT 4807 4570 LS
2078 
5276 4533 MT 5276 4570 LS
2079 
5318 4533 MT 5318 4570 LS
2080 
5361 4533 MT 5361 4570 LS
2081 
5403 4533 MT 5403 4570 LS
2082 
5446 4533 MT 5446 4570 LS
2083 
5489 4533 MT 5489 4570 LS
2084 
5531 4533 MT 5531 4570 LS
2085 
5574 4533 MT 5574 4570 LS
2086 
5616 4533 MT 5616 4570 LS
2087 
5233 4506 MT 5233 4570 LS
2088 
(200) 5233 4649 WT TS RSS
2089 
5702 4533 MT 5702 4570 LS
2090 
5744 4533 MT 5744 4570 LS
2091 
5787 4533 MT 5787 4570 LS
2092 
5829 4533 MT 5829 4570 LS
2093 
5872 4533 MT 5872 4570 LS
2094 
5915 4533 MT 5915 4570 LS
2095 
5957 4533 MT 5957 4570 LS
2096 
6000 4533 MT 6000 4570 LS
2097 
6042 4533 MT 6042 4570 LS
2098 
5659 4506 MT 5659 4570 LS
2099 
6128 4533 MT 6128 4570 LS
2100 
6170 4533 MT 6170 4570 LS
2101 
6213 4533 MT 6213 4570 LS
2102 
6255 4533 MT 6255 4570 LS
2103 
6298 4533 MT 6298 4570 LS
2104 
6341 4533 MT 6341 4570 LS
2105 
6383 4533 MT 6383 4570 LS
2106 
6426 4533 MT 6426 4570 LS
2107 
6468 4533 MT 6468 4570 LS
2108 
6085 4506 MT 6085 4570 LS
2109 
(220) 6085 4649 WT TS RSS
2110 
% draw grid
2111 
3529 300 MT 3529 4506 LS
2112 
3955 300 MT 3955 4506 LS
2113 
4381 300 MT 4381 4506 LS
2114 
4807 300 MT 4807 4506 LS
2115 
5233 300 MT 5233 4506 LS
2116 
5659 300 MT 5659 4506 LS
2117 
6085 300 MT 6085 4506 LS
2118 
% draw waveforms
2119 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) 3066 409 WT TSE RSS
2120 
3522 300 MT 3536 300 LS
2121 
3948 300 MT 3962 300 LS
2122 
4374 300 MT 4388 300 LS
2123 
4800 300 MT 4814 300 LS
2124 
5226 300 MT 5240 300 LS
2125 
5652 300 MT 5666 300 LS
2126 
6078 300 MT 6092 300 LS
2127 
3103 370 MT 6298 370 LS
2128 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) 3066 553 WT TSE RSS
2129 
3522 444 MT 3536 444 LS
2130 
3948 444 MT 3962 444 LS
2131 
4374 444 MT 4388 444 LS
2132 
4800 444 MT 4814 444 LS
2133 
5226 444 MT 5240 444 LS
2134 
5652 444 MT 5666 444 LS
2135 
6078 444 MT 6092 444 LS
2136 
3103 554 MT 6298 554 LS
2137 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) 3066 697 WT TSE RSS
2138 
3522 588 MT 3536 588 LS
2139 
3948 588 MT 3962 588 LS
2140 
4374 588 MT 4388 588 LS
2141 
4800 588 MT 4814 588 LS
2142 
5226 588 MT 5240 588 LS
2143 
5652 588 MT 5666 588 LS
2144 
6078 588 MT 6092 588 LS
2145 
3103 698 MT 6298 698 LS
2146 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) 3066 841 WT TSE RSS
2147 
3522 732 MT 3536 732 LS
2148 
3948 732 MT 3962 732 LS
2149 
4374 732 MT 4388 732 LS
2150 
4800 732 MT 4814 732 LS
2151 
5226 732 MT 5240 732 LS
2152 
5652 732 MT 5666 732 LS
2153 
6078 732 MT 6092 732 LS
2154 
3103 761 MT 3103 761 LT 6298 761 LT ST
2155 
3103 842 MT 3103 842 LT 6298 842 LT ST
2156 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
2157 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) 3066 985 WT TSE RSS
2158 
3522 876 MT 3536 876 LS
2159 
3948 876 MT 3962 876 LS
2160 
4374 876 MT 4388 876 LS
2161 
4800 876 MT 4814 876 LS
2162 
5226 876 MT 5240 876 LS
2163 
5652 876 MT 5666 876 LS
2164 
6078 876 MT 6092 876 LS
2165 
3103 986 MT 6298 986 LS
2166 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) 3066 1129 WT TSE RSS
2167 
3522 1020 MT 3536 1020 LS
2168 
3948 1020 MT 3962 1020 LS
2169 
4374 1020 MT 4388 1020 LS
2170 
4800 1020 MT 4814 1020 LS
2171 
5226 1020 MT 5240 1020 LS
2172 
5652 1020 MT 5666 1020 LS
2173 
6078 1020 MT 6092 1020 LS
2174 
3103 1050 MT 6298 1050 LS
2175 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) 3066 1273 WT TSE RSS
2176 
3522 1164 MT 3536 1164 LS
2177 
3948 1164 MT 3962 1164 LS
2178 
4374 1164 MT 4388 1164 LS
2179 
4800 1164 MT 4814 1164 LS
2180 
5226 1164 MT 5240 1164 LS
2181 
5652 1164 MT 5666 1164 LS
2182 
6078 1164 MT 6092 1164 LS
2183 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
2184 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
2185 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
2186 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) 3066 1417 WT TSE RSS
2187 
3522 1308 MT 3536 1308 LS
2188 
3948 1308 MT 3962 1308 LS
2189 
4374 1308 MT 4388 1308 LS
2190 
4800 1308 MT 4814 1308 LS
2191 
5226 1308 MT 5240 1308 LS
2192 
5652 1308 MT 5666 1308 LS
2193 
6078 1308 MT 6092 1308 LS
2194 
3103 1418 MT 6298 1418 LS
2195 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) 3066 1561 WT TSE RSS
2196 
3522 1452 MT 3536 1452 LS
2197 
3948 1452 MT 3962 1452 LS
2198 
4374 1452 MT 4388 1452 LS
2199 
4800 1452 MT 4814 1452 LS
2200 
5226 1452 MT 5240 1452 LS
2201 
5652 1452 MT 5666 1452 LS
2202 
6078 1452 MT 6092 1452 LS
2203 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
2204 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
2205 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
2206 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) 3066 1705 WT TSE RSS
2207 
3522 1596 MT 3536 1596 LS
2208 
3948 1596 MT 3962 1596 LS
2209 
4374 1596 MT 4388 1596 LS
2210 
4800 1596 MT 4814 1596 LS
2211 
5226 1596 MT 5240 1596 LS
2212 
5652 1596 MT 5666 1596 LS
2213 
6078 1596 MT 6092 1596 LS
2214 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
2215 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
2216 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
2217 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) 3066 1849 WT TSE RSS
2218 
3522 1740 MT 3536 1740 LS
2219 
3948 1740 MT 3962 1740 LS
2220 
4374 1740 MT 4388 1740 LS
2221 
4800 1740 MT 4814 1740 LS
2222 
5226 1740 MT 5240 1740 LS
2223 
5652 1740 MT 5666 1740 LS
2224 
6078 1740 MT 6092 1740 LS
2225 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
2226 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
2227 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
2228 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) 3066 1993 WT TSE RSS
2229 
3522 1884 MT 3536 1884 LS
2230 
3948 1884 MT 3962 1884 LS
2231 
4374 1884 MT 4388 1884 LS
2232 
4800 1884 MT 4814 1884 LS
2233 
5226 1884 MT 5240 1884 LS
2234 
5652 1884 MT 5666 1884 LS
2235 
6078 1884 MT 6092 1884 LS
2236 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
2237 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
2238 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
2239 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) 3066 2137 WT TSE RSS
2240 
3522 2028 MT 3536 2028 LS
2241 
3948 2028 MT 3962 2028 LS
2242 
4374 2028 MT 4388 2028 LS
2243 
4800 2028 MT 4814 2028 LS
2244 
5226 2028 MT 5240 2028 LS
2245 
5652 2028 MT 5666 2028 LS
2246 
6078 2028 MT 6092 2028 LS
2247 
3103 2138 MT 6298 2138 LS
2248 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) 3066 2281 WT TSE RSS
2249 
3522 2172 MT 3536 2172 LS
2250 
3948 2172 MT 3962 2172 LS
2251 
4374 2172 MT 4388 2172 LS
2252 
4800 2172 MT 4814 2172 LS
2253 
5226 2172 MT 5240 2172 LS
2254 
5652 2172 MT 5666 2172 LS
2255 
6078 2172 MT 6092 2172 LS
2256 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
2257 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
2258 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
2259 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) 3066 2425 WT TSE RSS
2260 
3522 2316 MT 3536 2316 LS
2261 
3948 2316 MT 3962 2316 LS
2262 
4374 2316 MT 4388 2316 LS
2263 
4800 2316 MT 4814 2316 LS
2264 
5226 2316 MT 5240 2316 LS
2265 
5652 2316 MT 5666 2316 LS
2266 
6078 2316 MT 6092 2316 LS
2267 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
2268 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
2269 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
2270 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) 3066 2569 WT TSE RSS
2271 
3522 2460 MT 3536 2460 LS
2272 
3948 2460 MT 3962 2460 LS
2273 
4374 2460 MT 4388 2460 LS
2274 
4800 2460 MT 4814 2460 LS
2275 
5226 2460 MT 5240 2460 LS
2276 
5652 2460 MT 5666 2460 LS
2277 
6078 2460 MT 6092 2460 LS
2278 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
2279 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
2280 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
2281 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) 3066 2713 WT TSE RSS
2282 
3522 2604 MT 3536 2604 LS
2283 
3948 2604 MT 3962 2604 LS
2284 
4374 2604 MT 4388 2604 LS
2285 
4800 2604 MT 4814 2604 LS
2286 
5226 2604 MT 5240 2604 LS
2287 
5652 2604 MT 5666 2604 LS
2288 
6078 2604 MT 6092 2604 LS
2289 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
2290 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
2291 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
2292 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) 3066 2857 WT TSE RSS
2293 
3522 2748 MT 3536 2748 LS
2294 
3948 2748 MT 3962 2748 LS
2295 
4374 2748 MT 4388 2748 LS
2296 
4800 2748 MT 4814 2748 LS
2297 
5226 2748 MT 5240 2748 LS
2298 
5652 2748 MT 5666 2748 LS
2299 
6078 2748 MT 6092 2748 LS
2300 
3103 2858 MT 6298 2858 LS
2301 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) 3066 3001 WT TSE RSS
2302 
3522 2892 MT 3536 2892 LS
2303 
3948 2892 MT 3962 2892 LS
2304 
4374 2892 MT 4388 2892 LS
2305 
4800 2892 MT 4814 2892 LS
2306 
5226 2892 MT 5240 2892 LS
2307 
5652 2892 MT 5666 2892 LS
2308 
6078 2892 MT 6092 2892 LS
2309 
3103 3002 MT 6298 3002 LS
2310 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) 3066 3145 WT TSE RSS
2311 
3522 3036 MT 3536 3036 LS
2312 
3948 3036 MT 3962 3036 LS
2313 
4374 3036 MT 4388 3036 LS
2314 
4800 3036 MT 4814 3036 LS
2315 
5226 3036 MT 5240 3036 LS
2316 
5652 3036 MT 5666 3036 LS
2317 
6078 3036 MT 6092 3036 LS
2318 
3103 3146 MT 6298 3146 LS
2319 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) 3066 3289 WT TSE RSS
2320 
3522 3180 MT 3536 3180 LS
2321 
3948 3180 MT 3962 3180 LS
2322 
4374 3180 MT 4388 3180 LS
2323 
4800 3180 MT 4814 3180 LS
2324 
5226 3180 MT 5240 3180 LS
2325 
5652 3180 MT 5666 3180 LS
2326 
6078 3180 MT 6092 3180 LS
2327 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
2328 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
2329 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
2330 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) 3066 3433 WT TSE RSS
2331 
3522 3324 MT 3536 3324 LS
2332 
3948 3324 MT 3962 3324 LS
2333 
4374 3324 MT 4388 3324 LS
2334 
4800 3324 MT 4814 3324 LS
2335 
5226 3324 MT 5240 3324 LS
2336 
5652 3324 MT 5666 3324 LS
2337 
6078 3324 MT 6092 3324 LS
2338 
3103 3434 MT 6298 3434 LS
2339 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) 3066 3577 WT TSE RSS
2340 
3522 3468 MT 3536 3468 LS
2341 
3948 3468 MT 3962 3468 LS
2342 
4374 3468 MT 4388 3468 LS
2343 
4800 3468 MT 4814 3468 LS
2344 
5226 3468 MT 5240 3468 LS
2345 
5652 3468 MT 5666 3468 LS
2346 
6078 3468 MT 6092 3468 LS
2347 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
2348 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
2349 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
2350 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) 3066 3721 WT TSE RSS
2351 
3522 3612 MT 3536 3612 LS
2352 
3948 3612 MT 3962 3612 LS
2353 
4374 3612 MT 4388 3612 LS
2354 
4800 3612 MT 4814 3612 LS
2355 
5226 3612 MT 5240 3612 LS
2356 
5652 3612 MT 5666 3612 LS
2357 
6078 3612 MT 6092 3612 LS
2358 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
2359 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
2360 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
2361 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) 3066 3865 WT TSE RSS
2362 
3522 3756 MT 3536 3756 LS
2363 
3948 3756 MT 3962 3756 LS
2364 
4374 3756 MT 4388 3756 LS
2365 
4800 3756 MT 4814 3756 LS
2366 
5226 3756 MT 5240 3756 LS
2367 
5652 3756 MT 5666 3756 LS
2368 
6078 3756 MT 6092 3756 LS
2369 
3103 3866 MT 6298 3866 LS
2370 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) 3066 4009 WT TSE RSS
2371 
3522 3900 MT 3536 3900 LS
2372 
3948 3900 MT 3962 3900 LS
2373 
4374 3900 MT 4388 3900 LS
2374 
4800 3900 MT 4814 3900 LS
2375 
5226 3900 MT 5240 3900 LS
2376 
5652 3900 MT 5666 3900 LS
2377 
6078 3900 MT 6092 3900 LS
2378 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
2379 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
2380 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
2381 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) 3066 4153 WT TSE RSS
2382 
3522 4044 MT 3536 4044 LS
2383 
3948 4044 MT 3962 4044 LS
2384 
4374 4044 MT 4388 4044 LS
2385 
4800 4044 MT 4814 4044 LS
2386 
5226 4044 MT 5240 4044 LS
2387 
5652 4044 MT 5666 4044 LS
2388 
6078 4044 MT 6092 4044 LS
2389 
3103 4154 MT 6298 4154 LS
2390 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) 3066 4297 WT TSE RSS
2391 
3522 4188 MT 3536 4188 LS
2392 
3948 4188 MT 3962 4188 LS
2393 
4374 4188 MT 4388 4188 LS
2394 
4800 4188 MT 4814 4188 LS
2395 
5226 4188 MT 5240 4188 LS
2396 
5652 4188 MT 5666 4188 LS
2397 
6078 4188 MT 6092 4188 LS
2398 
3103 4258 MT 6298 4258 LS
2399 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) 3066 4441 WT TSE RSS
2400 
3522 4332 MT 3536 4332 LS
2401 
3948 4332 MT 3962 4332 LS
2402 
4374 4332 MT 4388 4332 LS
2403 
4800 4332 MT 4814 4332 LS
2404 
5226 4332 MT 5240 4332 LS
2405 
5652 4332 MT 5666 4332 LS
2406 
6078 4332 MT 6092 4332 LS
2407 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
2408 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
2409 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
2410 
% draw footer
2411 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 3 Page: 5) 300 4799 WT TSW RSS
2412 
grestore
2413 
showpage
2414 
%%Page: 6 6
2415 
gsave
2416 
90 rotate 0.12 dup neg scale
2417 
% dump string table
2418 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
2419 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
2420 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
2421 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
2422 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
2423 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
2424 
/ARC {5 -2 roll SX 5 2 roll arc} def
2425 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
2426 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
2427 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
2428 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
2429 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
2430 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
2431 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
2432 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
2433 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
2434 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
2435 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
2436 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
2437 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
2438 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
2439 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
2440 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
2441 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
2442 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
2443 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
2444 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
2445 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
2446 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
2447 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
2448 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
2449 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
2450 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
2451 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
2452 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
2453 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
2454 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
2455 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
2456 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
2457 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
2458 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
2459 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
2460 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
2461 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
2462 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
2463 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
2464 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
2465 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
2466 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
2467 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
2468 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
2469 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
2470 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
2471 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
2472 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
2473 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
2474 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
2475 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
2476 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
2477 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
2478 
% draw waveform shading
2479 
[] 0 SD
2480 
2.995 setlinewidth
2481 
 
2482 
 
2483 
 
2484 
3103 329 MT 3103 329 LT 6298 329 LT ST
2485 
3103 410 MT 3103 410 LT 6298 410 LT ST
2486 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
2487 
3103 473 MT 3103 473 LT 3309 473 LT 3316 514 LT ST
2488 
3103 554 MT 3103 554 LT 3309 554 LT 3316 514 LT ST
2489 
(4) 3117 514 WT pop 0 originOffset 37 add RSS
2490 
3316 514 MT 3316 514 LT 3323 473 LT 3735 473 LT 3742 514 LT ST
2491 
3316 514 MT 3316 514 LT 3323 554 LT 3735 554 LT 3742 514 LT ST
2492 
(5) 3330 514 WT pop 0 originOffset 37 add RSS
2493 
3742 514 MT 3742 514 LT 3749 473 LT 4161 473 LT 4168 514 LT ST
2494 
3742 514 MT 3742 514 LT 3749 554 LT 4161 554 LT 4168 514 LT ST
2495 
(6) 3756 514 WT pop 0 originOffset 37 add RSS
2496 
4168 514 MT 4168 514 LT 4175 473 LT 4587 473 LT 4594 514 LT ST
2497 
4168 514 MT 4168 514 LT 4175 554 LT 4587 554 LT 4594 514 LT ST
2498 
(7) 4182 514 WT pop 0 originOffset 37 add RSS
2499 
4594 514 MT 4594 514 LT 4601 473 LT 5013 473 LT 5020 514 LT ST
2500 
4594 514 MT 4594 514 LT 4601 554 LT 5013 554 LT 5020 514 LT ST
2501 
(0) 4608 514 WT pop 0 originOffset 37 add RSS
2502 
5020 514 MT 5020 514 LT 5027 473 LT 5439 473 LT 5446 514 LT ST
2503 
5020 514 MT 5020 514 LT 5027 554 LT 5439 554 LT 5446 514 LT ST
2504 
(1) 5034 514 WT pop 0 originOffset 37 add RSS
2505 
5446 514 MT 5446 514 LT 5453 473 LT 5865 473 LT 5872 514 LT ST
2506 
5446 514 MT 5446 514 LT 5453 554 LT 5865 554 LT 5872 514 LT ST
2507 
(2) 5460 514 WT pop 0 originOffset 37 add RSS
2508 
5872 514 MT 5872 514 LT 5879 473 LT 6298 473 LT ST
2509 
5872 514 MT 5872 514 LT 5879 554 LT 6298 554 LT ST
2510 
(3) 5886 514 WT pop 0 originOffset 37 add RSS
2511 
3103 617 MT 3103 617 LT 3309 617 LT 3316 658 LT ST
2512 
3103 698 MT 3103 698 LT 3309 698 LT 3316 658 LT ST
2513 
(3) 3117 658 WT pop 0 originOffset 37 add RSS
2514 
3316 658 MT 3316 658 LT 3323 617 LT 3735 617 LT 3742 658 LT ST
2515 
3316 658 MT 3316 658 LT 3323 698 LT 3735 698 LT 3742 658 LT ST
2516 
(4) 3330 658 WT pop 0 originOffset 37 add RSS
2517 
3742 658 MT 3742 658 LT 3749 617 LT 4161 617 LT 4168 658 LT ST
2518 
3742 658 MT 3742 658 LT 3749 698 LT 4161 698 LT 4168 658 LT ST
2519 
(5) 3756 658 WT pop 0 originOffset 37 add RSS
2520 
4168 658 MT 4168 658 LT 4175 617 LT 4587 617 LT 4594 658 LT ST
2521 
4168 658 MT 4168 658 LT 4175 698 LT 4587 698 LT 4594 658 LT ST
2522 
(6) 4182 658 WT pop 0 originOffset 37 add RSS
2523 
4594 658 MT 4594 658 LT 4601 617 LT 5013 617 LT 5020 658 LT ST
2524 
4594 658 MT 4594 658 LT 4601 698 LT 5013 698 LT 5020 658 LT ST
2525 
(7) 4608 658 WT pop 0 originOffset 37 add RSS
2526 
5020 658 MT 5020 658 LT 5027 617 LT 5439 617 LT 5446 658 LT ST
2527 
5020 658 MT 5020 658 LT 5027 698 LT 5439 698 LT 5446 658 LT ST
2528 
(0) 5034 658 WT pop 0 originOffset 37 add RSS
2529 
5446 658 MT 5446 658 LT 5453 617 LT 5865 617 LT 5872 658 LT ST
2530 
5446 658 MT 5446 658 LT 5453 698 LT 5865 698 LT 5872 658 LT ST
2531 
(1) 5460 658 WT pop 0 originOffset 37 add RSS
2532 
5872 658 MT 5872 658 LT 5879 617 LT 6298 617 LT ST
2533 
5872 658 MT 5872 658 LT 5879 698 LT 6298 698 LT ST
2534 
(2) 5886 658 WT pop 0 originOffset 37 add RSS
2535 
3103 842 MT 6298 842 LS
2536 
3103 905 MT 3103 905 LT 6298 905 LT ST
2537 
3103 986 MT 3103 986 LT 6298 986 LT ST
2538 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
2539 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
2540 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
2541 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
2542 
3103 1274 MT 6298 1274 LS
2543 
% draw timeline
2544 
3146 4533 MT 3146 4570 LS
2545 
3188 4533 MT 3188 4570 LS
2546 
3231 4533 MT 3231 4570 LS
2547 
3273 4533 MT 3273 4570 LS
2548 
3316 4533 MT 3316 4570 LS
2549 
3359 4533 MT 3359 4570 LS
2550 
3401 4533 MT 3401 4570 LS
2551 
3444 4533 MT 3444 4570 LS
2552 
3486 4533 MT 3486 4570 LS
2553 
3572 4533 MT 3572 4570 LS
2554 
3614 4533 MT 3614 4570 LS
2555 
3657 4533 MT 3657 4570 LS
2556 
3699 4533 MT 3699 4570 LS
2557 
3742 4533 MT 3742 4570 LS
2558 
3785 4533 MT 3785 4570 LS
2559 
3827 4533 MT 3827 4570 LS
2560 
3870 4533 MT 3870 4570 LS
2561 
3912 4533 MT 3912 4570 LS
2562 
3529 4506 MT 3529 4570 LS
2563 
(160) 3529 4649 WT TS RSS
2564 
3998 4533 MT 3998 4570 LS
2565 
4040 4533 MT 4040 4570 LS
2566 
4083 4533 MT 4083 4570 LS
2567 
4125 4533 MT 4125 4570 LS
2568 
4168 4533 MT 4168 4570 LS
2569 
4211 4533 MT 4211 4570 LS
2570 
4253 4533 MT 4253 4570 LS
2571 
4296 4533 MT 4296 4570 LS
2572 
4338 4533 MT 4338 4570 LS
2573 
3955 4506 MT 3955 4570 LS
2574 
4424 4533 MT 4424 4570 LS
2575 
4466 4533 MT 4466 4570 LS
2576 
4509 4533 MT 4509 4570 LS
2577 
4551 4533 MT 4551 4570 LS
2578 
4594 4533 MT 4594 4570 LS
2579 
4637 4533 MT 4637 4570 LS
2580 
4679 4533 MT 4679 4570 LS
2581 
4722 4533 MT 4722 4570 LS
2582 
4764 4533 MT 4764 4570 LS
2583 
4381 4506 MT 4381 4570 LS
2584 
(180) 4381 4649 WT TS RSS
2585 
4850 4533 MT 4850 4570 LS
2586 
4892 4533 MT 4892 4570 LS
2587 
4935 4533 MT 4935 4570 LS
2588 
4977 4533 MT 4977 4570 LS
2589 
5020 4533 MT 5020 4570 LS
2590 
5063 4533 MT 5063 4570 LS
2591 
5105 4533 MT 5105 4570 LS
2592 
5148 4533 MT 5148 4570 LS
2593 
5190 4533 MT 5190 4570 LS
2594 
4807 4506 MT 4807 4570 LS
2595 
5276 4533 MT 5276 4570 LS
2596 
5318 4533 MT 5318 4570 LS
2597 
5361 4533 MT 5361 4570 LS
2598 
5403 4533 MT 5403 4570 LS
2599 
5446 4533 MT 5446 4570 LS
2600 
5489 4533 MT 5489 4570 LS
2601 
5531 4533 MT 5531 4570 LS
2602 
5574 4533 MT 5574 4570 LS
2603 
5616 4533 MT 5616 4570 LS
2604 
5233 4506 MT 5233 4570 LS
2605 
(200) 5233 4649 WT TS RSS
2606 
5702 4533 MT 5702 4570 LS
2607 
5744 4533 MT 5744 4570 LS
2608 
5787 4533 MT 5787 4570 LS
2609 
5829 4533 MT 5829 4570 LS
2610 
5872 4533 MT 5872 4570 LS
2611 
5915 4533 MT 5915 4570 LS
2612 
5957 4533 MT 5957 4570 LS
2613 
6000 4533 MT 6000 4570 LS
2614 
6042 4533 MT 6042 4570 LS
2615 
5659 4506 MT 5659 4570 LS
2616 
6128 4533 MT 6128 4570 LS
2617 
6170 4533 MT 6170 4570 LS
2618 
6213 4533 MT 6213 4570 LS
2619 
6255 4533 MT 6255 4570 LS
2620 
6298 4533 MT 6298 4570 LS
2621 
6341 4533 MT 6341 4570 LS
2622 
6383 4533 MT 6383 4570 LS
2623 
6426 4533 MT 6426 4570 LS
2624 
6468 4533 MT 6468 4570 LS
2625 
6085 4506 MT 6085 4570 LS
2626 
(220) 6085 4649 WT TS RSS
2627 
% draw grid
2628 
3529 300 MT 3529 4506 LS
2629 
3955 300 MT 3955 4506 LS
2630 
4381 300 MT 4381 4506 LS
2631 
4807 300 MT 4807 4506 LS
2632 
5233 300 MT 5233 4506 LS
2633 
5659 300 MT 5659 4506 LS
2634 
6085 300 MT 6085 4506 LS
2635 
% draw waveforms
2636 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) 3066 409 WT TSE RSS
2637 
3522 300 MT 3536 300 LS
2638 
3948 300 MT 3962 300 LS
2639 
4374 300 MT 4388 300 LS
2640 
4800 300 MT 4814 300 LS
2641 
5226 300 MT 5240 300 LS
2642 
5652 300 MT 5666 300 LS
2643 
6078 300 MT 6092 300 LS
2644 
3103 329 MT 3103 329 LT 6298 329 LT ST
2645 
3103 410 MT 3103 410 LT 6298 410 LT ST
2646 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
2647 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) 3066 553 WT TSE RSS
2648 
3522 444 MT 3536 444 LS
2649 
3948 444 MT 3962 444 LS
2650 
4374 444 MT 4388 444 LS
2651 
4800 444 MT 4814 444 LS
2652 
5226 444 MT 5240 444 LS
2653 
5652 444 MT 5666 444 LS
2654 
6078 444 MT 6092 444 LS
2655 
3103 473 MT 3103 473 LT 3309 473 LT 3316 514 LT ST
2656 
3103 554 MT 3103 554 LT 3309 554 LT 3316 514 LT ST
2657 
(4) 3117 514 WT pop 0 originOffset 37 add RSS
2658 
3316 514 MT 3316 514 LT 3323 473 LT 3735 473 LT 3742 514 LT ST
2659 
3316 514 MT 3316 514 LT 3323 554 LT 3735 554 LT 3742 514 LT ST
2660 
(5) 3330 514 WT pop 0 originOffset 37 add RSS
2661 
3742 514 MT 3742 514 LT 3749 473 LT 4161 473 LT 4168 514 LT ST
2662 
3742 514 MT 3742 514 LT 3749 554 LT 4161 554 LT 4168 514 LT ST
2663 
(6) 3756 514 WT pop 0 originOffset 37 add RSS
2664 
4168 514 MT 4168 514 LT 4175 473 LT 4587 473 LT 4594 514 LT ST
2665 
4168 514 MT 4168 514 LT 4175 554 LT 4587 554 LT 4594 514 LT ST
2666 
(7) 4182 514 WT pop 0 originOffset 37 add RSS
2667 
4594 514 MT 4594 514 LT 4601 473 LT 5013 473 LT 5020 514 LT ST
2668 
4594 514 MT 4594 514 LT 4601 554 LT 5013 554 LT 5020 514 LT ST
2669 
(0) 4608 514 WT pop 0 originOffset 37 add RSS
2670 
5020 514 MT 5020 514 LT 5027 473 LT 5439 473 LT 5446 514 LT ST
2671 
5020 514 MT 5020 514 LT 5027 554 LT 5439 554 LT 5446 514 LT ST
2672 
(1) 5034 514 WT pop 0 originOffset 37 add RSS
2673 
5446 514 MT 5446 514 LT 5453 473 LT 5865 473 LT 5872 514 LT ST
2674 
5446 514 MT 5446 514 LT 5453 554 LT 5865 554 LT 5872 514 LT ST
2675 
(2) 5460 514 WT pop 0 originOffset 37 add RSS
2676 
5872 514 MT 5872 514 LT 5879 473 LT 6298 473 LT ST
2677 
5872 514 MT 5872 514 LT 5879 554 LT 6298 554 LT ST
2678 
(3) 5886 514 WT pop 0 originOffset 37 add RSS
2679 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) 3066 697 WT TSE RSS
2680 
3522 588 MT 3536 588 LS
2681 
3948 588 MT 3962 588 LS
2682 
4374 588 MT 4388 588 LS
2683 
4800 588 MT 4814 588 LS
2684 
5226 588 MT 5240 588 LS
2685 
5652 588 MT 5666 588 LS
2686 
6078 588 MT 6092 588 LS
2687 
3103 617 MT 3103 617 LT 3309 617 LT 3316 658 LT ST
2688 
3103 698 MT 3103 698 LT 3309 698 LT 3316 658 LT ST
2689 
(3) 3117 658 WT pop 0 originOffset 37 add RSS
2690 
3316 658 MT 3316 658 LT 3323 617 LT 3735 617 LT 3742 658 LT ST
2691 
3316 658 MT 3316 658 LT 3323 698 LT 3735 698 LT 3742 658 LT ST
2692 
(4) 3330 658 WT pop 0 originOffset 37 add RSS
2693 
3742 658 MT 3742 658 LT 3749 617 LT 4161 617 LT 4168 658 LT ST
2694 
3742 658 MT 3742 658 LT 3749 698 LT 4161 698 LT 4168 658 LT ST
2695 
(5) 3756 658 WT pop 0 originOffset 37 add RSS
2696 
4168 658 MT 4168 658 LT 4175 617 LT 4587 617 LT 4594 658 LT ST
2697 
4168 658 MT 4168 658 LT 4175 698 LT 4587 698 LT 4594 658 LT ST
2698 
(6) 4182 658 WT pop 0 originOffset 37 add RSS
2699 
4594 658 MT 4594 658 LT 4601 617 LT 5013 617 LT 5020 658 LT ST
2700 
4594 658 MT 4594 658 LT 4601 698 LT 5013 698 LT 5020 658 LT ST
2701 
(7) 4608 658 WT pop 0 originOffset 37 add RSS
2702 
5020 658 MT 5020 658 LT 5027 617 LT 5439 617 LT 5446 658 LT ST
2703 
5020 658 MT 5020 658 LT 5027 698 LT 5439 698 LT 5446 658 LT ST
2704 
(0) 5034 658 WT pop 0 originOffset 37 add RSS
2705 
5446 658 MT 5446 658 LT 5453 617 LT 5865 617 LT 5872 658 LT ST
2706 
5446 658 MT 5446 658 LT 5453 698 LT 5865 698 LT 5872 658 LT ST
2707 
(1) 5460 658 WT pop 0 originOffset 37 add RSS
2708 
5872 658 MT 5872 658 LT 5879 617 LT 6298 617 LT ST
2709 
5872 658 MT 5872 658 LT 5879 698 LT 6298 698 LT ST
2710 
(2) 5886 658 WT pop 0 originOffset 37 add RSS
2711 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) 3066 841 WT TSE RSS
2712 
3522 732 MT 3536 732 LS
2713 
3948 732 MT 3962 732 LS
2714 
4374 732 MT 4388 732 LS
2715 
4800 732 MT 4814 732 LS
2716 
5226 732 MT 5240 732 LS
2717 
5652 732 MT 5666 732 LS
2718 
6078 732 MT 6092 732 LS
2719 
3103 842 MT 6298 842 LS
2720 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) 3066 985 WT TSE RSS
2721 
3522 876 MT 3536 876 LS
2722 
3948 876 MT 3962 876 LS
2723 
4374 876 MT 4388 876 LS
2724 
4800 876 MT 4814 876 LS
2725 
5226 876 MT 5240 876 LS
2726 
5652 876 MT 5666 876 LS
2727 
6078 876 MT 6092 876 LS
2728 
3103 905 MT 3103 905 LT 6298 905 LT ST
2729 
3103 986 MT 3103 986 LT 6298 986 LT ST
2730 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
2731 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) 3066 1129 WT TSE RSS
2732 
3522 1020 MT 3536 1020 LS
2733 
3948 1020 MT 3962 1020 LS
2734 
4374 1020 MT 4388 1020 LS
2735 
4800 1020 MT 4814 1020 LS
2736 
5226 1020 MT 5240 1020 LS
2737 
5652 1020 MT 5666 1020 LS
2738 
6078 1020 MT 6092 1020 LS
2739 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
2740 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
2741 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
2742 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) 3066 1273 WT TSE RSS
2743 
3522 1164 MT 3536 1164 LS
2744 
3948 1164 MT 3962 1164 LS
2745 
4374 1164 MT 4388 1164 LS
2746 
4800 1164 MT 4814 1164 LS
2747 
5226 1164 MT 5240 1164 LS
2748 
5652 1164 MT 5666 1164 LS
2749 
6078 1164 MT 6092 1164 LS
2750 
3103 1274 MT 6298 1274 LS
2751 
% draw footer
2752 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 3 Page: 6) 300 4799 WT TSW RSS
2753 
grestore
2754 
showpage
2755 
%%Page: 7 7
2756 
gsave
2757 
90 rotate 0.12 dup neg scale
2758 
% dump string table
2759 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
2760 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
2761 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
2762 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
2763 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
2764 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
2765 
/ARC {5 -2 roll SX 5 2 roll arc} def
2766 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
2767 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
2768 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
2769 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
2770 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
2771 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
2772 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
2773 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
2774 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
2775 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
2776 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
2777 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
2778 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
2779 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
2780 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
2781 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
2782 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
2783 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
2784 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
2785 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
2786 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
2787 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
2788 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
2789 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
2790 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
2791 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
2792 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
2793 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
2794 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
2795 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
2796 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
2797 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
2798 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
2799 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
2800 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
2801 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
2802 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
2803 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
2804 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
2805 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
2806 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
2807 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
2808 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
2809 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
2810 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
2811 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
2812 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
2813 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
2814 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
2815 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
2816 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
2817 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
2818 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
2819 
% draw waveform shading
2820 
[] 0 SD
2821 
2.995 setlinewidth
2822 
 
2823 
 
2824 
 
2825 
3103 370 MT 6298 370 LS
2826 
3103 554 MT 6298 554 LS
2827 
3103 698 MT 6298 698 LS
2828 
3103 761 MT 3103 761 LT 6298 761 LT ST
2829 
3103 842 MT 3103 842 LT 6298 842 LT ST
2830 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
2831 
3103 986 MT 6298 986 LS
2832 
3103 1050 MT 6298 1050 LS
2833 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
2834 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
2835 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
2836 
3103 1418 MT 6298 1418 LS
2837 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
2838 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
2839 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
2840 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
2841 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
2842 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
2843 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
2844 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
2845 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
2846 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
2847 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
2848 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
2849 
3103 2138 MT 6298 2138 LS
2850 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
2851 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
2852 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
2853 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
2854 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
2855 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
2856 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
2857 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
2858 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
2859 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
2860 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
2861 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
2862 
3103 2858 MT 6298 2858 LS
2863 
3103 3002 MT 6298 3002 LS
2864 
3103 3146 MT 6298 3146 LS
2865 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
2866 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
2867 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
2868 
3103 3434 MT 6298 3434 LS
2869 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
2870 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
2871 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
2872 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
2873 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
2874 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
2875 
3103 3866 MT 6298 3866 LS
2876 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
2877 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
2878 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
2879 
3103 4154 MT 6298 4154 LS
2880 
3103 4258 MT 6298 4258 LS
2881 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
2882 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
2883 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
2884 
% draw timeline
2885 
3145 4533 MT 3145 4570 LS
2886 
3187 4533 MT 3187 4570 LS
2887 
3230 4533 MT 3230 4570 LS
2888 
3272 4533 MT 3272 4570 LS
2889 
3359 4533 MT 3359 4570 LS
2890 
3401 4533 MT 3401 4570 LS
2891 
3444 4533 MT 3444 4570 LS
2892 
3486 4533 MT 3486 4570 LS
2893 
3529 4533 MT 3529 4570 LS
2894 
3572 4533 MT 3572 4570 LS
2895 
3614 4533 MT 3614 4570 LS
2896 
3657 4533 MT 3657 4570 LS
2897 
3699 4533 MT 3699 4570 LS
2898 
3316 4506 MT 3316 4570 LS
2899 
3785 4533 MT 3785 4570 LS
2900 
3827 4533 MT 3827 4570 LS
2901 
3870 4533 MT 3870 4570 LS
2902 
3912 4533 MT 3912 4570 LS
2903 
3955 4533 MT 3955 4570 LS
2904 
3998 4533 MT 3998 4570 LS
2905 
4040 4533 MT 4040 4570 LS
2906 
4083 4533 MT 4083 4570 LS
2907 
4125 4533 MT 4125 4570 LS
2908 
3742 4506 MT 3742 4570 LS
2909 
(240) 3742 4649 WT TS RSS
2910 
4211 4533 MT 4211 4570 LS
2911 
4253 4533 MT 4253 4570 LS
2912 
4296 4533 MT 4296 4570 LS
2913 
4338 4533 MT 4338 4570 LS
2914 
4381 4533 MT 4381 4570 LS
2915 
4424 4533 MT 4424 4570 LS
2916 
4466 4533 MT 4466 4570 LS
2917 
4509 4533 MT 4509 4570 LS
2918 
4551 4533 MT 4551 4570 LS
2919 
4168 4506 MT 4168 4570 LS
2920 
4637 4533 MT 4637 4570 LS
2921 
4679 4533 MT 4679 4570 LS
2922 
4722 4533 MT 4722 4570 LS
2923 
4764 4533 MT 4764 4570 LS
2924 
4807 4533 MT 4807 4570 LS
2925 
4850 4533 MT 4850 4570 LS
2926 
4892 4533 MT 4892 4570 LS
2927 
4935 4533 MT 4935 4570 LS
2928 
4977 4533 MT 4977 4570 LS
2929 
4594 4506 MT 4594 4570 LS
2930 
(260) 4594 4649 WT TS RSS
2931 
5063 4533 MT 5063 4570 LS
2932 
5105 4533 MT 5105 4570 LS
2933 
5148 4533 MT 5148 4570 LS
2934 
5190 4533 MT 5190 4570 LS
2935 
5233 4533 MT 5233 4570 LS
2936 
5276 4533 MT 5276 4570 LS
2937 
5318 4533 MT 5318 4570 LS
2938 
5361 4533 MT 5361 4570 LS
2939 
5403 4533 MT 5403 4570 LS
2940 
5020 4506 MT 5020 4570 LS
2941 
5489 4533 MT 5489 4570 LS
2942 
5531 4533 MT 5531 4570 LS
2943 
5574 4533 MT 5574 4570 LS
2944 
5616 4533 MT 5616 4570 LS
2945 
5659 4533 MT 5659 4570 LS
2946 
5702 4533 MT 5702 4570 LS
2947 
5744 4533 MT 5744 4570 LS
2948 
5787 4533 MT 5787 4570 LS
2949 
5829 4533 MT 5829 4570 LS
2950 
5446 4506 MT 5446 4570 LS
2951 
(280) 5446 4649 WT TS RSS
2952 
5915 4533 MT 5915 4570 LS
2953 
5957 4533 MT 5957 4570 LS
2954 
6000 4533 MT 6000 4570 LS
2955 
6042 4533 MT 6042 4570 LS
2956 
6085 4533 MT 6085 4570 LS
2957 
6128 4533 MT 6128 4570 LS
2958 
6170 4533 MT 6170 4570 LS
2959 
6213 4533 MT 6213 4570 LS
2960 
6255 4533 MT 6255 4570 LS
2961 
5872 4506 MT 5872 4570 LS
2962 
6341 4533 MT 6341 4570 LS
2963 
6383 4533 MT 6383 4570 LS
2964 
6426 4533 MT 6426 4570 LS
2965 
6468 4533 MT 6468 4570 LS
2966 
6511 4533 MT 6511 4570 LS
2967 
6554 4533 MT 6554 4570 LS
2968 
6596 4533 MT 6596 4570 LS
2969 
6639 4533 MT 6639 4570 LS
2970 
6681 4533 MT 6681 4570 LS
2971 
6298 4506 MT 6298 4570 LS
2972 
(300) 6298 4649 WT TS RSS
2973 
% draw grid
2974 
3316 300 MT 3316 4506 LS
2975 
3742 300 MT 3742 4506 LS
2976 
4168 300 MT 4168 4506 LS
2977 
4594 300 MT 4594 4506 LS
2978 
5020 300 MT 5020 4506 LS
2979 
5446 300 MT 5446 4506 LS
2980 
5872 300 MT 5872 4506 LS
2981 
6298 300 MT 6298 4506 LS
2982 
% draw waveforms
2983 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) 3066 409 WT TSE RSS
2984 
3309 300 MT 3323 300 LS
2985 
3735 300 MT 3749 300 LS
2986 
4161 300 MT 4175 300 LS
2987 
4587 300 MT 4601 300 LS
2988 
5013 300 MT 5027 300 LS
2989 
5439 300 MT 5453 300 LS
2990 
5865 300 MT 5879 300 LS
2991 
6291 300 MT 6305 300 LS
2992 
3103 370 MT 6298 370 LS
2993 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) 3066 553 WT TSE RSS
2994 
3309 444 MT 3323 444 LS
2995 
3735 444 MT 3749 444 LS
2996 
4161 444 MT 4175 444 LS
2997 
4587 444 MT 4601 444 LS
2998 
5013 444 MT 5027 444 LS
2999 
5439 444 MT 5453 444 LS
3000 
5865 444 MT 5879 444 LS
3001 
6291 444 MT 6305 444 LS
3002 
3103 554 MT 6298 554 LS
3003 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) 3066 697 WT TSE RSS
3004 
3309 588 MT 3323 588 LS
3005 
3735 588 MT 3749 588 LS
3006 
4161 588 MT 4175 588 LS
3007 
4587 588 MT 4601 588 LS
3008 
5013 588 MT 5027 588 LS
3009 
5439 588 MT 5453 588 LS
3010 
5865 588 MT 5879 588 LS
3011 
6291 588 MT 6305 588 LS
3012 
3103 698 MT 6298 698 LS
3013 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) 3066 841 WT TSE RSS
3014 
3309 732 MT 3323 732 LS
3015 
3735 732 MT 3749 732 LS
3016 
4161 732 MT 4175 732 LS
3017 
4587 732 MT 4601 732 LS
3018 
5013 732 MT 5027 732 LS
3019 
5439 732 MT 5453 732 LS
3020 
5865 732 MT 5879 732 LS
3021 
6291 732 MT 6305 732 LS
3022 
3103 761 MT 3103 761 LT 6298 761 LT ST
3023 
3103 842 MT 3103 842 LT 6298 842 LT ST
3024 
(14610000) 3117 802 WT pop 0 originOffset 37 add RSS
3025 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) 3066 985 WT TSE RSS
3026 
3309 876 MT 3323 876 LS
3027 
3735 876 MT 3749 876 LS
3028 
4161 876 MT 4175 876 LS
3029 
4587 876 MT 4601 876 LS
3030 
5013 876 MT 5027 876 LS
3031 
5439 876 MT 5453 876 LS
3032 
5865 876 MT 5879 876 LS
3033 
6291 876 MT 6305 876 LS
3034 
3103 986 MT 6298 986 LS
3035 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) 3066 1129 WT TSE RSS
3036 
3309 1020 MT 3323 1020 LS
3037 
3735 1020 MT 3749 1020 LS
3038 
4161 1020 MT 4175 1020 LS
3039 
4587 1020 MT 4601 1020 LS
3040 
5013 1020 MT 5027 1020 LS
3041 
5439 1020 MT 5453 1020 LS
3042 
5865 1020 MT 5879 1020 LS
3043 
6291 1020 MT 6305 1020 LS
3044 
3103 1050 MT 6298 1050 LS
3045 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) 3066 1273 WT TSE RSS
3046 
3309 1164 MT 3323 1164 LS
3047 
3735 1164 MT 3749 1164 LS
3048 
4161 1164 MT 4175 1164 LS
3049 
4587 1164 MT 4601 1164 LS
3050 
5013 1164 MT 5027 1164 LS
3051 
5439 1164 MT 5453 1164 LS
3052 
5865 1164 MT 5879 1164 LS
3053 
6291 1164 MT 6305 1164 LS
3054 
3103 1193 MT 3103 1193 LT 6298 1193 LT ST
3055 
3103 1274 MT 3103 1274 LT 6298 1274 LT ST
3056 
(14610000) 3117 1234 WT pop 0 originOffset 37 add RSS
3057 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) 3066 1417 WT TSE RSS
3058 
3309 1308 MT 3323 1308 LS
3059 
3735 1308 MT 3749 1308 LS
3060 
4161 1308 MT 4175 1308 LS
3061 
4587 1308 MT 4601 1308 LS
3062 
5013 1308 MT 5027 1308 LS
3063 
5439 1308 MT 5453 1308 LS
3064 
5865 1308 MT 5879 1308 LS
3065 
6291 1308 MT 6305 1308 LS
3066 
3103 1418 MT 6298 1418 LS
3067 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) 3066 1561 WT TSE RSS
3068 
3309 1452 MT 3323 1452 LS
3069 
3735 1452 MT 3749 1452 LS
3070 
4161 1452 MT 4175 1452 LS
3071 
4587 1452 MT 4601 1452 LS
3072 
5013 1452 MT 5027 1452 LS
3073 
5439 1452 MT 5453 1452 LS
3074 
5865 1452 MT 5879 1452 LS
3075 
6291 1452 MT 6305 1452 LS
3076 
3103 1481 MT 3103 1481 LT 6298 1481 LT ST
3077 
3103 1562 MT 3103 1562 LT 6298 1562 LT ST
3078 
(00000000) 3117 1522 WT pop 0 originOffset 37 add RSS
3079 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) 3066 1705 WT TSE RSS
3080 
3309 1596 MT 3323 1596 LS
3081 
3735 1596 MT 3749 1596 LS
3082 
4161 1596 MT 4175 1596 LS
3083 
4587 1596 MT 4601 1596 LS
3084 
5013 1596 MT 5027 1596 LS
3085 
5439 1596 MT 5453 1596 LS
3086 
5865 1596 MT 5879 1596 LS
3087 
6291 1596 MT 6305 1596 LS
3088 
3103 1625 MT 3103 1625 LT 6298 1625 LT ST
3089 
3103 1706 MT 3103 1706 LT 6298 1706 LT ST
3090 
(0) 3117 1666 WT pop 0 originOffset 37 add RSS
3091 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) 3066 1849 WT TSE RSS
3092 
3309 1740 MT 3323 1740 LS
3093 
3735 1740 MT 3749 1740 LS
3094 
4161 1740 MT 4175 1740 LS
3095 
4587 1740 MT 4601 1740 LS
3096 
5013 1740 MT 5027 1740 LS
3097 
5439 1740 MT 5453 1740 LS
3098 
5865 1740 MT 5879 1740 LS
3099 
6291 1740 MT 6305 1740 LS
3100 
3103 1769 MT 3103 1769 LT 6298 1769 LT ST
3101 
3103 1850 MT 3103 1850 LT 6298 1850 LT ST
3102 
(0) 3117 1810 WT pop 0 originOffset 37 add RSS
3103 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) 3066 1993 WT TSE RSS
3104 
3309 1884 MT 3323 1884 LS
3105 
3735 1884 MT 3749 1884 LS
3106 
4161 1884 MT 4175 1884 LS
3107 
4587 1884 MT 4601 1884 LS
3108 
5013 1884 MT 5027 1884 LS
3109 
5439 1884 MT 5453 1884 LS
3110 
5865 1884 MT 5879 1884 LS
3111 
6291 1884 MT 6305 1884 LS
3112 
3103 1913 MT 3103 1913 LT 6298 1913 LT ST
3113 
3103 1994 MT 3103 1994 LT 6298 1994 LT ST
3114 
(0) 3117 1954 WT pop 0 originOffset 37 add RSS
3115 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) 3066 2137 WT TSE RSS
3116 
3309 2028 MT 3323 2028 LS
3117 
3735 2028 MT 3749 2028 LS
3118 
4161 2028 MT 4175 2028 LS
3119 
4587 2028 MT 4601 2028 LS
3120 
5013 2028 MT 5027 2028 LS
3121 
5439 2028 MT 5453 2028 LS
3122 
5865 2028 MT 5879 2028 LS
3123 
6291 2028 MT 6305 2028 LS
3124 
3103 2138 MT 6298 2138 LS
3125 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) 3066 2281 WT TSE RSS
3126 
3309 2172 MT 3323 2172 LS
3127 
3735 2172 MT 3749 2172 LS
3128 
4161 2172 MT 4175 2172 LS
3129 
4587 2172 MT 4601 2172 LS
3130 
5013 2172 MT 5027 2172 LS
3131 
5439 2172 MT 5453 2172 LS
3132 
5865 2172 MT 5879 2172 LS
3133 
6291 2172 MT 6305 2172 LS
3134 
3103 2201 MT 3103 2201 LT 6298 2201 LT ST
3135 
3103 2282 MT 3103 2282 LT 6298 2282 LT ST
3136 
(0) 3117 2242 WT pop 0 originOffset 37 add RSS
3137 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) 3066 2425 WT TSE RSS
3138 
3309 2316 MT 3323 2316 LS
3139 
3735 2316 MT 3749 2316 LS
3140 
4161 2316 MT 4175 2316 LS
3141 
4587 2316 MT 4601 2316 LS
3142 
5013 2316 MT 5027 2316 LS
3143 
5439 2316 MT 5453 2316 LS
3144 
5865 2316 MT 5879 2316 LS
3145 
6291 2316 MT 6305 2316 LS
3146 
3103 2345 MT 3103 2345 LT 6298 2345 LT ST
3147 
3103 2426 MT 3103 2426 LT 6298 2426 LT ST
3148 
(01) 3117 2386 WT pop 0 originOffset 37 add RSS
3149 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) 3066 2569 WT TSE RSS
3150 
3309 2460 MT 3323 2460 LS
3151 
3735 2460 MT 3749 2460 LS
3152 
4161 2460 MT 4175 2460 LS
3153 
4587 2460 MT 4601 2460 LS
3154 
5013 2460 MT 5027 2460 LS
3155 
5439 2460 MT 5453 2460 LS
3156 
5865 2460 MT 5879 2460 LS
3157 
6291 2460 MT 6305 2460 LS
3158 
3103 2489 MT 3103 2489 LT 6298 2489 LT ST
3159 
3103 2570 MT 3103 2570 LT 6298 2570 LT ST
3160 
(00) 3117 2530 WT pop 0 originOffset 37 add RSS
3161 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) 3066 2713 WT TSE RSS
3162 
3309 2604 MT 3323 2604 LS
3163 
3735 2604 MT 3749 2604 LS
3164 
4161 2604 MT 4175 2604 LS
3165 
4587 2604 MT 4601 2604 LS
3166 
5013 2604 MT 5027 2604 LS
3167 
5439 2604 MT 5453 2604 LS
3168 
5865 2604 MT 5879 2604 LS
3169 
6291 2604 MT 6305 2604 LS
3170 
3103 2633 MT 3103 2633 LT 6298 2633 LT ST
3171 
3103 2714 MT 3103 2714 LT 6298 2714 LT ST
3172 
(03) 3117 2674 WT pop 0 originOffset 37 add RSS
3173 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) 3066 2857 WT TSE RSS
3174 
3309 2748 MT 3323 2748 LS
3175 
3735 2748 MT 3749 2748 LS
3176 
4161 2748 MT 4175 2748 LS
3177 
4587 2748 MT 4601 2748 LS
3178 
5013 2748 MT 5027 2748 LS
3179 
5439 2748 MT 5453 2748 LS
3180 
5865 2748 MT 5879 2748 LS
3181 
6291 2748 MT 6305 2748 LS
3182 
3103 2858 MT 6298 2858 LS
3183 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) 3066 3001 WT TSE RSS
3184 
3309 2892 MT 3323 2892 LS
3185 
3735 2892 MT 3749 2892 LS
3186 
4161 2892 MT 4175 2892 LS
3187 
4587 2892 MT 4601 2892 LS
3188 
5013 2892 MT 5027 2892 LS
3189 
5439 2892 MT 5453 2892 LS
3190 
5865 2892 MT 5879 2892 LS
3191 
6291 2892 MT 6305 2892 LS
3192 
3103 3002 MT 6298 3002 LS
3193 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) 3066 3145 WT TSE RSS
3194 
3309 3036 MT 3323 3036 LS
3195 
3735 3036 MT 3749 3036 LS
3196 
4161 3036 MT 4175 3036 LS
3197 
4587 3036 MT 4601 3036 LS
3198 
5013 3036 MT 5027 3036 LS
3199 
5439 3036 MT 5453 3036 LS
3200 
5865 3036 MT 5879 3036 LS
3201 
6291 3036 MT 6305 3036 LS
3202 
3103 3146 MT 6298 3146 LS
3203 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) 3066 3289 WT TSE RSS
3204 
3309 3180 MT 3323 3180 LS
3205 
3735 3180 MT 3749 3180 LS
3206 
4161 3180 MT 4175 3180 LS
3207 
4587 3180 MT 4601 3180 LS
3208 
5013 3180 MT 5027 3180 LS
3209 
5439 3180 MT 5453 3180 LS
3210 
5865 3180 MT 5879 3180 LS
3211 
6291 3180 MT 6305 3180 LS
3212 
3103 3209 MT 3103 3209 LT 6298 3209 LT ST
3213 
3103 3290 MT 3103 3290 LT 6298 3290 LT ST
3214 
(0) 3117 3250 WT pop 0 originOffset 37 add RSS
3215 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) 3066 3433 WT TSE RSS
3216 
3309 3324 MT 3323 3324 LS
3217 
3735 3324 MT 3749 3324 LS
3218 
4161 3324 MT 4175 3324 LS
3219 
4587 3324 MT 4601 3324 LS
3220 
5013 3324 MT 5027 3324 LS
3221 
5439 3324 MT 5453 3324 LS
3222 
5865 3324 MT 5879 3324 LS
3223 
6291 3324 MT 6305 3324 LS
3224 
3103 3434 MT 6298 3434 LS
3225 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) 3066 3577 WT TSE RSS
3226 
3309 3468 MT 3323 3468 LS
3227 
3735 3468 MT 3749 3468 LS
3228 
4161 3468 MT 4175 3468 LS
3229 
4587 3468 MT 4601 3468 LS
3230 
5013 3468 MT 5027 3468 LS
3231 
5439 3468 MT 5453 3468 LS
3232 
5865 3468 MT 5879 3468 LS
3233 
6291 3468 MT 6305 3468 LS
3234 
3103 3497 MT 3103 3497 LT 6298 3497 LT ST
3235 
3103 3578 MT 3103 3578 LT 6298 3578 LT ST
3236 
(0) 3117 3538 WT pop 0 originOffset 37 add RSS
3237 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) 3066 3721 WT TSE RSS
3238 
3309 3612 MT 3323 3612 LS
3239 
3735 3612 MT 3749 3612 LS
3240 
4161 3612 MT 4175 3612 LS
3241 
4587 3612 MT 4601 3612 LS
3242 
5013 3612 MT 5027 3612 LS
3243 
5439 3612 MT 5453 3612 LS
3244 
5865 3612 MT 5879 3612 LS
3245 
6291 3612 MT 6305 3612 LS
3246 
3103 3641 MT 3103 3641 LT 6298 3641 LT ST
3247 
3103 3722 MT 3103 3722 LT 6298 3722 LT ST
3248 
(0) 3117 3682 WT pop 0 originOffset 37 add RSS
3249 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) 3066 3865 WT TSE RSS
3250 
3309 3756 MT 3323 3756 LS
3251 
3735 3756 MT 3749 3756 LS
3252 
4161 3756 MT 4175 3756 LS
3253 
4587 3756 MT 4601 3756 LS
3254 
5013 3756 MT 5027 3756 LS
3255 
5439 3756 MT 5453 3756 LS
3256 
5865 3756 MT 5879 3756 LS
3257 
6291 3756 MT 6305 3756 LS
3258 
3103 3866 MT 6298 3866 LS
3259 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) 3066 4009 WT TSE RSS
3260 
3309 3900 MT 3323 3900 LS
3261 
3735 3900 MT 3749 3900 LS
3262 
4161 3900 MT 4175 3900 LS
3263 
4587 3900 MT 4601 3900 LS
3264 
5013 3900 MT 5027 3900 LS
3265 
5439 3900 MT 5453 3900 LS
3266 
5865 3900 MT 5879 3900 LS
3267 
6291 3900 MT 6305 3900 LS
3268 
3103 3929 MT 3103 3929 LT 6298 3929 LT ST
3269 
3103 4010 MT 3103 4010 LT 6298 4010 LT ST
3270 
(0) 3117 3970 WT pop 0 originOffset 37 add RSS
3271 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) 3066 4153 WT TSE RSS
3272 
3309 4044 MT 3323 4044 LS
3273 
3735 4044 MT 3749 4044 LS
3274 
4161 4044 MT 4175 4044 LS
3275 
4587 4044 MT 4601 4044 LS
3276 
5013 4044 MT 5027 4044 LS
3277 
5439 4044 MT 5453 4044 LS
3278 
5865 4044 MT 5879 4044 LS
3279 
6291 4044 MT 6305 4044 LS
3280 
3103 4154 MT 6298 4154 LS
3281 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) 3066 4297 WT TSE RSS
3282 
3309 4188 MT 3323 4188 LS
3283 
3735 4188 MT 3749 4188 LS
3284 
4161 4188 MT 4175 4188 LS
3285 
4587 4188 MT 4601 4188 LS
3286 
5013 4188 MT 5027 4188 LS
3287 
5439 4188 MT 5453 4188 LS
3288 
5865 4188 MT 5879 4188 LS
3289 
6291 4188 MT 6305 4188 LS
3290 
3103 4258 MT 6298 4258 LS
3291 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) 3066 4441 WT TSE RSS
3292 
3309 4332 MT 3323 4332 LS
3293 
3735 4332 MT 3749 4332 LS
3294 
4161 4332 MT 4175 4332 LS
3295 
4587 4332 MT 4601 4332 LS
3296 
5013 4332 MT 5027 4332 LS
3297 
5439 4332 MT 5453 4332 LS
3298 
5865 4332 MT 5879 4332 LS
3299 
6291 4332 MT 6305 4332 LS
3300 
3103 4361 MT 3103 4361 LT 6298 4361 LT ST
3301 
3103 4442 MT 3103 4442 LT 6298 4442 LT ST
3302 
(00000000) 3117 4402 WT pop 0 originOffset 37 add RSS
3303 
% draw footer
3304 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 4 Page: 7) 300 4799 WT TSW RSS
3305 
grestore
3306 
showpage
3307 
%%Page: 8 8
3308 
gsave
3309 
90 rotate 0.12 dup neg scale
3310 
% dump string table
3311 
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
3312 
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
3313 
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
3314 
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
3315 
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
3316 
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
3317 
/ARC {5 -2 roll SX 5 2 roll arc} def
3318 
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3103 def/REdge 5699 def/LabelWidth 3066 def
3319 
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
3320 
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
3321 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/alu_op) MLW
3322 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_addrofs) MLW
3323 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_op) MLW
3324 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/branch_taken) MLW
3325 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/clk) MLW
3326 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/comp_op) MLW
3327 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_limm) MLW
3328 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/cust5_op) MLW
3329 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/du_hwbkpt) MLW
3330 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_freeze) MLW
3331 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_insn) MLW
3332 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_macrc_op) MLW
3333 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/ex_void) MLW
3334 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/except_illegal) MLW
3335 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/flushpipe) MLW
3336 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/force_dslot_fetch) MLW
3337 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_freeze) MLW
3338 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_insn) MLW
3339 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_macrc_op) MLW
3340 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/id_void) MLW
3341 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/if_insn) MLW
3342 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/imm_signextend) MLW
3343 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_addrofs) MLW
3344 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/lsu_op) MLW
3345 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/mac_op) MLW
3346 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/multicycle) MLW
3347 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/no_more_dslot) MLW
3348 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/pre_branch_op) MLW
3349 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addra) MLW
3350 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrb) MLW
3351 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_addrw) MLW
3352 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rda) MLW
3353 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rf_rdb) MLW
3354 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfe) MLW
3355 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rfwb_op) MLW
3356 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/rst) MLW
3357 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_a) MLW
3358 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_b) MLW
3359 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sel_imm) MLW
3360 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/shrot_op) MLW
3361 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_syscall) MLW
3362 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/sig_trap) MLW
3363 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/simm) MLW
3364 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) MLW
3365 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) MLW
3366 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) MLW
3367 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) MLW
3368 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) MLW
3369 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) MLW
3370 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) MLW
3371 
% draw waveform shading
3372 
[] 0 SD
3373 
2.995 setlinewidth
3374 
 
3375 
 
3376 
 
3377 
3103 329 MT 3103 329 LT 6298 329 LT ST
3378 
3103 410 MT 3103 410 LT 6298 410 LT ST
3379 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
3380 
3103 473 MT 3103 473 LT 3522 473 LT 3529 514 LT ST
3381 
3103 554 MT 3103 554 LT 3522 554 LT 3529 514 LT ST
3382 
(4) 3117 514 WT pop 0 originOffset 37 add RSS
3383 
3529 514 MT 3529 514 LT 3536 473 LT 3948 473 LT 3955 514 LT ST
3384 
3529 514 MT 3529 514 LT 3536 554 LT 3948 554 LT 3955 514 LT ST
3385 
(5) 3543 514 WT pop 0 originOffset 37 add RSS
3386 
3955 514 MT 3955 514 LT 3962 473 LT 4374 473 LT 4381 514 LT ST
3387 
3955 514 MT 3955 514 LT 3962 554 LT 4374 554 LT 4381 514 LT ST
3388 
(6) 3969 514 WT pop 0 originOffset 37 add RSS
3389 
4381 514 MT 4381 514 LT 4388 473 LT 4800 473 LT 4807 514 LT ST
3390 
4381 514 MT 4381 514 LT 4388 554 LT 4800 554 LT 4807 514 LT ST
3391 
(7) 4395 514 WT pop 0 originOffset 37 add RSS
3392 
4807 514 MT 4807 514 LT 4814 473 LT 5226 473 LT 5233 514 LT ST
3393 
4807 514 MT 4807 514 LT 4814 554 LT 5226 554 LT 5233 514 LT ST
3394 
(0) 4821 514 WT pop 0 originOffset 37 add RSS
3395 
5233 514 MT 5233 514 LT 5240 473 LT 5652 473 LT 5659 514 LT ST
3396 
5233 514 MT 5233 514 LT 5240 554 LT 5652 554 LT 5659 514 LT ST
3397 
(1) 5247 514 WT pop 0 originOffset 37 add RSS
3398 
5659 514 MT 5659 514 LT 5666 473 LT 6078 473 LT 6085 514 LT ST
3399 
5659 514 MT 5659 514 LT 5666 554 LT 6078 554 LT 6085 514 LT ST
3400 
(2) 5673 514 WT pop 0 originOffset 37 add RSS
3401 
6085 514 MT 6085 514 LT 6092 473 LT 6298 473 LT ST
3402 
6085 514 MT 6085 514 LT 6092 554 LT 6298 554 LT ST
3403 
(3) 6099 514 WT pop 0 originOffset 37 add RSS
3404 
3103 617 MT 3103 617 LT 3522 617 LT 3529 658 LT ST
3405 
3103 698 MT 3103 698 LT 3522 698 LT 3529 658 LT ST
3406 
(3) 3117 658 WT pop 0 originOffset 37 add RSS
3407 
3529 658 MT 3529 658 LT 3536 617 LT 3948 617 LT 3955 658 LT ST
3408 
3529 658 MT 3529 658 LT 3536 698 LT 3948 698 LT 3955 658 LT ST
3409 
(4) 3543 658 WT pop 0 originOffset 37 add RSS
3410 
3955 658 MT 3955 658 LT 3962 617 LT 4374 617 LT 4381 658 LT ST
3411 
3955 658 MT 3955 658 LT 3962 698 LT 4374 698 LT 4381 658 LT ST
3412 
(5) 3969 658 WT pop 0 originOffset 37 add RSS
3413 
4381 658 MT 4381 658 LT 4388 617 LT 4800 617 LT 4807 658 LT ST
3414 
4381 658 MT 4381 658 LT 4388 698 LT 4800 698 LT 4807 658 LT ST
3415 
(6) 4395 658 WT pop 0 originOffset 37 add RSS
3416 
4807 658 MT 4807 658 LT 4814 617 LT 5226 617 LT 5233 658 LT ST
3417 
4807 658 MT 4807 658 LT 4814 698 LT 5226 698 LT 5233 658 LT ST
3418 
(7) 4821 658 WT pop 0 originOffset 37 add RSS
3419 
5233 658 MT 5233 658 LT 5240 617 LT 5652 617 LT 5659 658 LT ST
3420 
5233 658 MT 5233 658 LT 5240 698 LT 5652 698 LT 5659 658 LT ST
3421 
(0) 5247 658 WT pop 0 originOffset 37 add RSS
3422 
5659 658 MT 5659 658 LT 5666 617 LT 6078 617 LT 6085 658 LT ST
3423 
5659 658 MT 5659 658 LT 5666 698 LT 6078 698 LT 6085 658 LT ST
3424 
(1) 5673 658 WT pop 0 originOffset 37 add RSS
3425 
6085 658 MT 6085 658 LT 6092 617 LT 6298 617 LT ST
3426 
6085 658 MT 6085 658 LT 6092 698 LT 6298 698 LT ST
3427 
(2) 6099 658 WT pop 0 originOffset 37 add RSS
3428 
3103 842 MT 6298 842 LS
3429 
3103 905 MT 3103 905 LT 6298 905 LT ST
3430 
3103 986 MT 3103 986 LT 6298 986 LT ST
3431 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
3432 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
3433 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
3434 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
3435 
3103 1274 MT 6298 1274 LS
3436 
% draw timeline
3437 
3145 4533 MT 3145 4570 LS
3438 
3187 4533 MT 3187 4570 LS
3439 
3230 4533 MT 3230 4570 LS
3440 
3272 4533 MT 3272 4570 LS
3441 
3359 4533 MT 3359 4570 LS
3442 
3401 4533 MT 3401 4570 LS
3443 
3444 4533 MT 3444 4570 LS
3444 
3486 4533 MT 3486 4570 LS
3445 
3529 4533 MT 3529 4570 LS
3446 
3572 4533 MT 3572 4570 LS
3447 
3614 4533 MT 3614 4570 LS
3448 
3657 4533 MT 3657 4570 LS
3449 
3699 4533 MT 3699 4570 LS
3450 
3316 4506 MT 3316 4570 LS
3451 
3785 4533 MT 3785 4570 LS
3452 
3827 4533 MT 3827 4570 LS
3453 
3870 4533 MT 3870 4570 LS
3454 
3912 4533 MT 3912 4570 LS
3455 
3955 4533 MT 3955 4570 LS
3456 
3998 4533 MT 3998 4570 LS
3457 
4040 4533 MT 4040 4570 LS
3458 
4083 4533 MT 4083 4570 LS
3459 
4125 4533 MT 4125 4570 LS
3460 
3742 4506 MT 3742 4570 LS
3461 
(240) 3742 4649 WT TS RSS
3462 
4211 4533 MT 4211 4570 LS
3463 
4253 4533 MT 4253 4570 LS
3464 
4296 4533 MT 4296 4570 LS
3465 
4338 4533 MT 4338 4570 LS
3466 
4381 4533 MT 4381 4570 LS
3467 
4424 4533 MT 4424 4570 LS
3468 
4466 4533 MT 4466 4570 LS
3469 
4509 4533 MT 4509 4570 LS
3470 
4551 4533 MT 4551 4570 LS
3471 
4168 4506 MT 4168 4570 LS
3472 
4637 4533 MT 4637 4570 LS
3473 
4679 4533 MT 4679 4570 LS
3474 
4722 4533 MT 4722 4570 LS
3475 
4764 4533 MT 4764 4570 LS
3476 
4807 4533 MT 4807 4570 LS
3477 
4850 4533 MT 4850 4570 LS
3478 
4892 4533 MT 4892 4570 LS
3479 
4935 4533 MT 4935 4570 LS
3480 
4977 4533 MT 4977 4570 LS
3481 
4594 4506 MT 4594 4570 LS
3482 
(260) 4594 4649 WT TS RSS
3483 
5063 4533 MT 5063 4570 LS
3484 
5105 4533 MT 5105 4570 LS
3485 
5148 4533 MT 5148 4570 LS
3486 
5190 4533 MT 5190 4570 LS
3487 
5233 4533 MT 5233 4570 LS
3488 
5276 4533 MT 5276 4570 LS
3489 
5318 4533 MT 5318 4570 LS
3490 
5361 4533 MT 5361 4570 LS
3491 
5403 4533 MT 5403 4570 LS
3492 
5020 4506 MT 5020 4570 LS
3493 
5489 4533 MT 5489 4570 LS
3494 
5531 4533 MT 5531 4570 LS
3495 
5574 4533 MT 5574 4570 LS
3496 
5616 4533 MT 5616 4570 LS
3497 
5659 4533 MT 5659 4570 LS
3498 
5702 4533 MT 5702 4570 LS
3499 
5744 4533 MT 5744 4570 LS
3500 
5787 4533 MT 5787 4570 LS
3501 
5829 4533 MT 5829 4570 LS
3502 
5446 4506 MT 5446 4570 LS
3503 
(280) 5446 4649 WT TS RSS
3504 
5915 4533 MT 5915 4570 LS
3505 
5957 4533 MT 5957 4570 LS
3506 
6000 4533 MT 6000 4570 LS
3507 
6042 4533 MT 6042 4570 LS
3508 
6085 4533 MT 6085 4570 LS
3509 
6128 4533 MT 6128 4570 LS
3510 
6170 4533 MT 6170 4570 LS
3511 
6213 4533 MT 6213 4570 LS
3512 
6255 4533 MT 6255 4570 LS
3513 
5872 4506 MT 5872 4570 LS
3514 
6341 4533 MT 6341 4570 LS
3515 
6383 4533 MT 6383 4570 LS
3516 
6426 4533 MT 6426 4570 LS
3517 
6468 4533 MT 6468 4570 LS
3518 
6511 4533 MT 6511 4570 LS
3519 
6554 4533 MT 6554 4570 LS
3520 
6596 4533 MT 6596 4570 LS
3521 
6639 4533 MT 6639 4570 LS
3522 
6681 4533 MT 6681 4570 LS
3523 
6298 4506 MT 6298 4570 LS
3524 
(300) 6298 4649 WT TS RSS
3525 
% draw grid
3526 
3316 300 MT 3316 4506 LS
3527 
3742 300 MT 3742 4506 LS
3528 
4168 300 MT 4168 4506 LS
3529 
4594 300 MT 4594 4506 LS
3530 
5020 300 MT 5020 4506 LS
3531 
5446 300 MT 5446 4506 LS
3532 
5872 300 MT 5872 4506 LS
3533 
6298 300 MT 6298 4506 LS
3534 
% draw waveforms
3535 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/spr_addrimm) 3066 409 WT TSE RSS
3536 
3309 300 MT 3323 300 LS
3537 
3735 300 MT 3749 300 LS
3538 
4161 300 MT 4175 300 LS
3539 
4587 300 MT 4601 300 LS
3540 
5013 300 MT 5027 300 LS
3541 
5439 300 MT 5453 300 LS
3542 
5865 300 MT 5879 300 LS
3543 
6291 300 MT 6305 300 LS
3544 
3103 329 MT 3103 329 LT 6298 329 LT ST
3545 
3103 410 MT 3103 410 LT 6298 410 LT ST
3546 
(1800) 3117 370 WT pop 0 originOffset 37 add RSS
3547 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_in) 3066 553 WT TSE RSS
3548 
3309 444 MT 3323 444 LS
3549 
3735 444 MT 3749 444 LS
3550 
4161 444 MT 4175 444 LS
3551 
4587 444 MT 4601 444 LS
3552 
5013 444 MT 5027 444 LS
3553 
5439 444 MT 5453 444 LS
3554 
5865 444 MT 5879 444 LS
3555 
6291 444 MT 6305 444 LS
3556 
3103 473 MT 3103 473 LT 3522 473 LT 3529 514 LT ST
3557 
3103 554 MT 3103 554 LT 3522 554 LT 3529 514 LT ST
3558 
(4) 3117 514 WT pop 0 originOffset 37 add RSS
3559 
3529 514 MT 3529 514 LT 3536 473 LT 3948 473 LT 3955 514 LT ST
3560 
3529 514 MT 3529 514 LT 3536 554 LT 3948 554 LT 3955 514 LT ST
3561 
(5) 3543 514 WT pop 0 originOffset 37 add RSS
3562 
3955 514 MT 3955 514 LT 3962 473 LT 4374 473 LT 4381 514 LT ST
3563 
3955 514 MT 3955 514 LT 3962 554 LT 4374 554 LT 4381 514 LT ST
3564 
(6) 3969 514 WT pop 0 originOffset 37 add RSS
3565 
4381 514 MT 4381 514 LT 4388 473 LT 4800 473 LT 4807 514 LT ST
3566 
4381 514 MT 4381 514 LT 4388 554 LT 4800 554 LT 4807 514 LT ST
3567 
(7) 4395 514 WT pop 0 originOffset 37 add RSS
3568 
4807 514 MT 4807 514 LT 4814 473 LT 5226 473 LT 5233 514 LT ST
3569 
4807 514 MT 4807 514 LT 4814 554 LT 5226 554 LT 5233 514 LT ST
3570 
(0) 4821 514 WT pop 0 originOffset 37 add RSS
3571 
5233 514 MT 5233 514 LT 5240 473 LT 5652 473 LT 5659 514 LT ST
3572 
5233 514 MT 5233 514 LT 5240 554 LT 5652 554 LT 5659 514 LT ST
3573 
(1) 5247 514 WT pop 0 originOffset 37 add RSS
3574 
5659 514 MT 5659 514 LT 5666 473 LT 6078 473 LT 6085 514 LT ST
3575 
5659 514 MT 5659 514 LT 5666 554 LT 6078 554 LT 6085 514 LT ST
3576 
(2) 5673 514 WT pop 0 originOffset 37 add RSS
3577 
6085 514 MT 6085 514 LT 6092 473 LT 6298 473 LT ST
3578 
6085 514 MT 6085 514 LT 6092 554 LT 6298 554 LT ST
3579 
(3) 6099 514 WT pop 0 originOffset 37 add RSS
3580 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/thread_out) 3066 697 WT TSE RSS
3581 
3309 588 MT 3323 588 LS
3582 
3735 588 MT 3749 588 LS
3583 
4161 588 MT 4175 588 LS
3584 
4587 588 MT 4601 588 LS
3585 
5013 588 MT 5027 588 LS
3586 
5439 588 MT 5453 588 LS
3587 
5865 588 MT 5879 588 LS
3588 
6291 588 MT 6305 588 LS
3589 
3103 617 MT 3103 617 LT 3522 617 LT 3529 658 LT ST
3590 
3103 698 MT 3103 698 LT 3522 698 LT 3529 658 LT ST
3591 
(3) 3117 658 WT pop 0 originOffset 37 add RSS
3592 
3529 658 MT 3529 658 LT 3536 617 LT 3948 617 LT 3955 658 LT ST
3593 
3529 658 MT 3529 658 LT 3536 698 LT 3948 698 LT 3955 658 LT ST
3594 
(4) 3543 658 WT pop 0 originOffset 37 add RSS
3595 
3955 658 MT 3955 658 LT 3962 617 LT 4374 617 LT 4381 658 LT ST
3596 
3955 658 MT 3955 658 LT 3962 698 LT 4374 698 LT 4381 658 LT ST
3597 
(5) 3969 658 WT pop 0 originOffset 37 add RSS
3598 
4381 658 MT 4381 658 LT 4388 617 LT 4800 617 LT 4807 658 LT ST
3599 
4381 658 MT 4381 658 LT 4388 698 LT 4800 698 LT 4807 658 LT ST
3600 
(6) 4395 658 WT pop 0 originOffset 37 add RSS
3601 
4807 658 MT 4807 658 LT 4814 617 LT 5226 617 LT 5233 658 LT ST
3602 
4807 658 MT 4807 658 LT 4814 698 LT 5226 698 LT 5233 658 LT ST
3603 
(7) 4821 658 WT pop 0 originOffset 37 add RSS
3604 
5233 658 MT 5233 658 LT 5240 617 LT 5652 617 LT 5659 658 LT ST
3605 
5233 658 MT 5233 658 LT 5240 698 LT 5652 698 LT 5659 658 LT ST
3606 
(0) 5247 658 WT pop 0 originOffset 37 add RSS
3607 
5659 658 MT 5659 658 LT 5666 617 LT 6078 617 LT 6085 658 LT ST
3608 
5659 658 MT 5659 658 LT 5666 698 LT 6078 698 LT 6085 658 LT ST
3609 
(1) 5673 658 WT pop 0 originOffset 37 add RSS
3610 
6085 658 MT 6085 658 LT 6092 617 LT 6298 617 LT ST
3611 
6085 658 MT 6085 658 LT 6092 698 LT 6298 698 LT ST
3612 
(2) 6099 658 WT pop 0 originOffset 37 add RSS
3613 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_freeze) 3066 841 WT TSE RSS
3614 
3309 732 MT 3323 732 LS
3615 
3735 732 MT 3749 732 LS
3616 
4161 732 MT 4175 732 LS
3617 
4587 732 MT 4601 732 LS
3618 
5013 732 MT 5027 732 LS
3619 
5439 732 MT 5453 732 LS
3620 
5865 732 MT 5879 732 LS
3621 
6291 732 MT 6305 732 LS
3622 
3103 842 MT 6298 842 LS
3623 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_insn) 3066 985 WT TSE RSS
3624 
3309 876 MT 3323 876 LS
3625 
3735 876 MT 3749 876 LS
3626 
4161 876 MT 4175 876 LS
3627 
4587 876 MT 4601 876 LS
3628 
5013 876 MT 5027 876 LS
3629 
5439 876 MT 5453 876 LS
3630 
5865 876 MT 5879 876 LS
3631 
6291 876 MT 6305 876 LS
3632 
3103 905 MT 3103 905 LT 6298 905 LT ST
3633 
3103 986 MT 3103 986 LT 6298 986 LT ST
3634 
(14610000) 3117 946 WT pop 0 originOffset 37 add RSS
3635 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wb_rfaddrw) 3066 1129 WT TSE RSS
3636 
3309 1020 MT 3323 1020 LS
3637 
3735 1020 MT 3749 1020 LS
3638 
4161 1020 MT 4175 1020 LS
3639 
4587 1020 MT 4601 1020 LS
3640 
5013 1020 MT 5027 1020 LS
3641 
5439 1020 MT 5453 1020 LS
3642 
5865 1020 MT 5879 1020 LS
3643 
6291 1020 MT 6305 1020 LS
3644 
3103 1049 MT 3103 1049 LT 6298 1049 LT ST
3645 
3103 1130 MT 3103 1130 LT 6298 1130 LT ST
3646 
(03) 3117 1090 WT pop 0 originOffset 37 add RSS
3647 
(/tb_or1200_cpu/or1200_cpu/or1200_ctrl2/wbforw_valid) 3066 1273 WT TSE RSS
3648 
3309 1164 MT 3323 1164 LS
3649 
3735 1164 MT 3749 1164 LS
3650 
4161 1164 MT 4175 1164 LS
3651 
4587 1164 MT 4601 1164 LS
3652 
5013 1164 MT 5027 1164 LS
3653 
5439 1164 MT 5453 1164 LS
3654 
5865 1164 MT 5879 1164 LS
3655 
6291 1164 MT 6305 1164 LS
3656 
3103 1274 MT 6298 1274 LS
3657 
% draw footer
3658 
(Entity:tb_or1200_cpu  Architecture:  Date: Sat Aug 14 00:33:37 EDT 2004   Row: 4 Page: 8) 300 4799 WT TSW RSS
3659 
grestore
3660 
showpage
3661 
%%EOF

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