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%%Creator: Model Technology ModelSim SE vsim 5.7e Simulator 2003.07 Jul 8 2003
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%%Title: /afs/eos.ncsu.edu/service/ece/research/tinker/bviyer/vol1/OR_1200_Multithreading_Implementation/verilog_with_my_changes/or1200_cpu/Wave_Forms_For_The_Whole_Thing/operandmuxes_module.ps
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%%CreationDate: 2004-08-14 01:14:01 AM
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%%DocumentData: Clean8Bit
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%%DocumentNeededResources: font Helvetica
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%%Orientation: Landscape
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%%Pages: 8
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%%EndComments
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90 rotate 0.12 dup neg scale
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/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
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/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
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(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
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(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
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3511 1666 MT 3511 1666 LT 3518 1706 LT 4300 1706 LT 4307 1666 LT ST
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(00000000) 3525 1666 WT pop 0 originOffset 37 add RSS
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4307 1666 MT 6297 1666 LS
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3312 1810 MT 3511 1810 LS
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3511 1810 MT 3511 1810 LT 3518 1769 LT 4698 1769 LT 4705 1810 LT ST
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3511 1810 MT 3511 1810 LT 3518 1850 LT 4698 1850 LT 4705 1810 LT ST
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(00000000) 3525 1810 WT pop 0 originOffset 37 add RSS
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4705 1810 MT 6297 1810 LS
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3312 1954 MT 3511 1954 LS
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3511 1954 MT 3511 1954 LT 3518 1913 LT 4300 1913 LT 4307 1954 LT ST
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3511 1954 MT 3511 1954 LT 3518 1994 LT 4300 1994 LT 4307 1954 LT ST
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(00000000) 3525 1954 WT pop 0 originOffset 37 add RSS
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4307 1954 MT 6297 1954 LS
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3312 2098 MT 3511 2098 LS
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3511 2098 MT 3511 2098 LT 3518 2057 LT 4698 2057 LT 4705 2098 LT ST
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3511 2098 MT 3511 2098 LT 3518 2138 LT 4698 2138 LT 4705 2098 LT ST
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(00000000) 3525 2098 WT pop 0 originOffset 37 add RSS
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4705 2098 MT 6297 2098 LS
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3312 2242 MT 3511 2242 LS
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3511 2242 MT 3511 2242 LT 3518 2201 LT 6297 2201 LT ST
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3511 2242 MT 3511 2242 LT 3518 2282 LT 6297 2282 LT ST
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(00000000) 3525 2242 WT pop 0 originOffset 37 add RSS
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3312 2386 MT 3511 2386 LS
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3511 2386 MT 3511 2386 LT 3518 2345 LT 6297 2345 LT ST
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3511 2386 MT 3511 2386 LT 3518 2426 LT 6297 2426 LT ST
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(00000000) 3525 2386 WT pop 0 originOffset 37 add RSS
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3312 2530 MT 3511 2530 LS
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3511 2530 MT 3511 2530 LT 3518 2489 LT 6297 2489 LT ST
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3511 2530 MT 3511 2530 LT 3518 2570 LT 6297 2570 LT ST
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(0) 3525 2530 WT pop 0 originOffset 37 add RSS
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3312 2674 MT 3511 2674 LS
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3511 2674 MT 3511 2674 LT 3518 2633 LT 6297 2633 LT ST
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3511 2674 MT 3511 2674 LT 3518 2714 LT 6297 2714 LT ST
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(0) 3525 2674 WT pop 0 originOffset 37 add RSS
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3312 2818 MT 3511 2818 LS
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3511 2818 MT 3511 2818 LT 3518 2777 LT 6297 2777 LT ST
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3511 2818 MT 3511 2818 LT 3518 2858 LT 6297 2858 LT ST
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(0) 3525 2818 WT pop 0 originOffset 37 add RSS
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3312 2962 MT 3511 2962 LS
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3511 2962 MT 3511 2962 LT 3518 2921 LT 6297 2921 LT ST
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3511 2962 MT 3511 2962 LT 3518 3002 LT 6297 3002 LT ST
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(0) 3525 2962 WT pop 0 originOffset 37 add RSS
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3312 3106 MT 3511 3106 LS
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3511 3106 MT 3511 3106 LT 3518 3065 LT 4300 3065 LT 4307 3106 LT ST
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3511 3106 MT 3511 3106 LT 3518 3146 LT 4300 3146 LT 4307 3106 LT ST
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(00000000) 3525 3106 WT pop 0 originOffset 37 add RSS
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4307 3106 MT 6297 3106 LS
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3312 3250 MT 3511 3250 LS
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3511 3250 MT 3511 3250 LT 3518 3209 LT 4300 3209 LT 4307 3250 LT ST
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3511 3250 MT 3511 3250 LT 3518 3290 LT 4300 3290 LT 4307 3250 LT ST
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(00000000) 3525 3250 WT pop 0 originOffset 37 add RSS
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4307 3250 MT 6297 3250 LS
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3312 3394 MT 3511 3394 LS
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3511 3394 MT 3511 3394 LT 3518 3353 LT 4300 3353 LT 4307 3394 LT ST
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3511 3394 MT 3511 3394 LT 3518 3434 LT 4300 3434 LT 4307 3394 LT ST
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(00000000) 3525 3394 WT pop 0 originOffset 37 add RSS
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4307 3394 MT 6297 3394 LS
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3312 3538 MT 3511 3538 LS
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3511 3538 MT 3511 3538 LT 3518 3497 LT 4300 3497 LT 4307 3538 LT ST
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3511 3538 MT 3511 3538 LT 3518 3578 LT 4300 3578 LT 4307 3538 LT ST
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(00000000) 3525 3538 WT pop 0 originOffset 37 add RSS
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4307 3538 MT 6297 3538 LS
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3511 3970 MT 3511 3970 LT 3518 3929 LT 5096 3929 LT 5103 3970 LT ST
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3511 3970 MT 3511 3970 LT 3518 4010 LT 5096 4010 LT 5103 3970 LT ST
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5103 3970 MT 5103 3970 LT 5110 3929 LT 5494 3929 LT 5501 3970 LT ST
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5103 3970 MT 5103 3970 LT 5110 4010 LT 5494 4010 LT 5501 3970 LT ST
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(1) 5117 3970 WT pop 0 originOffset 37 add RSS
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5501 3970 MT 5501 3970 LT 5508 3929 LT 5892 3929 LT 5899 3970 LT ST
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5501 3970 MT 5501 3970 LT 5508 4010 LT 5892 4010 LT 5899 3970 LT ST
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(2) 5515 3970 WT pop 0 originOffset 37 add RSS
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5899 3970 MT 5899 3970 LT 5906 3929 LT 6297 3929 LT ST
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5899 3970 MT 5899 3970 LT 5906 4010 LT 6297 4010 LT ST
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(3) 5913 3970 WT pop 0 originOffset 37 add RSS
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3312 4114 MT 3511 4114 LS
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3511 4114 MT 3511 4114 LT 3518 4073 LT 5096 4073 LT 5103 4114 LT ST
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3511 4114 MT 3511 4114 LT 3518 4154 LT 5096 4154 LT 5103 4114 LT ST
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(0) 3525 4114 WT pop 0 originOffset 37 add RSS
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5103 4114 MT 5103 4114 LT 5110 4073 LT 5494 4073 LT 5501 4114 LT ST
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5103 4114 MT 5103 4114 LT 5110 4154 LT 5494 4154 LT 5501 4114 LT ST
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(1) 5117 4114 WT pop 0 originOffset 37 add RSS
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5501 4114 MT 5501 4114 LT 5508 4073 LT 5892 4073 LT 5899 4114 LT ST
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5501 4114 MT 5501 4114 LT 5508 4154 LT 5892 4154 LT 5899 4114 LT ST
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(2) 5515 4114 WT pop 0 originOffset 37 add RSS
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(3) 5913 4114 WT pop 0 originOffset 37 add RSS
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3312 4258 MT 6297 4258 LS
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3312 4402 MT 6297 4402 LS
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% draw timeline
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4108 4506 MT 4108 4570 LS
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(20) 4108 4649 WT TS RSS
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4546 4533 MT 4546 4570 LS
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4904 4506 MT 4904 4570 LS
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(40) 4904 4649 WT TS RSS
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5342 4533 MT 5342 4570 LS
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5382 4533 MT 5382 4570 LS
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5302 4506 MT 5302 4570 LS
|
270 |
|
|
5740 4533 MT 5740 4570 LS
|
271 |
|
|
5780 4533 MT 5780 4570 LS
|
272 |
|
|
5819 4533 MT 5819 4570 LS
|
273 |
|
|
5859 4533 MT 5859 4570 LS
|
274 |
|
|
5899 4533 MT 5899 4570 LS
|
275 |
|
|
5939 4533 MT 5939 4570 LS
|
276 |
|
|
5979 4533 MT 5979 4570 LS
|
277 |
|
|
6019 4533 MT 6019 4570 LS
|
278 |
|
|
6058 4533 MT 6058 4570 LS
|
279 |
|
|
5700 4506 MT 5700 4570 LS
|
280 |
|
|
(60) 5700 4649 WT TS RSS
|
281 |
|
|
6138 4533 MT 6138 4570 LS
|
282 |
|
|
6178 4533 MT 6178 4570 LS
|
283 |
|
|
6217 4533 MT 6217 4570 LS
|
284 |
|
|
6257 4533 MT 6257 4570 LS
|
285 |
|
|
6297 4533 MT 6297 4570 LS
|
286 |
|
|
6337 4533 MT 6337 4570 LS
|
287 |
|
|
6377 4533 MT 6377 4570 LS
|
288 |
|
|
6417 4533 MT 6417 4570 LS
|
289 |
|
|
6456 4533 MT 6456 4570 LS
|
290 |
|
|
6098 4506 MT 6098 4570 LS
|
291 |
|
|
% draw grid
|
292 |
|
|
3710 300 MT 3710 4506 LS
|
293 |
|
|
4108 300 MT 4108 4506 LS
|
294 |
|
|
4506 300 MT 4506 4506 LS
|
295 |
|
|
4904 300 MT 4904 4506 LS
|
296 |
|
|
5302 300 MT 5302 4506 LS
|
297 |
|
|
5700 300 MT 5700 4506 LS
|
298 |
|
|
6098 300 MT 6098 4506 LS
|
299 |
|
|
% draw waveforms
|
300 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) 3275 409 WT TSE RSS
|
301 |
|
|
3703 300 MT 3717 300 LS
|
302 |
|
|
4101 300 MT 4115 300 LS
|
303 |
|
|
4499 300 MT 4513 300 LS
|
304 |
|
|
4897 300 MT 4911 300 LS
|
305 |
|
|
5295 300 MT 5309 300 LS
|
306 |
|
|
5693 300 MT 5707 300 LS
|
307 |
|
|
6091 300 MT 6105 300 LS
|
308 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
309 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
310 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
311 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) 3275 553 WT TSE RSS
|
312 |
|
|
3703 444 MT 3717 444 LS
|
313 |
|
|
4101 444 MT 4115 444 LS
|
314 |
|
|
4499 444 MT 4513 444 LS
|
315 |
|
|
4897 444 MT 4911 444 LS
|
316 |
|
|
5295 444 MT 5309 444 LS
|
317 |
|
|
5693 444 MT 5707 444 LS
|
318 |
|
|
6091 444 MT 6105 444 LS
|
319 |
|
|
3312 514 MT 3312 554 LS
|
320 |
|
|
3312 554 MT 3511 554 LS
|
321 |
|
|
3511 554 MT 3511 474 LS
|
322 |
|
|
3511 474 MT 3710 474 LS
|
323 |
|
|
3710 474 MT 3710 554 LS
|
324 |
|
|
3710 554 MT 3909 554 LS
|
325 |
|
|
3909 554 MT 3909 474 LS
|
326 |
|
|
3909 474 MT 4108 474 LS
|
327 |
|
|
4108 474 MT 4108 554 LS
|
328 |
|
|
4108 554 MT 4307 554 LS
|
329 |
|
|
4307 554 MT 4307 474 LS
|
330 |
|
|
4307 474 MT 4506 474 LS
|
331 |
|
|
4506 474 MT 4506 554 LS
|
332 |
|
|
4506 554 MT 4705 554 LS
|
333 |
|
|
4705 554 MT 4705 474 LS
|
334 |
|
|
4705 474 MT 4904 474 LS
|
335 |
|
|
4904 474 MT 4904 554 LS
|
336 |
|
|
4904 554 MT 5103 554 LS
|
337 |
|
|
5103 554 MT 5103 474 LS
|
338 |
|
|
5103 474 MT 5302 474 LS
|
339 |
|
|
5302 474 MT 5302 554 LS
|
340 |
|
|
5302 554 MT 5501 554 LS
|
341 |
|
|
5501 554 MT 5501 474 LS
|
342 |
|
|
5501 474 MT 5700 474 LS
|
343 |
|
|
5700 474 MT 5700 554 LS
|
344 |
|
|
5700 554 MT 5899 554 LS
|
345 |
|
|
5899 554 MT 5899 474 LS
|
346 |
|
|
5899 474 MT 6098 474 LS
|
347 |
|
|
6098 474 MT 6098 554 LS
|
348 |
|
|
6098 554 MT 6297 554 LS
|
349 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) 3275 697 WT TSE RSS
|
350 |
|
|
3703 588 MT 3717 588 LS
|
351 |
|
|
4101 588 MT 4115 588 LS
|
352 |
|
|
4499 588 MT 4513 588 LS
|
353 |
|
|
4897 588 MT 4911 588 LS
|
354 |
|
|
5295 588 MT 5309 588 LS
|
355 |
|
|
5693 588 MT 5707 588 LS
|
356 |
|
|
6091 588 MT 6105 588 LS
|
357 |
|
|
3312 658 MT 3312 698 LS
|
358 |
|
|
3312 698 MT 3511 698 LS
|
359 |
|
|
3511 698 MT 3511 618 LS
|
360 |
|
|
3511 618 MT 3710 618 LS
|
361 |
|
|
3710 618 MT 3710 698 LS
|
362 |
|
|
3710 698 MT 6297 698 LS
|
363 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) 3275 841 WT TSE RSS
|
364 |
|
|
3703 732 MT 3717 732 LS
|
365 |
|
|
4101 732 MT 4115 732 LS
|
366 |
|
|
4499 732 MT 4513 732 LS
|
367 |
|
|
4897 732 MT 4911 732 LS
|
368 |
|
|
5295 732 MT 5309 732 LS
|
369 |
|
|
5693 732 MT 5707 732 LS
|
370 |
|
|
6091 732 MT 6105 732 LS
|
371 |
|
|
3312 802 MT 4108 802 LS
|
372 |
|
|
4108 802 MT 4108 842 LS
|
373 |
|
|
4108 842 MT 6297 842 LS
|
374 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) 3275 985 WT TSE RSS
|
375 |
|
|
3703 876 MT 3717 876 LS
|
376 |
|
|
4101 876 MT 4115 876 LS
|
377 |
|
|
4499 876 MT 4513 876 LS
|
378 |
|
|
4897 876 MT 4911 876 LS
|
379 |
|
|
5295 876 MT 5309 876 LS
|
380 |
|
|
5693 876 MT 5707 876 LS
|
381 |
|
|
6091 876 MT 6105 876 LS
|
382 |
|
|
3312 946 MT 4108 946 LS
|
383 |
|
|
4108 946 MT 4108 986 LS
|
384 |
|
|
4108 986 MT 6297 986 LS
|
385 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) 3275 1129 WT TSE RSS
|
386 |
|
|
3703 1020 MT 3717 1020 LS
|
387 |
|
|
4101 1020 MT 4115 1020 LS
|
388 |
|
|
4499 1020 MT 4513 1020 LS
|
389 |
|
|
4897 1020 MT 4911 1020 LS
|
390 |
|
|
5295 1020 MT 5309 1020 LS
|
391 |
|
|
5693 1020 MT 5707 1020 LS
|
392 |
|
|
6091 1020 MT 6105 1020 LS
|
393 |
|
|
3312 1090 MT 6297 1090 LS
|
394 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) 3275 1273 WT TSE RSS
|
395 |
|
|
3703 1164 MT 3717 1164 LS
|
396 |
|
|
4101 1164 MT 4115 1164 LS
|
397 |
|
|
4499 1164 MT 4513 1164 LS
|
398 |
|
|
4897 1164 MT 4911 1164 LS
|
399 |
|
|
5295 1164 MT 5309 1164 LS
|
400 |
|
|
5693 1164 MT 5707 1164 LS
|
401 |
|
|
6091 1164 MT 6105 1164 LS
|
402 |
|
|
3312 1234 MT 6297 1234 LS
|
403 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) 3275 1417 WT TSE RSS
|
404 |
|
|
3703 1308 MT 3717 1308 LS
|
405 |
|
|
4101 1308 MT 4115 1308 LS
|
406 |
|
|
4499 1308 MT 4513 1308 LS
|
407 |
|
|
4897 1308 MT 4911 1308 LS
|
408 |
|
|
5295 1308 MT 5309 1308 LS
|
409 |
|
|
5693 1308 MT 5707 1308 LS
|
410 |
|
|
6091 1308 MT 6105 1308 LS
|
411 |
|
|
3312 1378 MT 6297 1378 LS
|
412 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) 3275 1561 WT TSE RSS
|
413 |
|
|
3703 1452 MT 3717 1452 LS
|
414 |
|
|
4101 1452 MT 4115 1452 LS
|
415 |
|
|
4499 1452 MT 4513 1452 LS
|
416 |
|
|
4897 1452 MT 4911 1452 LS
|
417 |
|
|
5295 1452 MT 5309 1452 LS
|
418 |
|
|
5693 1452 MT 5707 1452 LS
|
419 |
|
|
6091 1452 MT 6105 1452 LS
|
420 |
|
|
3312 1522 MT 6297 1522 LS
|
421 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) 3275 1705 WT TSE RSS
|
422 |
|
|
3703 1596 MT 3717 1596 LS
|
423 |
|
|
4101 1596 MT 4115 1596 LS
|
424 |
|
|
4499 1596 MT 4513 1596 LS
|
425 |
|
|
4897 1596 MT 4911 1596 LS
|
426 |
|
|
5295 1596 MT 5309 1596 LS
|
427 |
|
|
5693 1596 MT 5707 1596 LS
|
428 |
|
|
6091 1596 MT 6105 1596 LS
|
429 |
|
|
3312 1666 MT 3511 1666 LS
|
430 |
|
|
3511 1666 MT 3511 1666 LT 3518 1625 LT 4300 1625 LT 4307 1666 LT ST
|
431 |
|
|
3511 1666 MT 3511 1666 LT 3518 1706 LT 4300 1706 LT 4307 1666 LT ST
|
432 |
|
|
(00000000) 3525 1666 WT pop 0 originOffset 37 add RSS
|
433 |
|
|
4307 1666 MT 6297 1666 LS
|
434 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) 3275 1849 WT TSE RSS
|
435 |
|
|
3703 1740 MT 3717 1740 LS
|
436 |
|
|
4101 1740 MT 4115 1740 LS
|
437 |
|
|
4499 1740 MT 4513 1740 LS
|
438 |
|
|
4897 1740 MT 4911 1740 LS
|
439 |
|
|
5295 1740 MT 5309 1740 LS
|
440 |
|
|
5693 1740 MT 5707 1740 LS
|
441 |
|
|
6091 1740 MT 6105 1740 LS
|
442 |
|
|
3312 1810 MT 3511 1810 LS
|
443 |
|
|
3511 1810 MT 3511 1810 LT 3518 1769 LT 4698 1769 LT 4705 1810 LT ST
|
444 |
|
|
3511 1810 MT 3511 1810 LT 3518 1850 LT 4698 1850 LT 4705 1810 LT ST
|
445 |
|
|
(00000000) 3525 1810 WT pop 0 originOffset 37 add RSS
|
446 |
|
|
4705 1810 MT 6297 1810 LS
|
447 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) 3275 1993 WT TSE RSS
|
448 |
|
|
3703 1884 MT 3717 1884 LS
|
449 |
|
|
4101 1884 MT 4115 1884 LS
|
450 |
|
|
4499 1884 MT 4513 1884 LS
|
451 |
|
|
4897 1884 MT 4911 1884 LS
|
452 |
|
|
5295 1884 MT 5309 1884 LS
|
453 |
|
|
5693 1884 MT 5707 1884 LS
|
454 |
|
|
6091 1884 MT 6105 1884 LS
|
455 |
|
|
3312 1954 MT 3511 1954 LS
|
456 |
|
|
3511 1954 MT 3511 1954 LT 3518 1913 LT 4300 1913 LT 4307 1954 LT ST
|
457 |
|
|
3511 1954 MT 3511 1954 LT 3518 1994 LT 4300 1994 LT 4307 1954 LT ST
|
458 |
|
|
(00000000) 3525 1954 WT pop 0 originOffset 37 add RSS
|
459 |
|
|
4307 1954 MT 6297 1954 LS
|
460 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) 3275 2137 WT TSE RSS
|
461 |
|
|
3703 2028 MT 3717 2028 LS
|
462 |
|
|
4101 2028 MT 4115 2028 LS
|
463 |
|
|
4499 2028 MT 4513 2028 LS
|
464 |
|
|
4897 2028 MT 4911 2028 LS
|
465 |
|
|
5295 2028 MT 5309 2028 LS
|
466 |
|
|
5693 2028 MT 5707 2028 LS
|
467 |
|
|
6091 2028 MT 6105 2028 LS
|
468 |
|
|
3312 2098 MT 3511 2098 LS
|
469 |
|
|
3511 2098 MT 3511 2098 LT 3518 2057 LT 4698 2057 LT 4705 2098 LT ST
|
470 |
|
|
3511 2098 MT 3511 2098 LT 3518 2138 LT 4698 2138 LT 4705 2098 LT ST
|
471 |
|
|
(00000000) 3525 2098 WT pop 0 originOffset 37 add RSS
|
472 |
|
|
4705 2098 MT 6297 2098 LS
|
473 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) 3275 2281 WT TSE RSS
|
474 |
|
|
3703 2172 MT 3717 2172 LS
|
475 |
|
|
4101 2172 MT 4115 2172 LS
|
476 |
|
|
4499 2172 MT 4513 2172 LS
|
477 |
|
|
4897 2172 MT 4911 2172 LS
|
478 |
|
|
5295 2172 MT 5309 2172 LS
|
479 |
|
|
5693 2172 MT 5707 2172 LS
|
480 |
|
|
6091 2172 MT 6105 2172 LS
|
481 |
|
|
3312 2242 MT 3511 2242 LS
|
482 |
|
|
3511 2242 MT 3511 2242 LT 3518 2201 LT 6297 2201 LT ST
|
483 |
|
|
3511 2242 MT 3511 2242 LT 3518 2282 LT 6297 2282 LT ST
|
484 |
|
|
(00000000) 3525 2242 WT pop 0 originOffset 37 add RSS
|
485 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) 3275 2425 WT TSE RSS
|
486 |
|
|
3703 2316 MT 3717 2316 LS
|
487 |
|
|
4101 2316 MT 4115 2316 LS
|
488 |
|
|
4499 2316 MT 4513 2316 LS
|
489 |
|
|
4897 2316 MT 4911 2316 LS
|
490 |
|
|
5295 2316 MT 5309 2316 LS
|
491 |
|
|
5693 2316 MT 5707 2316 LS
|
492 |
|
|
6091 2316 MT 6105 2316 LS
|
493 |
|
|
3312 2386 MT 3511 2386 LS
|
494 |
|
|
3511 2386 MT 3511 2386 LT 3518 2345 LT 6297 2345 LT ST
|
495 |
|
|
3511 2386 MT 3511 2386 LT 3518 2426 LT 6297 2426 LT ST
|
496 |
|
|
(00000000) 3525 2386 WT pop 0 originOffset 37 add RSS
|
497 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) 3275 2569 WT TSE RSS
|
498 |
|
|
3703 2460 MT 3717 2460 LS
|
499 |
|
|
4101 2460 MT 4115 2460 LS
|
500 |
|
|
4499 2460 MT 4513 2460 LS
|
501 |
|
|
4897 2460 MT 4911 2460 LS
|
502 |
|
|
5295 2460 MT 5309 2460 LS
|
503 |
|
|
5693 2460 MT 5707 2460 LS
|
504 |
|
|
6091 2460 MT 6105 2460 LS
|
505 |
|
|
3312 2530 MT 3511 2530 LS
|
506 |
|
|
3511 2530 MT 3511 2530 LT 3518 2489 LT 6297 2489 LT ST
|
507 |
|
|
3511 2530 MT 3511 2530 LT 3518 2570 LT 6297 2570 LT ST
|
508 |
|
|
(0) 3525 2530 WT pop 0 originOffset 37 add RSS
|
509 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) 3275 2713 WT TSE RSS
|
510 |
|
|
3703 2604 MT 3717 2604 LS
|
511 |
|
|
4101 2604 MT 4115 2604 LS
|
512 |
|
|
4499 2604 MT 4513 2604 LS
|
513 |
|
|
4897 2604 MT 4911 2604 LS
|
514 |
|
|
5295 2604 MT 5309 2604 LS
|
515 |
|
|
5693 2604 MT 5707 2604 LS
|
516 |
|
|
6091 2604 MT 6105 2604 LS
|
517 |
|
|
3312 2674 MT 3511 2674 LS
|
518 |
|
|
3511 2674 MT 3511 2674 LT 3518 2633 LT 6297 2633 LT ST
|
519 |
|
|
3511 2674 MT 3511 2674 LT 3518 2714 LT 6297 2714 LT ST
|
520 |
|
|
(0) 3525 2674 WT pop 0 originOffset 37 add RSS
|
521 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) 3275 2857 WT TSE RSS
|
522 |
|
|
3703 2748 MT 3717 2748 LS
|
523 |
|
|
4101 2748 MT 4115 2748 LS
|
524 |
|
|
4499 2748 MT 4513 2748 LS
|
525 |
|
|
4897 2748 MT 4911 2748 LS
|
526 |
|
|
5295 2748 MT 5309 2748 LS
|
527 |
|
|
5693 2748 MT 5707 2748 LS
|
528 |
|
|
6091 2748 MT 6105 2748 LS
|
529 |
|
|
3312 2818 MT 3511 2818 LS
|
530 |
|
|
3511 2818 MT 3511 2818 LT 3518 2777 LT 6297 2777 LT ST
|
531 |
|
|
3511 2818 MT 3511 2818 LT 3518 2858 LT 6297 2858 LT ST
|
532 |
|
|
(0) 3525 2818 WT pop 0 originOffset 37 add RSS
|
533 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) 3275 3001 WT TSE RSS
|
534 |
|
|
3703 2892 MT 3717 2892 LS
|
535 |
|
|
4101 2892 MT 4115 2892 LS
|
536 |
|
|
4499 2892 MT 4513 2892 LS
|
537 |
|
|
4897 2892 MT 4911 2892 LS
|
538 |
|
|
5295 2892 MT 5309 2892 LS
|
539 |
|
|
5693 2892 MT 5707 2892 LS
|
540 |
|
|
6091 2892 MT 6105 2892 LS
|
541 |
|
|
3312 2962 MT 3511 2962 LS
|
542 |
|
|
3511 2962 MT 3511 2962 LT 3518 2921 LT 6297 2921 LT ST
|
543 |
|
|
3511 2962 MT 3511 2962 LT 3518 3002 LT 6297 3002 LT ST
|
544 |
|
|
(0) 3525 2962 WT pop 0 originOffset 37 add RSS
|
545 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) 3275 3145 WT TSE RSS
|
546 |
|
|
3703 3036 MT 3717 3036 LS
|
547 |
|
|
4101 3036 MT 4115 3036 LS
|
548 |
|
|
4499 3036 MT 4513 3036 LS
|
549 |
|
|
4897 3036 MT 4911 3036 LS
|
550 |
|
|
5295 3036 MT 5309 3036 LS
|
551 |
|
|
5693 3036 MT 5707 3036 LS
|
552 |
|
|
6091 3036 MT 6105 3036 LS
|
553 |
|
|
3312 3106 MT 3511 3106 LS
|
554 |
|
|
3511 3106 MT 3511 3106 LT 3518 3065 LT 4300 3065 LT 4307 3106 LT ST
|
555 |
|
|
3511 3106 MT 3511 3106 LT 3518 3146 LT 4300 3146 LT 4307 3106 LT ST
|
556 |
|
|
(00000000) 3525 3106 WT pop 0 originOffset 37 add RSS
|
557 |
|
|
4307 3106 MT 6297 3106 LS
|
558 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) 3275 3289 WT TSE RSS
|
559 |
|
|
3703 3180 MT 3717 3180 LS
|
560 |
|
|
4101 3180 MT 4115 3180 LS
|
561 |
|
|
4499 3180 MT 4513 3180 LS
|
562 |
|
|
4897 3180 MT 4911 3180 LS
|
563 |
|
|
5295 3180 MT 5309 3180 LS
|
564 |
|
|
5693 3180 MT 5707 3180 LS
|
565 |
|
|
6091 3180 MT 6105 3180 LS
|
566 |
|
|
3312 3250 MT 3511 3250 LS
|
567 |
|
|
3511 3250 MT 3511 3250 LT 3518 3209 LT 4300 3209 LT 4307 3250 LT ST
|
568 |
|
|
3511 3250 MT 3511 3250 LT 3518 3290 LT 4300 3290 LT 4307 3250 LT ST
|
569 |
|
|
(00000000) 3525 3250 WT pop 0 originOffset 37 add RSS
|
570 |
|
|
4307 3250 MT 6297 3250 LS
|
571 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) 3275 3433 WT TSE RSS
|
572 |
|
|
3703 3324 MT 3717 3324 LS
|
573 |
|
|
4101 3324 MT 4115 3324 LS
|
574 |
|
|
4499 3324 MT 4513 3324 LS
|
575 |
|
|
4897 3324 MT 4911 3324 LS
|
576 |
|
|
5295 3324 MT 5309 3324 LS
|
577 |
|
|
5693 3324 MT 5707 3324 LS
|
578 |
|
|
6091 3324 MT 6105 3324 LS
|
579 |
|
|
3312 3394 MT 3511 3394 LS
|
580 |
|
|
3511 3394 MT 3511 3394 LT 3518 3353 LT 4300 3353 LT 4307 3394 LT ST
|
581 |
|
|
3511 3394 MT 3511 3394 LT 3518 3434 LT 4300 3434 LT 4307 3394 LT ST
|
582 |
|
|
(00000000) 3525 3394 WT pop 0 originOffset 37 add RSS
|
583 |
|
|
4307 3394 MT 6297 3394 LS
|
584 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) 3275 3577 WT TSE RSS
|
585 |
|
|
3703 3468 MT 3717 3468 LS
|
586 |
|
|
4101 3468 MT 4115 3468 LS
|
587 |
|
|
4499 3468 MT 4513 3468 LS
|
588 |
|
|
4897 3468 MT 4911 3468 LS
|
589 |
|
|
5295 3468 MT 5309 3468 LS
|
590 |
|
|
5693 3468 MT 5707 3468 LS
|
591 |
|
|
6091 3468 MT 6105 3468 LS
|
592 |
|
|
3312 3538 MT 3511 3538 LS
|
593 |
|
|
3511 3538 MT 3511 3538 LT 3518 3497 LT 4300 3497 LT 4307 3538 LT ST
|
594 |
|
|
3511 3538 MT 3511 3538 LT 3518 3578 LT 4300 3578 LT 4307 3538 LT ST
|
595 |
|
|
(00000000) 3525 3538 WT pop 0 originOffset 37 add RSS
|
596 |
|
|
4307 3538 MT 6297 3538 LS
|
597 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) 3275 3721 WT TSE RSS
|
598 |
|
|
3703 3612 MT 3717 3612 LS
|
599 |
|
|
4101 3612 MT 4115 3612 LS
|
600 |
|
|
4499 3612 MT 4513 3612 LS
|
601 |
|
|
4897 3612 MT 4911 3612 LS
|
602 |
|
|
5295 3612 MT 5309 3612 LS
|
603 |
|
|
5693 3612 MT 5707 3612 LS
|
604 |
|
|
6091 3612 MT 6105 3612 LS
|
605 |
|
|
3312 3682 MT 6297 3682 LS
|
606 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) 3275 3865 WT TSE RSS
|
607 |
|
|
3703 3756 MT 3717 3756 LS
|
608 |
|
|
4101 3756 MT 4115 3756 LS
|
609 |
|
|
4499 3756 MT 4513 3756 LS
|
610 |
|
|
4897 3756 MT 4911 3756 LS
|
611 |
|
|
5295 3756 MT 5309 3756 LS
|
612 |
|
|
5693 3756 MT 5707 3756 LS
|
613 |
|
|
6091 3756 MT 6105 3756 LS
|
614 |
|
|
3312 3826 MT 6297 3826 LS
|
615 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) 3275 4009 WT TSE RSS
|
616 |
|
|
3703 3900 MT 3717 3900 LS
|
617 |
|
|
4101 3900 MT 4115 3900 LS
|
618 |
|
|
4499 3900 MT 4513 3900 LS
|
619 |
|
|
4897 3900 MT 4911 3900 LS
|
620 |
|
|
5295 3900 MT 5309 3900 LS
|
621 |
|
|
5693 3900 MT 5707 3900 LS
|
622 |
|
|
6091 3900 MT 6105 3900 LS
|
623 |
|
|
3312 3970 MT 3511 3970 LS
|
624 |
|
|
3511 3970 MT 3511 3970 LT 3518 3929 LT 5096 3929 LT 5103 3970 LT ST
|
625 |
|
|
3511 3970 MT 3511 3970 LT 3518 4010 LT 5096 4010 LT 5103 3970 LT ST
|
626 |
|
|
(0) 3525 3970 WT pop 0 originOffset 37 add RSS
|
627 |
|
|
5103 3970 MT 5103 3970 LT 5110 3929 LT 5494 3929 LT 5501 3970 LT ST
|
628 |
|
|
5103 3970 MT 5103 3970 LT 5110 4010 LT 5494 4010 LT 5501 3970 LT ST
|
629 |
|
|
(1) 5117 3970 WT pop 0 originOffset 37 add RSS
|
630 |
|
|
5501 3970 MT 5501 3970 LT 5508 3929 LT 5892 3929 LT 5899 3970 LT ST
|
631 |
|
|
5501 3970 MT 5501 3970 LT 5508 4010 LT 5892 4010 LT 5899 3970 LT ST
|
632 |
|
|
(2) 5515 3970 WT pop 0 originOffset 37 add RSS
|
633 |
|
|
5899 3970 MT 5899 3970 LT 5906 3929 LT 6297 3929 LT ST
|
634 |
|
|
5899 3970 MT 5899 3970 LT 5906 4010 LT 6297 4010 LT ST
|
635 |
|
|
(3) 5913 3970 WT pop 0 originOffset 37 add RSS
|
636 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) 3275 4153 WT TSE RSS
|
637 |
|
|
3703 4044 MT 3717 4044 LS
|
638 |
|
|
4101 4044 MT 4115 4044 LS
|
639 |
|
|
4499 4044 MT 4513 4044 LS
|
640 |
|
|
4897 4044 MT 4911 4044 LS
|
641 |
|
|
5295 4044 MT 5309 4044 LS
|
642 |
|
|
5693 4044 MT 5707 4044 LS
|
643 |
|
|
6091 4044 MT 6105 4044 LS
|
644 |
|
|
3312 4114 MT 3511 4114 LS
|
645 |
|
|
3511 4114 MT 3511 4114 LT 3518 4073 LT 5096 4073 LT 5103 4114 LT ST
|
646 |
|
|
3511 4114 MT 3511 4114 LT 3518 4154 LT 5096 4154 LT 5103 4114 LT ST
|
647 |
|
|
(0) 3525 4114 WT pop 0 originOffset 37 add RSS
|
648 |
|
|
5103 4114 MT 5103 4114 LT 5110 4073 LT 5494 4073 LT 5501 4114 LT ST
|
649 |
|
|
5103 4114 MT 5103 4114 LT 5110 4154 LT 5494 4154 LT 5501 4114 LT ST
|
650 |
|
|
(1) 5117 4114 WT pop 0 originOffset 37 add RSS
|
651 |
|
|
5501 4114 MT 5501 4114 LT 5508 4073 LT 5892 4073 LT 5899 4114 LT ST
|
652 |
|
|
5501 4114 MT 5501 4114 LT 5508 4154 LT 5892 4154 LT 5899 4114 LT ST
|
653 |
|
|
(2) 5515 4114 WT pop 0 originOffset 37 add RSS
|
654 |
|
|
5899 4114 MT 5899 4114 LT 5906 4073 LT 6297 4073 LT ST
|
655 |
|
|
5899 4114 MT 5899 4114 LT 5906 4154 LT 6297 4154 LT ST
|
656 |
|
|
(3) 5913 4114 WT pop 0 originOffset 37 add RSS
|
657 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) 3275 4297 WT TSE RSS
|
658 |
|
|
3703 4188 MT 3717 4188 LS
|
659 |
|
|
4101 4188 MT 4115 4188 LS
|
660 |
|
|
4499 4188 MT 4513 4188 LS
|
661 |
|
|
4897 4188 MT 4911 4188 LS
|
662 |
|
|
5295 4188 MT 5309 4188 LS
|
663 |
|
|
5693 4188 MT 5707 4188 LS
|
664 |
|
|
6091 4188 MT 6105 4188 LS
|
665 |
|
|
3312 4258 MT 6297 4258 LS
|
666 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) 3275 4441 WT TSE RSS
|
667 |
|
|
3703 4332 MT 3717 4332 LS
|
668 |
|
|
4101 4332 MT 4115 4332 LS
|
669 |
|
|
4499 4332 MT 4513 4332 LS
|
670 |
|
|
4897 4332 MT 4911 4332 LS
|
671 |
|
|
5295 4332 MT 5309 4332 LS
|
672 |
|
|
5693 4332 MT 5707 4332 LS
|
673 |
|
|
6091 4332 MT 6105 4332 LS
|
674 |
|
|
3312 4402 MT 6297 4402 LS
|
675 |
|
|
% draw footer
|
676 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 1 Page: 1) 300 4799 WT TSW RSS
|
677 |
|
|
grestore
|
678 |
|
|
showpage
|
679 |
|
|
%%Page: 2 2
|
680 |
|
|
gsave
|
681 |
|
|
90 rotate 0.12 dup neg scale
|
682 |
|
|
% dump string table
|
683 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
684 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
685 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
686 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
687 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
688 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
689 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
690 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
691 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
692 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
693 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
694 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
695 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
696 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
697 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
698 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
699 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
700 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
701 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
702 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
703 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
704 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
705 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
706 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
707 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
708 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
709 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
710 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
711 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
712 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
713 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
714 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
715 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
716 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
717 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
718 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
719 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
720 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
721 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
722 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
723 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
724 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
725 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
726 |
|
|
% draw waveform shading
|
727 |
|
|
[] 0 SD
|
728 |
|
|
2.995 setlinewidth
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
3312 370 MT 3511 370 LS
|
733 |
|
|
3511 370 MT 3511 410 LS
|
734 |
|
|
3511 410 MT 6297 410 LS
|
735 |
|
|
3312 514 MT 3511 514 LS
|
736 |
|
|
3511 514 MT 3511 554 LS
|
737 |
|
|
3511 554 MT 6297 554 LS
|
738 |
|
|
3312 658 MT 3511 658 LS
|
739 |
|
|
3511 658 MT 3511 698 LS
|
740 |
|
|
3511 698 MT 6297 698 LS
|
741 |
|
|
3312 802 MT 3511 802 LS
|
742 |
|
|
3511 802 MT 3511 842 LS
|
743 |
|
|
3511 842 MT 6297 842 LS
|
744 |
|
|
% draw timeline
|
745 |
|
|
3352 4533 MT 3352 4570 LS
|
746 |
|
|
3392 4533 MT 3392 4570 LS
|
747 |
|
|
3431 4533 MT 3431 4570 LS
|
748 |
|
|
3471 4533 MT 3471 4570 LS
|
749 |
|
|
3511 4533 MT 3511 4570 LS
|
750 |
|
|
3551 4533 MT 3551 4570 LS
|
751 |
|
|
3591 4533 MT 3591 4570 LS
|
752 |
|
|
3631 4533 MT 3631 4570 LS
|
753 |
|
|
3670 4533 MT 3670 4570 LS
|
754 |
|
|
(0) 3312 4649 WT TS RSS
|
755 |
|
|
3750 4533 MT 3750 4570 LS
|
756 |
|
|
3790 4533 MT 3790 4570 LS
|
757 |
|
|
3829 4533 MT 3829 4570 LS
|
758 |
|
|
3869 4533 MT 3869 4570 LS
|
759 |
|
|
3909 4533 MT 3909 4570 LS
|
760 |
|
|
3949 4533 MT 3949 4570 LS
|
761 |
|
|
3989 4533 MT 3989 4570 LS
|
762 |
|
|
4029 4533 MT 4029 4570 LS
|
763 |
|
|
4068 4533 MT 4068 4570 LS
|
764 |
|
|
3710 4506 MT 3710 4570 LS
|
765 |
|
|
4148 4533 MT 4148 4570 LS
|
766 |
|
|
4188 4533 MT 4188 4570 LS
|
767 |
|
|
4227 4533 MT 4227 4570 LS
|
768 |
|
|
4267 4533 MT 4267 4570 LS
|
769 |
|
|
4307 4533 MT 4307 4570 LS
|
770 |
|
|
4347 4533 MT 4347 4570 LS
|
771 |
|
|
4387 4533 MT 4387 4570 LS
|
772 |
|
|
4427 4533 MT 4427 4570 LS
|
773 |
|
|
4466 4533 MT 4466 4570 LS
|
774 |
|
|
4108 4506 MT 4108 4570 LS
|
775 |
|
|
(20) 4108 4649 WT TS RSS
|
776 |
|
|
4546 4533 MT 4546 4570 LS
|
777 |
|
|
4586 4533 MT 4586 4570 LS
|
778 |
|
|
4625 4533 MT 4625 4570 LS
|
779 |
|
|
4665 4533 MT 4665 4570 LS
|
780 |
|
|
4705 4533 MT 4705 4570 LS
|
781 |
|
|
4745 4533 MT 4745 4570 LS
|
782 |
|
|
4785 4533 MT 4785 4570 LS
|
783 |
|
|
4825 4533 MT 4825 4570 LS
|
784 |
|
|
4864 4533 MT 4864 4570 LS
|
785 |
|
|
4506 4506 MT 4506 4570 LS
|
786 |
|
|
4944 4533 MT 4944 4570 LS
|
787 |
|
|
4984 4533 MT 4984 4570 LS
|
788 |
|
|
5023 4533 MT 5023 4570 LS
|
789 |
|
|
5063 4533 MT 5063 4570 LS
|
790 |
|
|
5103 4533 MT 5103 4570 LS
|
791 |
|
|
5143 4533 MT 5143 4570 LS
|
792 |
|
|
5183 4533 MT 5183 4570 LS
|
793 |
|
|
5223 4533 MT 5223 4570 LS
|
794 |
|
|
5262 4533 MT 5262 4570 LS
|
795 |
|
|
4904 4506 MT 4904 4570 LS
|
796 |
|
|
(40) 4904 4649 WT TS RSS
|
797 |
|
|
5342 4533 MT 5342 4570 LS
|
798 |
|
|
5382 4533 MT 5382 4570 LS
|
799 |
|
|
5421 4533 MT 5421 4570 LS
|
800 |
|
|
5461 4533 MT 5461 4570 LS
|
801 |
|
|
5501 4533 MT 5501 4570 LS
|
802 |
|
|
5541 4533 MT 5541 4570 LS
|
803 |
|
|
5581 4533 MT 5581 4570 LS
|
804 |
|
|
5621 4533 MT 5621 4570 LS
|
805 |
|
|
5660 4533 MT 5660 4570 LS
|
806 |
|
|
5302 4506 MT 5302 4570 LS
|
807 |
|
|
5740 4533 MT 5740 4570 LS
|
808 |
|
|
5780 4533 MT 5780 4570 LS
|
809 |
|
|
5819 4533 MT 5819 4570 LS
|
810 |
|
|
5859 4533 MT 5859 4570 LS
|
811 |
|
|
5899 4533 MT 5899 4570 LS
|
812 |
|
|
5939 4533 MT 5939 4570 LS
|
813 |
|
|
5979 4533 MT 5979 4570 LS
|
814 |
|
|
6019 4533 MT 6019 4570 LS
|
815 |
|
|
6058 4533 MT 6058 4570 LS
|
816 |
|
|
5700 4506 MT 5700 4570 LS
|
817 |
|
|
(60) 5700 4649 WT TS RSS
|
818 |
|
|
6138 4533 MT 6138 4570 LS
|
819 |
|
|
6178 4533 MT 6178 4570 LS
|
820 |
|
|
6217 4533 MT 6217 4570 LS
|
821 |
|
|
6257 4533 MT 6257 4570 LS
|
822 |
|
|
6297 4533 MT 6297 4570 LS
|
823 |
|
|
6337 4533 MT 6337 4570 LS
|
824 |
|
|
6377 4533 MT 6377 4570 LS
|
825 |
|
|
6417 4533 MT 6417 4570 LS
|
826 |
|
|
6456 4533 MT 6456 4570 LS
|
827 |
|
|
6098 4506 MT 6098 4570 LS
|
828 |
|
|
% draw grid
|
829 |
|
|
3710 300 MT 3710 4506 LS
|
830 |
|
|
4108 300 MT 4108 4506 LS
|
831 |
|
|
4506 300 MT 4506 4506 LS
|
832 |
|
|
4904 300 MT 4904 4506 LS
|
833 |
|
|
5302 300 MT 5302 4506 LS
|
834 |
|
|
5700 300 MT 5700 4506 LS
|
835 |
|
|
6098 300 MT 6098 4506 LS
|
836 |
|
|
% draw waveforms
|
837 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) 3275 409 WT TSE RSS
|
838 |
|
|
3703 300 MT 3717 300 LS
|
839 |
|
|
4101 300 MT 4115 300 LS
|
840 |
|
|
4499 300 MT 4513 300 LS
|
841 |
|
|
4897 300 MT 4911 300 LS
|
842 |
|
|
5295 300 MT 5309 300 LS
|
843 |
|
|
5693 300 MT 5707 300 LS
|
844 |
|
|
6091 300 MT 6105 300 LS
|
845 |
|
|
3312 370 MT 3511 370 LS
|
846 |
|
|
3511 370 MT 3511 410 LS
|
847 |
|
|
3511 410 MT 6297 410 LS
|
848 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) 3275 553 WT TSE RSS
|
849 |
|
|
3703 444 MT 3717 444 LS
|
850 |
|
|
4101 444 MT 4115 444 LS
|
851 |
|
|
4499 444 MT 4513 444 LS
|
852 |
|
|
4897 444 MT 4911 444 LS
|
853 |
|
|
5295 444 MT 5309 444 LS
|
854 |
|
|
5693 444 MT 5707 444 LS
|
855 |
|
|
6091 444 MT 6105 444 LS
|
856 |
|
|
3312 514 MT 3511 514 LS
|
857 |
|
|
3511 514 MT 3511 554 LS
|
858 |
|
|
3511 554 MT 6297 554 LS
|
859 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) 3275 697 WT TSE RSS
|
860 |
|
|
3703 588 MT 3717 588 LS
|
861 |
|
|
4101 588 MT 4115 588 LS
|
862 |
|
|
4499 588 MT 4513 588 LS
|
863 |
|
|
4897 588 MT 4911 588 LS
|
864 |
|
|
5295 588 MT 5309 588 LS
|
865 |
|
|
5693 588 MT 5707 588 LS
|
866 |
|
|
6091 588 MT 6105 588 LS
|
867 |
|
|
3312 658 MT 3511 658 LS
|
868 |
|
|
3511 658 MT 3511 698 LS
|
869 |
|
|
3511 698 MT 6297 698 LS
|
870 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) 3275 841 WT TSE RSS
|
871 |
|
|
3703 732 MT 3717 732 LS
|
872 |
|
|
4101 732 MT 4115 732 LS
|
873 |
|
|
4499 732 MT 4513 732 LS
|
874 |
|
|
4897 732 MT 4911 732 LS
|
875 |
|
|
5295 732 MT 5309 732 LS
|
876 |
|
|
5693 732 MT 5707 732 LS
|
877 |
|
|
6091 732 MT 6105 732 LS
|
878 |
|
|
3312 802 MT 3511 802 LS
|
879 |
|
|
3511 802 MT 3511 842 LS
|
880 |
|
|
3511 842 MT 6297 842 LS
|
881 |
|
|
% draw footer
|
882 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 1 Page: 2) 300 4799 WT TSW RSS
|
883 |
|
|
grestore
|
884 |
|
|
showpage
|
885 |
|
|
%%Page: 3 3
|
886 |
|
|
gsave
|
887 |
|
|
90 rotate 0.12 dup neg scale
|
888 |
|
|
% dump string table
|
889 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
890 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
891 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
892 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
893 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
894 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
895 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
896 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
897 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
898 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
899 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
900 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
901 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
902 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
903 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
904 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
905 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
906 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
907 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
908 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
909 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
910 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
911 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
912 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
913 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
914 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
915 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
916 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
917 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
918 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
919 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
920 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
921 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
922 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
923 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
924 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
925 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
926 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
927 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
928 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
929 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
930 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
931 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
932 |
|
|
% draw waveform shading
|
933 |
|
|
[] 0 SD
|
934 |
|
|
2.995 setlinewidth
|
935 |
|
|
|
936 |
|
|
|
937 |
|
|
|
938 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
939 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
940 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
941 |
|
|
3312 554 MT 3312 474 LS
|
942 |
|
|
3312 474 MT 3511 474 LS
|
943 |
|
|
3511 474 MT 3511 554 LS
|
944 |
|
|
3511 554 MT 3710 554 LS
|
945 |
|
|
3710 554 MT 3710 474 LS
|
946 |
|
|
3710 474 MT 3909 474 LS
|
947 |
|
|
3909 474 MT 3909 554 LS
|
948 |
|
|
3909 554 MT 4108 554 LS
|
949 |
|
|
4108 554 MT 4108 474 LS
|
950 |
|
|
4108 474 MT 4307 474 LS
|
951 |
|
|
4307 474 MT 4307 554 LS
|
952 |
|
|
4307 554 MT 4506 554 LS
|
953 |
|
|
4506 554 MT 4506 474 LS
|
954 |
|
|
4506 474 MT 4705 474 LS
|
955 |
|
|
4705 474 MT 4705 554 LS
|
956 |
|
|
4705 554 MT 4904 554 LS
|
957 |
|
|
4904 554 MT 4904 474 LS
|
958 |
|
|
4904 474 MT 5103 474 LS
|
959 |
|
|
5103 474 MT 5103 554 LS
|
960 |
|
|
5103 554 MT 5302 554 LS
|
961 |
|
|
5302 554 MT 5302 474 LS
|
962 |
|
|
5302 474 MT 5501 474 LS
|
963 |
|
|
5501 474 MT 5501 554 LS
|
964 |
|
|
5501 554 MT 5700 554 LS
|
965 |
|
|
5700 554 MT 5700 474 LS
|
966 |
|
|
5700 474 MT 5899 474 LS
|
967 |
|
|
5899 474 MT 5899 554 LS
|
968 |
|
|
5899 554 MT 6098 554 LS
|
969 |
|
|
6098 554 MT 6098 474 LS
|
970 |
|
|
6098 474 MT 6297 474 LS
|
971 |
|
|
3312 698 MT 6297 698 LS
|
972 |
|
|
3312 842 MT 6297 842 LS
|
973 |
|
|
3312 986 MT 6297 986 LS
|
974 |
|
|
3312 1090 MT 6297 1090 LS
|
975 |
|
|
3312 1234 MT 6297 1234 LS
|
976 |
|
|
3312 1378 MT 6297 1378 LS
|
977 |
|
|
3312 1522 MT 6297 1522 LS
|
978 |
|
|
3312 1666 MT 6297 1666 LS
|
979 |
|
|
3312 1810 MT 6297 1810 LS
|
980 |
|
|
3312 1954 MT 6297 1954 LS
|
981 |
|
|
3312 2098 MT 6297 2098 LS
|
982 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
983 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
984 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
985 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
986 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
987 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
988 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
989 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
990 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
991 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
992 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
993 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
994 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
995 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
996 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
997 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
998 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
999 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
1000 |
|
|
3312 3106 MT 6297 3106 LS
|
1001 |
|
|
3312 3250 MT 6297 3250 LS
|
1002 |
|
|
3312 3394 MT 6297 3394 LS
|
1003 |
|
|
3312 3538 MT 6297 3538 LS
|
1004 |
|
|
3312 3682 MT 6297 3682 LS
|
1005 |
|
|
3312 3826 MT 6297 3826 LS
|
1006 |
|
|
3312 3929 MT 3312 3929 LT 3703 3929 LT 3710 3970 LT ST
|
1007 |
|
|
3312 4010 MT 3312 4010 LT 3703 4010 LT 3710 3970 LT ST
|
1008 |
|
|
(4) 3326 3970 WT pop 0 originOffset 37 add RSS
|
1009 |
|
|
3710 3970 MT 3710 3970 LT 3717 3929 LT 4101 3929 LT 4108 3970 LT ST
|
1010 |
|
|
3710 3970 MT 3710 3970 LT 3717 4010 LT 4101 4010 LT 4108 3970 LT ST
|
1011 |
|
|
(5) 3724 3970 WT pop 0 originOffset 37 add RSS
|
1012 |
|
|
4108 3970 MT 4108 3970 LT 4115 3929 LT 4499 3929 LT 4506 3970 LT ST
|
1013 |
|
|
4108 3970 MT 4108 3970 LT 4115 4010 LT 4499 4010 LT 4506 3970 LT ST
|
1014 |
|
|
(6) 4122 3970 WT pop 0 originOffset 37 add RSS
|
1015 |
|
|
4506 3970 MT 4506 3970 LT 4513 3929 LT 4897 3929 LT 4904 3970 LT ST
|
1016 |
|
|
4506 3970 MT 4506 3970 LT 4513 4010 LT 4897 4010 LT 4904 3970 LT ST
|
1017 |
|
|
(7) 4520 3970 WT pop 0 originOffset 37 add RSS
|
1018 |
|
|
4904 3970 MT 4904 3970 LT 4911 3929 LT 5295 3929 LT 5302 3970 LT ST
|
1019 |
|
|
4904 3970 MT 4904 3970 LT 4911 4010 LT 5295 4010 LT 5302 3970 LT ST
|
1020 |
|
|
(0) 4918 3970 WT pop 0 originOffset 37 add RSS
|
1021 |
|
|
5302 3970 MT 5302 3970 LT 5309 3929 LT 5693 3929 LT 5700 3970 LT ST
|
1022 |
|
|
5302 3970 MT 5302 3970 LT 5309 4010 LT 5693 4010 LT 5700 3970 LT ST
|
1023 |
|
|
(1) 5316 3970 WT pop 0 originOffset 37 add RSS
|
1024 |
|
|
5700 3970 MT 5700 3970 LT 5707 3929 LT 6091 3929 LT 6098 3970 LT ST
|
1025 |
|
|
5700 3970 MT 5700 3970 LT 5707 4010 LT 6091 4010 LT 6098 3970 LT ST
|
1026 |
|
|
(2) 5714 3970 WT pop 0 originOffset 37 add RSS
|
1027 |
|
|
6098 3970 MT 6098 3970 LT 6105 3929 LT 6297 3929 LT ST
|
1028 |
|
|
6098 3970 MT 6098 3970 LT 6105 4010 LT 6297 4010 LT ST
|
1029 |
|
|
(3) 6112 3970 WT pop 0 originOffset 37 add RSS
|
1030 |
|
|
3312 4073 MT 3312 4073 LT 3703 4073 LT 3710 4114 LT ST
|
1031 |
|
|
3312 4154 MT 3312 4154 LT 3703 4154 LT 3710 4114 LT ST
|
1032 |
|
|
(4) 3326 4114 WT pop 0 originOffset 37 add RSS
|
1033 |
|
|
3710 4114 MT 3710 4114 LT 3717 4073 LT 4101 4073 LT 4108 4114 LT ST
|
1034 |
|
|
3710 4114 MT 3710 4114 LT 3717 4154 LT 4101 4154 LT 4108 4114 LT ST
|
1035 |
|
|
(5) 3724 4114 WT pop 0 originOffset 37 add RSS
|
1036 |
|
|
4108 4114 MT 4108 4114 LT 4115 4073 LT 4499 4073 LT 4506 4114 LT ST
|
1037 |
|
|
4108 4114 MT 4108 4114 LT 4115 4154 LT 4499 4154 LT 4506 4114 LT ST
|
1038 |
|
|
(6) 4122 4114 WT pop 0 originOffset 37 add RSS
|
1039 |
|
|
4506 4114 MT 4506 4114 LT 4513 4073 LT 4897 4073 LT 4904 4114 LT ST
|
1040 |
|
|
4506 4114 MT 4506 4114 LT 4513 4154 LT 4897 4154 LT 4904 4114 LT ST
|
1041 |
|
|
(7) 4520 4114 WT pop 0 originOffset 37 add RSS
|
1042 |
|
|
4904 4114 MT 4904 4114 LT 4911 4073 LT 5295 4073 LT 5302 4114 LT ST
|
1043 |
|
|
4904 4114 MT 4904 4114 LT 4911 4154 LT 5295 4154 LT 5302 4114 LT ST
|
1044 |
|
|
(0) 4918 4114 WT pop 0 originOffset 37 add RSS
|
1045 |
|
|
5302 4114 MT 5302 4114 LT 5309 4073 LT 5693 4073 LT 5700 4114 LT ST
|
1046 |
|
|
5302 4114 MT 5302 4114 LT 5309 4154 LT 5693 4154 LT 5700 4114 LT ST
|
1047 |
|
|
(1) 5316 4114 WT pop 0 originOffset 37 add RSS
|
1048 |
|
|
5700 4114 MT 5700 4114 LT 5707 4073 LT 6091 4073 LT 6098 4114 LT ST
|
1049 |
|
|
5700 4114 MT 5700 4114 LT 5707 4154 LT 6091 4154 LT 6098 4114 LT ST
|
1050 |
|
|
(2) 5714 4114 WT pop 0 originOffset 37 add RSS
|
1051 |
|
|
6098 4114 MT 6098 4114 LT 6105 4073 LT 6297 4073 LT ST
|
1052 |
|
|
6098 4114 MT 6098 4114 LT 6105 4154 LT 6297 4154 LT ST
|
1053 |
|
|
(3) 6112 4114 WT pop 0 originOffset 37 add RSS
|
1054 |
|
|
3312 4258 MT 6297 4258 LS
|
1055 |
|
|
3312 4402 MT 6297 4402 LS
|
1056 |
|
|
% draw timeline
|
1057 |
|
|
3351 4533 MT 3351 4570 LS
|
1058 |
|
|
3391 4533 MT 3391 4570 LS
|
1059 |
|
|
3431 4533 MT 3431 4570 LS
|
1060 |
|
|
3470 4533 MT 3470 4570 LS
|
1061 |
|
|
3551 4533 MT 3551 4570 LS
|
1062 |
|
|
3591 4533 MT 3591 4570 LS
|
1063 |
|
|
3630 4533 MT 3630 4570 LS
|
1064 |
|
|
3670 4533 MT 3670 4570 LS
|
1065 |
|
|
3710 4533 MT 3710 4570 LS
|
1066 |
|
|
3750 4533 MT 3750 4570 LS
|
1067 |
|
|
3790 4533 MT 3790 4570 LS
|
1068 |
|
|
3830 4533 MT 3830 4570 LS
|
1069 |
|
|
3869 4533 MT 3869 4570 LS
|
1070 |
|
|
3511 4506 MT 3511 4570 LS
|
1071 |
|
|
(80) 3511 4649 WT TS RSS
|
1072 |
|
|
3949 4533 MT 3949 4570 LS
|
1073 |
|
|
3989 4533 MT 3989 4570 LS
|
1074 |
|
|
4028 4533 MT 4028 4570 LS
|
1075 |
|
|
4068 4533 MT 4068 4570 LS
|
1076 |
|
|
4108 4533 MT 4108 4570 LS
|
1077 |
|
|
4148 4533 MT 4148 4570 LS
|
1078 |
|
|
4188 4533 MT 4188 4570 LS
|
1079 |
|
|
4228 4533 MT 4228 4570 LS
|
1080 |
|
|
4267 4533 MT 4267 4570 LS
|
1081 |
|
|
3909 4506 MT 3909 4570 LS
|
1082 |
|
|
4347 4533 MT 4347 4570 LS
|
1083 |
|
|
4387 4533 MT 4387 4570 LS
|
1084 |
|
|
4426 4533 MT 4426 4570 LS
|
1085 |
|
|
4466 4533 MT 4466 4570 LS
|
1086 |
|
|
4506 4533 MT 4506 4570 LS
|
1087 |
|
|
4546 4533 MT 4546 4570 LS
|
1088 |
|
|
4586 4533 MT 4586 4570 LS
|
1089 |
|
|
4626 4533 MT 4626 4570 LS
|
1090 |
|
|
4665 4533 MT 4665 4570 LS
|
1091 |
|
|
4307 4506 MT 4307 4570 LS
|
1092 |
|
|
(100) 4307 4649 WT TS RSS
|
1093 |
|
|
4745 4533 MT 4745 4570 LS
|
1094 |
|
|
4785 4533 MT 4785 4570 LS
|
1095 |
|
|
4824 4533 MT 4824 4570 LS
|
1096 |
|
|
4864 4533 MT 4864 4570 LS
|
1097 |
|
|
4904 4533 MT 4904 4570 LS
|
1098 |
|
|
4944 4533 MT 4944 4570 LS
|
1099 |
|
|
4984 4533 MT 4984 4570 LS
|
1100 |
|
|
5024 4533 MT 5024 4570 LS
|
1101 |
|
|
5063 4533 MT 5063 4570 LS
|
1102 |
|
|
4705 4506 MT 4705 4570 LS
|
1103 |
|
|
5143 4533 MT 5143 4570 LS
|
1104 |
|
|
5183 4533 MT 5183 4570 LS
|
1105 |
|
|
5222 4533 MT 5222 4570 LS
|
1106 |
|
|
5262 4533 MT 5262 4570 LS
|
1107 |
|
|
5302 4533 MT 5302 4570 LS
|
1108 |
|
|
5342 4533 MT 5342 4570 LS
|
1109 |
|
|
5382 4533 MT 5382 4570 LS
|
1110 |
|
|
5422 4533 MT 5422 4570 LS
|
1111 |
|
|
5461 4533 MT 5461 4570 LS
|
1112 |
|
|
5103 4506 MT 5103 4570 LS
|
1113 |
|
|
(120) 5103 4649 WT TS RSS
|
1114 |
|
|
5541 4533 MT 5541 4570 LS
|
1115 |
|
|
5581 4533 MT 5581 4570 LS
|
1116 |
|
|
5620 4533 MT 5620 4570 LS
|
1117 |
|
|
5660 4533 MT 5660 4570 LS
|
1118 |
|
|
5700 4533 MT 5700 4570 LS
|
1119 |
|
|
5740 4533 MT 5740 4570 LS
|
1120 |
|
|
5780 4533 MT 5780 4570 LS
|
1121 |
|
|
5820 4533 MT 5820 4570 LS
|
1122 |
|
|
5859 4533 MT 5859 4570 LS
|
1123 |
|
|
5501 4506 MT 5501 4570 LS
|
1124 |
|
|
5939 4533 MT 5939 4570 LS
|
1125 |
|
|
5979 4533 MT 5979 4570 LS
|
1126 |
|
|
6018 4533 MT 6018 4570 LS
|
1127 |
|
|
6058 4533 MT 6058 4570 LS
|
1128 |
|
|
6098 4533 MT 6098 4570 LS
|
1129 |
|
|
6138 4533 MT 6138 4570 LS
|
1130 |
|
|
6178 4533 MT 6178 4570 LS
|
1131 |
|
|
6218 4533 MT 6218 4570 LS
|
1132 |
|
|
6257 4533 MT 6257 4570 LS
|
1133 |
|
|
5899 4506 MT 5899 4570 LS
|
1134 |
|
|
(140) 5899 4649 WT TS RSS
|
1135 |
|
|
6337 4533 MT 6337 4570 LS
|
1136 |
|
|
6377 4533 MT 6377 4570 LS
|
1137 |
|
|
6416 4533 MT 6416 4570 LS
|
1138 |
|
|
6456 4533 MT 6456 4570 LS
|
1139 |
|
|
6496 4533 MT 6496 4570 LS
|
1140 |
|
|
6536 4533 MT 6536 4570 LS
|
1141 |
|
|
6576 4533 MT 6576 4570 LS
|
1142 |
|
|
6616 4533 MT 6616 4570 LS
|
1143 |
|
|
6655 4533 MT 6655 4570 LS
|
1144 |
|
|
6297 4506 MT 6297 4570 LS
|
1145 |
|
|
% draw grid
|
1146 |
|
|
3511 300 MT 3511 4506 LS
|
1147 |
|
|
3909 300 MT 3909 4506 LS
|
1148 |
|
|
4307 300 MT 4307 4506 LS
|
1149 |
|
|
4705 300 MT 4705 4506 LS
|
1150 |
|
|
5103 300 MT 5103 4506 LS
|
1151 |
|
|
5501 300 MT 5501 4506 LS
|
1152 |
|
|
5899 300 MT 5899 4506 LS
|
1153 |
|
|
6297 300 MT 6297 4506 LS
|
1154 |
|
|
% draw waveforms
|
1155 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) 3275 409 WT TSE RSS
|
1156 |
|
|
3504 300 MT 3518 300 LS
|
1157 |
|
|
3902 300 MT 3916 300 LS
|
1158 |
|
|
4300 300 MT 4314 300 LS
|
1159 |
|
|
4698 300 MT 4712 300 LS
|
1160 |
|
|
5096 300 MT 5110 300 LS
|
1161 |
|
|
5494 300 MT 5508 300 LS
|
1162 |
|
|
5892 300 MT 5906 300 LS
|
1163 |
|
|
6290 300 MT 6304 300 LS
|
1164 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
1165 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
1166 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
1167 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) 3275 553 WT TSE RSS
|
1168 |
|
|
3504 444 MT 3518 444 LS
|
1169 |
|
|
3902 444 MT 3916 444 LS
|
1170 |
|
|
4300 444 MT 4314 444 LS
|
1171 |
|
|
4698 444 MT 4712 444 LS
|
1172 |
|
|
5096 444 MT 5110 444 LS
|
1173 |
|
|
5494 444 MT 5508 444 LS
|
1174 |
|
|
5892 444 MT 5906 444 LS
|
1175 |
|
|
6290 444 MT 6304 444 LS
|
1176 |
|
|
3312 554 MT 3312 474 LS
|
1177 |
|
|
3312 474 MT 3511 474 LS
|
1178 |
|
|
3511 474 MT 3511 554 LS
|
1179 |
|
|
3511 554 MT 3710 554 LS
|
1180 |
|
|
3710 554 MT 3710 474 LS
|
1181 |
|
|
3710 474 MT 3909 474 LS
|
1182 |
|
|
3909 474 MT 3909 554 LS
|
1183 |
|
|
3909 554 MT 4108 554 LS
|
1184 |
|
|
4108 554 MT 4108 474 LS
|
1185 |
|
|
4108 474 MT 4307 474 LS
|
1186 |
|
|
4307 474 MT 4307 554 LS
|
1187 |
|
|
4307 554 MT 4506 554 LS
|
1188 |
|
|
4506 554 MT 4506 474 LS
|
1189 |
|
|
4506 474 MT 4705 474 LS
|
1190 |
|
|
4705 474 MT 4705 554 LS
|
1191 |
|
|
4705 554 MT 4904 554 LS
|
1192 |
|
|
4904 554 MT 4904 474 LS
|
1193 |
|
|
4904 474 MT 5103 474 LS
|
1194 |
|
|
5103 474 MT 5103 554 LS
|
1195 |
|
|
5103 554 MT 5302 554 LS
|
1196 |
|
|
5302 554 MT 5302 474 LS
|
1197 |
|
|
5302 474 MT 5501 474 LS
|
1198 |
|
|
5501 474 MT 5501 554 LS
|
1199 |
|
|
5501 554 MT 5700 554 LS
|
1200 |
|
|
5700 554 MT 5700 474 LS
|
1201 |
|
|
5700 474 MT 5899 474 LS
|
1202 |
|
|
5899 474 MT 5899 554 LS
|
1203 |
|
|
5899 554 MT 6098 554 LS
|
1204 |
|
|
6098 554 MT 6098 474 LS
|
1205 |
|
|
6098 474 MT 6297 474 LS
|
1206 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) 3275 697 WT TSE RSS
|
1207 |
|
|
3504 588 MT 3518 588 LS
|
1208 |
|
|
3902 588 MT 3916 588 LS
|
1209 |
|
|
4300 588 MT 4314 588 LS
|
1210 |
|
|
4698 588 MT 4712 588 LS
|
1211 |
|
|
5096 588 MT 5110 588 LS
|
1212 |
|
|
5494 588 MT 5508 588 LS
|
1213 |
|
|
5892 588 MT 5906 588 LS
|
1214 |
|
|
6290 588 MT 6304 588 LS
|
1215 |
|
|
3312 698 MT 6297 698 LS
|
1216 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) 3275 841 WT TSE RSS
|
1217 |
|
|
3504 732 MT 3518 732 LS
|
1218 |
|
|
3902 732 MT 3916 732 LS
|
1219 |
|
|
4300 732 MT 4314 732 LS
|
1220 |
|
|
4698 732 MT 4712 732 LS
|
1221 |
|
|
5096 732 MT 5110 732 LS
|
1222 |
|
|
5494 732 MT 5508 732 LS
|
1223 |
|
|
5892 732 MT 5906 732 LS
|
1224 |
|
|
6290 732 MT 6304 732 LS
|
1225 |
|
|
3312 842 MT 6297 842 LS
|
1226 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) 3275 985 WT TSE RSS
|
1227 |
|
|
3504 876 MT 3518 876 LS
|
1228 |
|
|
3902 876 MT 3916 876 LS
|
1229 |
|
|
4300 876 MT 4314 876 LS
|
1230 |
|
|
4698 876 MT 4712 876 LS
|
1231 |
|
|
5096 876 MT 5110 876 LS
|
1232 |
|
|
5494 876 MT 5508 876 LS
|
1233 |
|
|
5892 876 MT 5906 876 LS
|
1234 |
|
|
6290 876 MT 6304 876 LS
|
1235 |
|
|
3312 986 MT 6297 986 LS
|
1236 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) 3275 1129 WT TSE RSS
|
1237 |
|
|
3504 1020 MT 3518 1020 LS
|
1238 |
|
|
3902 1020 MT 3916 1020 LS
|
1239 |
|
|
4300 1020 MT 4314 1020 LS
|
1240 |
|
|
4698 1020 MT 4712 1020 LS
|
1241 |
|
|
5096 1020 MT 5110 1020 LS
|
1242 |
|
|
5494 1020 MT 5508 1020 LS
|
1243 |
|
|
5892 1020 MT 5906 1020 LS
|
1244 |
|
|
6290 1020 MT 6304 1020 LS
|
1245 |
|
|
3312 1090 MT 6297 1090 LS
|
1246 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) 3275 1273 WT TSE RSS
|
1247 |
|
|
3504 1164 MT 3518 1164 LS
|
1248 |
|
|
3902 1164 MT 3916 1164 LS
|
1249 |
|
|
4300 1164 MT 4314 1164 LS
|
1250 |
|
|
4698 1164 MT 4712 1164 LS
|
1251 |
|
|
5096 1164 MT 5110 1164 LS
|
1252 |
|
|
5494 1164 MT 5508 1164 LS
|
1253 |
|
|
5892 1164 MT 5906 1164 LS
|
1254 |
|
|
6290 1164 MT 6304 1164 LS
|
1255 |
|
|
3312 1234 MT 6297 1234 LS
|
1256 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) 3275 1417 WT TSE RSS
|
1257 |
|
|
3504 1308 MT 3518 1308 LS
|
1258 |
|
|
3902 1308 MT 3916 1308 LS
|
1259 |
|
|
4300 1308 MT 4314 1308 LS
|
1260 |
|
|
4698 1308 MT 4712 1308 LS
|
1261 |
|
|
5096 1308 MT 5110 1308 LS
|
1262 |
|
|
5494 1308 MT 5508 1308 LS
|
1263 |
|
|
5892 1308 MT 5906 1308 LS
|
1264 |
|
|
6290 1308 MT 6304 1308 LS
|
1265 |
|
|
3312 1378 MT 6297 1378 LS
|
1266 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) 3275 1561 WT TSE RSS
|
1267 |
|
|
3504 1452 MT 3518 1452 LS
|
1268 |
|
|
3902 1452 MT 3916 1452 LS
|
1269 |
|
|
4300 1452 MT 4314 1452 LS
|
1270 |
|
|
4698 1452 MT 4712 1452 LS
|
1271 |
|
|
5096 1452 MT 5110 1452 LS
|
1272 |
|
|
5494 1452 MT 5508 1452 LS
|
1273 |
|
|
5892 1452 MT 5906 1452 LS
|
1274 |
|
|
6290 1452 MT 6304 1452 LS
|
1275 |
|
|
3312 1522 MT 6297 1522 LS
|
1276 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) 3275 1705 WT TSE RSS
|
1277 |
|
|
3504 1596 MT 3518 1596 LS
|
1278 |
|
|
3902 1596 MT 3916 1596 LS
|
1279 |
|
|
4300 1596 MT 4314 1596 LS
|
1280 |
|
|
4698 1596 MT 4712 1596 LS
|
1281 |
|
|
5096 1596 MT 5110 1596 LS
|
1282 |
|
|
5494 1596 MT 5508 1596 LS
|
1283 |
|
|
5892 1596 MT 5906 1596 LS
|
1284 |
|
|
6290 1596 MT 6304 1596 LS
|
1285 |
|
|
3312 1666 MT 6297 1666 LS
|
1286 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) 3275 1849 WT TSE RSS
|
1287 |
|
|
3504 1740 MT 3518 1740 LS
|
1288 |
|
|
3902 1740 MT 3916 1740 LS
|
1289 |
|
|
4300 1740 MT 4314 1740 LS
|
1290 |
|
|
4698 1740 MT 4712 1740 LS
|
1291 |
|
|
5096 1740 MT 5110 1740 LS
|
1292 |
|
|
5494 1740 MT 5508 1740 LS
|
1293 |
|
|
5892 1740 MT 5906 1740 LS
|
1294 |
|
|
6290 1740 MT 6304 1740 LS
|
1295 |
|
|
3312 1810 MT 6297 1810 LS
|
1296 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) 3275 1993 WT TSE RSS
|
1297 |
|
|
3504 1884 MT 3518 1884 LS
|
1298 |
|
|
3902 1884 MT 3916 1884 LS
|
1299 |
|
|
4300 1884 MT 4314 1884 LS
|
1300 |
|
|
4698 1884 MT 4712 1884 LS
|
1301 |
|
|
5096 1884 MT 5110 1884 LS
|
1302 |
|
|
5494 1884 MT 5508 1884 LS
|
1303 |
|
|
5892 1884 MT 5906 1884 LS
|
1304 |
|
|
6290 1884 MT 6304 1884 LS
|
1305 |
|
|
3312 1954 MT 6297 1954 LS
|
1306 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) 3275 2137 WT TSE RSS
|
1307 |
|
|
3504 2028 MT 3518 2028 LS
|
1308 |
|
|
3902 2028 MT 3916 2028 LS
|
1309 |
|
|
4300 2028 MT 4314 2028 LS
|
1310 |
|
|
4698 2028 MT 4712 2028 LS
|
1311 |
|
|
5096 2028 MT 5110 2028 LS
|
1312 |
|
|
5494 2028 MT 5508 2028 LS
|
1313 |
|
|
5892 2028 MT 5906 2028 LS
|
1314 |
|
|
6290 2028 MT 6304 2028 LS
|
1315 |
|
|
3312 2098 MT 6297 2098 LS
|
1316 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) 3275 2281 WT TSE RSS
|
1317 |
|
|
3504 2172 MT 3518 2172 LS
|
1318 |
|
|
3902 2172 MT 3916 2172 LS
|
1319 |
|
|
4300 2172 MT 4314 2172 LS
|
1320 |
|
|
4698 2172 MT 4712 2172 LS
|
1321 |
|
|
5096 2172 MT 5110 2172 LS
|
1322 |
|
|
5494 2172 MT 5508 2172 LS
|
1323 |
|
|
5892 2172 MT 5906 2172 LS
|
1324 |
|
|
6290 2172 MT 6304 2172 LS
|
1325 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
1326 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
1327 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
1328 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) 3275 2425 WT TSE RSS
|
1329 |
|
|
3504 2316 MT 3518 2316 LS
|
1330 |
|
|
3902 2316 MT 3916 2316 LS
|
1331 |
|
|
4300 2316 MT 4314 2316 LS
|
1332 |
|
|
4698 2316 MT 4712 2316 LS
|
1333 |
|
|
5096 2316 MT 5110 2316 LS
|
1334 |
|
|
5494 2316 MT 5508 2316 LS
|
1335 |
|
|
5892 2316 MT 5906 2316 LS
|
1336 |
|
|
6290 2316 MT 6304 2316 LS
|
1337 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
1338 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
1339 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
1340 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) 3275 2569 WT TSE RSS
|
1341 |
|
|
3504 2460 MT 3518 2460 LS
|
1342 |
|
|
3902 2460 MT 3916 2460 LS
|
1343 |
|
|
4300 2460 MT 4314 2460 LS
|
1344 |
|
|
4698 2460 MT 4712 2460 LS
|
1345 |
|
|
5096 2460 MT 5110 2460 LS
|
1346 |
|
|
5494 2460 MT 5508 2460 LS
|
1347 |
|
|
5892 2460 MT 5906 2460 LS
|
1348 |
|
|
6290 2460 MT 6304 2460 LS
|
1349 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
1350 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
1351 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
1352 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) 3275 2713 WT TSE RSS
|
1353 |
|
|
3504 2604 MT 3518 2604 LS
|
1354 |
|
|
3902 2604 MT 3916 2604 LS
|
1355 |
|
|
4300 2604 MT 4314 2604 LS
|
1356 |
|
|
4698 2604 MT 4712 2604 LS
|
1357 |
|
|
5096 2604 MT 5110 2604 LS
|
1358 |
|
|
5494 2604 MT 5508 2604 LS
|
1359 |
|
|
5892 2604 MT 5906 2604 LS
|
1360 |
|
|
6290 2604 MT 6304 2604 LS
|
1361 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
1362 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
1363 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
1364 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) 3275 2857 WT TSE RSS
|
1365 |
|
|
3504 2748 MT 3518 2748 LS
|
1366 |
|
|
3902 2748 MT 3916 2748 LS
|
1367 |
|
|
4300 2748 MT 4314 2748 LS
|
1368 |
|
|
4698 2748 MT 4712 2748 LS
|
1369 |
|
|
5096 2748 MT 5110 2748 LS
|
1370 |
|
|
5494 2748 MT 5508 2748 LS
|
1371 |
|
|
5892 2748 MT 5906 2748 LS
|
1372 |
|
|
6290 2748 MT 6304 2748 LS
|
1373 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
1374 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
1375 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
1376 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) 3275 3001 WT TSE RSS
|
1377 |
|
|
3504 2892 MT 3518 2892 LS
|
1378 |
|
|
3902 2892 MT 3916 2892 LS
|
1379 |
|
|
4300 2892 MT 4314 2892 LS
|
1380 |
|
|
4698 2892 MT 4712 2892 LS
|
1381 |
|
|
5096 2892 MT 5110 2892 LS
|
1382 |
|
|
5494 2892 MT 5508 2892 LS
|
1383 |
|
|
5892 2892 MT 5906 2892 LS
|
1384 |
|
|
6290 2892 MT 6304 2892 LS
|
1385 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
1386 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
1387 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
1388 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) 3275 3145 WT TSE RSS
|
1389 |
|
|
3504 3036 MT 3518 3036 LS
|
1390 |
|
|
3902 3036 MT 3916 3036 LS
|
1391 |
|
|
4300 3036 MT 4314 3036 LS
|
1392 |
|
|
4698 3036 MT 4712 3036 LS
|
1393 |
|
|
5096 3036 MT 5110 3036 LS
|
1394 |
|
|
5494 3036 MT 5508 3036 LS
|
1395 |
|
|
5892 3036 MT 5906 3036 LS
|
1396 |
|
|
6290 3036 MT 6304 3036 LS
|
1397 |
|
|
3312 3106 MT 6297 3106 LS
|
1398 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) 3275 3289 WT TSE RSS
|
1399 |
|
|
3504 3180 MT 3518 3180 LS
|
1400 |
|
|
3902 3180 MT 3916 3180 LS
|
1401 |
|
|
4300 3180 MT 4314 3180 LS
|
1402 |
|
|
4698 3180 MT 4712 3180 LS
|
1403 |
|
|
5096 3180 MT 5110 3180 LS
|
1404 |
|
|
5494 3180 MT 5508 3180 LS
|
1405 |
|
|
5892 3180 MT 5906 3180 LS
|
1406 |
|
|
6290 3180 MT 6304 3180 LS
|
1407 |
|
|
3312 3250 MT 6297 3250 LS
|
1408 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) 3275 3433 WT TSE RSS
|
1409 |
|
|
3504 3324 MT 3518 3324 LS
|
1410 |
|
|
3902 3324 MT 3916 3324 LS
|
1411 |
|
|
4300 3324 MT 4314 3324 LS
|
1412 |
|
|
4698 3324 MT 4712 3324 LS
|
1413 |
|
|
5096 3324 MT 5110 3324 LS
|
1414 |
|
|
5494 3324 MT 5508 3324 LS
|
1415 |
|
|
5892 3324 MT 5906 3324 LS
|
1416 |
|
|
6290 3324 MT 6304 3324 LS
|
1417 |
|
|
3312 3394 MT 6297 3394 LS
|
1418 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) 3275 3577 WT TSE RSS
|
1419 |
|
|
3504 3468 MT 3518 3468 LS
|
1420 |
|
|
3902 3468 MT 3916 3468 LS
|
1421 |
|
|
4300 3468 MT 4314 3468 LS
|
1422 |
|
|
4698 3468 MT 4712 3468 LS
|
1423 |
|
|
5096 3468 MT 5110 3468 LS
|
1424 |
|
|
5494 3468 MT 5508 3468 LS
|
1425 |
|
|
5892 3468 MT 5906 3468 LS
|
1426 |
|
|
6290 3468 MT 6304 3468 LS
|
1427 |
|
|
3312 3538 MT 6297 3538 LS
|
1428 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) 3275 3721 WT TSE RSS
|
1429 |
|
|
3504 3612 MT 3518 3612 LS
|
1430 |
|
|
3902 3612 MT 3916 3612 LS
|
1431 |
|
|
4300 3612 MT 4314 3612 LS
|
1432 |
|
|
4698 3612 MT 4712 3612 LS
|
1433 |
|
|
5096 3612 MT 5110 3612 LS
|
1434 |
|
|
5494 3612 MT 5508 3612 LS
|
1435 |
|
|
5892 3612 MT 5906 3612 LS
|
1436 |
|
|
6290 3612 MT 6304 3612 LS
|
1437 |
|
|
3312 3682 MT 6297 3682 LS
|
1438 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) 3275 3865 WT TSE RSS
|
1439 |
|
|
3504 3756 MT 3518 3756 LS
|
1440 |
|
|
3902 3756 MT 3916 3756 LS
|
1441 |
|
|
4300 3756 MT 4314 3756 LS
|
1442 |
|
|
4698 3756 MT 4712 3756 LS
|
1443 |
|
|
5096 3756 MT 5110 3756 LS
|
1444 |
|
|
5494 3756 MT 5508 3756 LS
|
1445 |
|
|
5892 3756 MT 5906 3756 LS
|
1446 |
|
|
6290 3756 MT 6304 3756 LS
|
1447 |
|
|
3312 3826 MT 6297 3826 LS
|
1448 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) 3275 4009 WT TSE RSS
|
1449 |
|
|
3504 3900 MT 3518 3900 LS
|
1450 |
|
|
3902 3900 MT 3916 3900 LS
|
1451 |
|
|
4300 3900 MT 4314 3900 LS
|
1452 |
|
|
4698 3900 MT 4712 3900 LS
|
1453 |
|
|
5096 3900 MT 5110 3900 LS
|
1454 |
|
|
5494 3900 MT 5508 3900 LS
|
1455 |
|
|
5892 3900 MT 5906 3900 LS
|
1456 |
|
|
6290 3900 MT 6304 3900 LS
|
1457 |
|
|
3312 3929 MT 3312 3929 LT 3703 3929 LT 3710 3970 LT ST
|
1458 |
|
|
3312 4010 MT 3312 4010 LT 3703 4010 LT 3710 3970 LT ST
|
1459 |
|
|
(4) 3326 3970 WT pop 0 originOffset 37 add RSS
|
1460 |
|
|
3710 3970 MT 3710 3970 LT 3717 3929 LT 4101 3929 LT 4108 3970 LT ST
|
1461 |
|
|
3710 3970 MT 3710 3970 LT 3717 4010 LT 4101 4010 LT 4108 3970 LT ST
|
1462 |
|
|
(5) 3724 3970 WT pop 0 originOffset 37 add RSS
|
1463 |
|
|
4108 3970 MT 4108 3970 LT 4115 3929 LT 4499 3929 LT 4506 3970 LT ST
|
1464 |
|
|
4108 3970 MT 4108 3970 LT 4115 4010 LT 4499 4010 LT 4506 3970 LT ST
|
1465 |
|
|
(6) 4122 3970 WT pop 0 originOffset 37 add RSS
|
1466 |
|
|
4506 3970 MT 4506 3970 LT 4513 3929 LT 4897 3929 LT 4904 3970 LT ST
|
1467 |
|
|
4506 3970 MT 4506 3970 LT 4513 4010 LT 4897 4010 LT 4904 3970 LT ST
|
1468 |
|
|
(7) 4520 3970 WT pop 0 originOffset 37 add RSS
|
1469 |
|
|
4904 3970 MT 4904 3970 LT 4911 3929 LT 5295 3929 LT 5302 3970 LT ST
|
1470 |
|
|
4904 3970 MT 4904 3970 LT 4911 4010 LT 5295 4010 LT 5302 3970 LT ST
|
1471 |
|
|
(0) 4918 3970 WT pop 0 originOffset 37 add RSS
|
1472 |
|
|
5302 3970 MT 5302 3970 LT 5309 3929 LT 5693 3929 LT 5700 3970 LT ST
|
1473 |
|
|
5302 3970 MT 5302 3970 LT 5309 4010 LT 5693 4010 LT 5700 3970 LT ST
|
1474 |
|
|
(1) 5316 3970 WT pop 0 originOffset 37 add RSS
|
1475 |
|
|
5700 3970 MT 5700 3970 LT 5707 3929 LT 6091 3929 LT 6098 3970 LT ST
|
1476 |
|
|
5700 3970 MT 5700 3970 LT 5707 4010 LT 6091 4010 LT 6098 3970 LT ST
|
1477 |
|
|
(2) 5714 3970 WT pop 0 originOffset 37 add RSS
|
1478 |
|
|
6098 3970 MT 6098 3970 LT 6105 3929 LT 6297 3929 LT ST
|
1479 |
|
|
6098 3970 MT 6098 3970 LT 6105 4010 LT 6297 4010 LT ST
|
1480 |
|
|
(3) 6112 3970 WT pop 0 originOffset 37 add RSS
|
1481 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) 3275 4153 WT TSE RSS
|
1482 |
|
|
3504 4044 MT 3518 4044 LS
|
1483 |
|
|
3902 4044 MT 3916 4044 LS
|
1484 |
|
|
4300 4044 MT 4314 4044 LS
|
1485 |
|
|
4698 4044 MT 4712 4044 LS
|
1486 |
|
|
5096 4044 MT 5110 4044 LS
|
1487 |
|
|
5494 4044 MT 5508 4044 LS
|
1488 |
|
|
5892 4044 MT 5906 4044 LS
|
1489 |
|
|
6290 4044 MT 6304 4044 LS
|
1490 |
|
|
3312 4073 MT 3312 4073 LT 3703 4073 LT 3710 4114 LT ST
|
1491 |
|
|
3312 4154 MT 3312 4154 LT 3703 4154 LT 3710 4114 LT ST
|
1492 |
|
|
(4) 3326 4114 WT pop 0 originOffset 37 add RSS
|
1493 |
|
|
3710 4114 MT 3710 4114 LT 3717 4073 LT 4101 4073 LT 4108 4114 LT ST
|
1494 |
|
|
3710 4114 MT 3710 4114 LT 3717 4154 LT 4101 4154 LT 4108 4114 LT ST
|
1495 |
|
|
(5) 3724 4114 WT pop 0 originOffset 37 add RSS
|
1496 |
|
|
4108 4114 MT 4108 4114 LT 4115 4073 LT 4499 4073 LT 4506 4114 LT ST
|
1497 |
|
|
4108 4114 MT 4108 4114 LT 4115 4154 LT 4499 4154 LT 4506 4114 LT ST
|
1498 |
|
|
(6) 4122 4114 WT pop 0 originOffset 37 add RSS
|
1499 |
|
|
4506 4114 MT 4506 4114 LT 4513 4073 LT 4897 4073 LT 4904 4114 LT ST
|
1500 |
|
|
4506 4114 MT 4506 4114 LT 4513 4154 LT 4897 4154 LT 4904 4114 LT ST
|
1501 |
|
|
(7) 4520 4114 WT pop 0 originOffset 37 add RSS
|
1502 |
|
|
4904 4114 MT 4904 4114 LT 4911 4073 LT 5295 4073 LT 5302 4114 LT ST
|
1503 |
|
|
4904 4114 MT 4904 4114 LT 4911 4154 LT 5295 4154 LT 5302 4114 LT ST
|
1504 |
|
|
(0) 4918 4114 WT pop 0 originOffset 37 add RSS
|
1505 |
|
|
5302 4114 MT 5302 4114 LT 5309 4073 LT 5693 4073 LT 5700 4114 LT ST
|
1506 |
|
|
5302 4114 MT 5302 4114 LT 5309 4154 LT 5693 4154 LT 5700 4114 LT ST
|
1507 |
|
|
(1) 5316 4114 WT pop 0 originOffset 37 add RSS
|
1508 |
|
|
5700 4114 MT 5700 4114 LT 5707 4073 LT 6091 4073 LT 6098 4114 LT ST
|
1509 |
|
|
5700 4114 MT 5700 4114 LT 5707 4154 LT 6091 4154 LT 6098 4114 LT ST
|
1510 |
|
|
(2) 5714 4114 WT pop 0 originOffset 37 add RSS
|
1511 |
|
|
6098 4114 MT 6098 4114 LT 6105 4073 LT 6297 4073 LT ST
|
1512 |
|
|
6098 4114 MT 6098 4114 LT 6105 4154 LT 6297 4154 LT ST
|
1513 |
|
|
(3) 6112 4114 WT pop 0 originOffset 37 add RSS
|
1514 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) 3275 4297 WT TSE RSS
|
1515 |
|
|
3504 4188 MT 3518 4188 LS
|
1516 |
|
|
3902 4188 MT 3916 4188 LS
|
1517 |
|
|
4300 4188 MT 4314 4188 LS
|
1518 |
|
|
4698 4188 MT 4712 4188 LS
|
1519 |
|
|
5096 4188 MT 5110 4188 LS
|
1520 |
|
|
5494 4188 MT 5508 4188 LS
|
1521 |
|
|
5892 4188 MT 5906 4188 LS
|
1522 |
|
|
6290 4188 MT 6304 4188 LS
|
1523 |
|
|
3312 4258 MT 6297 4258 LS
|
1524 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) 3275 4441 WT TSE RSS
|
1525 |
|
|
3504 4332 MT 3518 4332 LS
|
1526 |
|
|
3902 4332 MT 3916 4332 LS
|
1527 |
|
|
4300 4332 MT 4314 4332 LS
|
1528 |
|
|
4698 4332 MT 4712 4332 LS
|
1529 |
|
|
5096 4332 MT 5110 4332 LS
|
1530 |
|
|
5494 4332 MT 5508 4332 LS
|
1531 |
|
|
5892 4332 MT 5906 4332 LS
|
1532 |
|
|
6290 4332 MT 6304 4332 LS
|
1533 |
|
|
3312 4402 MT 6297 4402 LS
|
1534 |
|
|
% draw footer
|
1535 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 2 Page: 3) 300 4799 WT TSW RSS
|
1536 |
|
|
grestore
|
1537 |
|
|
showpage
|
1538 |
|
|
%%Page: 4 4
|
1539 |
|
|
gsave
|
1540 |
|
|
90 rotate 0.12 dup neg scale
|
1541 |
|
|
% dump string table
|
1542 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
1543 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
1544 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
1545 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
1546 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
1547 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
1548 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
1549 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
1550 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
1551 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
1552 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
1553 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
1554 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
1555 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
1556 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
1557 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
1558 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
1559 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
1560 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
1561 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
1562 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
1563 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
1564 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
1565 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
1566 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
1567 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
1568 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
1569 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
1570 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
1571 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
1572 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
1573 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
1574 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
1575 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
1576 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
1577 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
1578 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
1579 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
1580 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
1581 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
1582 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
1583 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
1584 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
1585 |
|
|
% draw waveform shading
|
1586 |
|
|
[] 0 SD
|
1587 |
|
|
2.995 setlinewidth
|
1588 |
|
|
|
1589 |
|
|
|
1590 |
|
|
|
1591 |
|
|
3312 410 MT 6297 410 LS
|
1592 |
|
|
3312 554 MT 6297 554 LS
|
1593 |
|
|
3312 698 MT 6297 698 LS
|
1594 |
|
|
3312 842 MT 6297 842 LS
|
1595 |
|
|
% draw timeline
|
1596 |
|
|
3351 4533 MT 3351 4570 LS
|
1597 |
|
|
3391 4533 MT 3391 4570 LS
|
1598 |
|
|
3431 4533 MT 3431 4570 LS
|
1599 |
|
|
3470 4533 MT 3470 4570 LS
|
1600 |
|
|
3551 4533 MT 3551 4570 LS
|
1601 |
|
|
3591 4533 MT 3591 4570 LS
|
1602 |
|
|
3630 4533 MT 3630 4570 LS
|
1603 |
|
|
3670 4533 MT 3670 4570 LS
|
1604 |
|
|
3710 4533 MT 3710 4570 LS
|
1605 |
|
|
3750 4533 MT 3750 4570 LS
|
1606 |
|
|
3790 4533 MT 3790 4570 LS
|
1607 |
|
|
3830 4533 MT 3830 4570 LS
|
1608 |
|
|
3869 4533 MT 3869 4570 LS
|
1609 |
|
|
3511 4506 MT 3511 4570 LS
|
1610 |
|
|
(80) 3511 4649 WT TS RSS
|
1611 |
|
|
3949 4533 MT 3949 4570 LS
|
1612 |
|
|
3989 4533 MT 3989 4570 LS
|
1613 |
|
|
4028 4533 MT 4028 4570 LS
|
1614 |
|
|
4068 4533 MT 4068 4570 LS
|
1615 |
|
|
4108 4533 MT 4108 4570 LS
|
1616 |
|
|
4148 4533 MT 4148 4570 LS
|
1617 |
|
|
4188 4533 MT 4188 4570 LS
|
1618 |
|
|
4228 4533 MT 4228 4570 LS
|
1619 |
|
|
4267 4533 MT 4267 4570 LS
|
1620 |
|
|
3909 4506 MT 3909 4570 LS
|
1621 |
|
|
4347 4533 MT 4347 4570 LS
|
1622 |
|
|
4387 4533 MT 4387 4570 LS
|
1623 |
|
|
4426 4533 MT 4426 4570 LS
|
1624 |
|
|
4466 4533 MT 4466 4570 LS
|
1625 |
|
|
4506 4533 MT 4506 4570 LS
|
1626 |
|
|
4546 4533 MT 4546 4570 LS
|
1627 |
|
|
4586 4533 MT 4586 4570 LS
|
1628 |
|
|
4626 4533 MT 4626 4570 LS
|
1629 |
|
|
4665 4533 MT 4665 4570 LS
|
1630 |
|
|
4307 4506 MT 4307 4570 LS
|
1631 |
|
|
(100) 4307 4649 WT TS RSS
|
1632 |
|
|
4745 4533 MT 4745 4570 LS
|
1633 |
|
|
4785 4533 MT 4785 4570 LS
|
1634 |
|
|
4824 4533 MT 4824 4570 LS
|
1635 |
|
|
4864 4533 MT 4864 4570 LS
|
1636 |
|
|
4904 4533 MT 4904 4570 LS
|
1637 |
|
|
4944 4533 MT 4944 4570 LS
|
1638 |
|
|
4984 4533 MT 4984 4570 LS
|
1639 |
|
|
5024 4533 MT 5024 4570 LS
|
1640 |
|
|
5063 4533 MT 5063 4570 LS
|
1641 |
|
|
4705 4506 MT 4705 4570 LS
|
1642 |
|
|
5143 4533 MT 5143 4570 LS
|
1643 |
|
|
5183 4533 MT 5183 4570 LS
|
1644 |
|
|
5222 4533 MT 5222 4570 LS
|
1645 |
|
|
5262 4533 MT 5262 4570 LS
|
1646 |
|
|
5302 4533 MT 5302 4570 LS
|
1647 |
|
|
5342 4533 MT 5342 4570 LS
|
1648 |
|
|
5382 4533 MT 5382 4570 LS
|
1649 |
|
|
5422 4533 MT 5422 4570 LS
|
1650 |
|
|
5461 4533 MT 5461 4570 LS
|
1651 |
|
|
5103 4506 MT 5103 4570 LS
|
1652 |
|
|
(120) 5103 4649 WT TS RSS
|
1653 |
|
|
5541 4533 MT 5541 4570 LS
|
1654 |
|
|
5581 4533 MT 5581 4570 LS
|
1655 |
|
|
5620 4533 MT 5620 4570 LS
|
1656 |
|
|
5660 4533 MT 5660 4570 LS
|
1657 |
|
|
5700 4533 MT 5700 4570 LS
|
1658 |
|
|
5740 4533 MT 5740 4570 LS
|
1659 |
|
|
5780 4533 MT 5780 4570 LS
|
1660 |
|
|
5820 4533 MT 5820 4570 LS
|
1661 |
|
|
5859 4533 MT 5859 4570 LS
|
1662 |
|
|
5501 4506 MT 5501 4570 LS
|
1663 |
|
|
5939 4533 MT 5939 4570 LS
|
1664 |
|
|
5979 4533 MT 5979 4570 LS
|
1665 |
|
|
6018 4533 MT 6018 4570 LS
|
1666 |
|
|
6058 4533 MT 6058 4570 LS
|
1667 |
|
|
6098 4533 MT 6098 4570 LS
|
1668 |
|
|
6138 4533 MT 6138 4570 LS
|
1669 |
|
|
6178 4533 MT 6178 4570 LS
|
1670 |
|
|
6218 4533 MT 6218 4570 LS
|
1671 |
|
|
6257 4533 MT 6257 4570 LS
|
1672 |
|
|
5899 4506 MT 5899 4570 LS
|
1673 |
|
|
(140) 5899 4649 WT TS RSS
|
1674 |
|
|
6337 4533 MT 6337 4570 LS
|
1675 |
|
|
6377 4533 MT 6377 4570 LS
|
1676 |
|
|
6416 4533 MT 6416 4570 LS
|
1677 |
|
|
6456 4533 MT 6456 4570 LS
|
1678 |
|
|
6496 4533 MT 6496 4570 LS
|
1679 |
|
|
6536 4533 MT 6536 4570 LS
|
1680 |
|
|
6576 4533 MT 6576 4570 LS
|
1681 |
|
|
6616 4533 MT 6616 4570 LS
|
1682 |
|
|
6655 4533 MT 6655 4570 LS
|
1683 |
|
|
6297 4506 MT 6297 4570 LS
|
1684 |
|
|
% draw grid
|
1685 |
|
|
3511 300 MT 3511 4506 LS
|
1686 |
|
|
3909 300 MT 3909 4506 LS
|
1687 |
|
|
4307 300 MT 4307 4506 LS
|
1688 |
|
|
4705 300 MT 4705 4506 LS
|
1689 |
|
|
5103 300 MT 5103 4506 LS
|
1690 |
|
|
5501 300 MT 5501 4506 LS
|
1691 |
|
|
5899 300 MT 5899 4506 LS
|
1692 |
|
|
6297 300 MT 6297 4506 LS
|
1693 |
|
|
% draw waveforms
|
1694 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) 3275 409 WT TSE RSS
|
1695 |
|
|
3504 300 MT 3518 300 LS
|
1696 |
|
|
3902 300 MT 3916 300 LS
|
1697 |
|
|
4300 300 MT 4314 300 LS
|
1698 |
|
|
4698 300 MT 4712 300 LS
|
1699 |
|
|
5096 300 MT 5110 300 LS
|
1700 |
|
|
5494 300 MT 5508 300 LS
|
1701 |
|
|
5892 300 MT 5906 300 LS
|
1702 |
|
|
6290 300 MT 6304 300 LS
|
1703 |
|
|
3312 410 MT 6297 410 LS
|
1704 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) 3275 553 WT TSE RSS
|
1705 |
|
|
3504 444 MT 3518 444 LS
|
1706 |
|
|
3902 444 MT 3916 444 LS
|
1707 |
|
|
4300 444 MT 4314 444 LS
|
1708 |
|
|
4698 444 MT 4712 444 LS
|
1709 |
|
|
5096 444 MT 5110 444 LS
|
1710 |
|
|
5494 444 MT 5508 444 LS
|
1711 |
|
|
5892 444 MT 5906 444 LS
|
1712 |
|
|
6290 444 MT 6304 444 LS
|
1713 |
|
|
3312 554 MT 6297 554 LS
|
1714 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) 3275 697 WT TSE RSS
|
1715 |
|
|
3504 588 MT 3518 588 LS
|
1716 |
|
|
3902 588 MT 3916 588 LS
|
1717 |
|
|
4300 588 MT 4314 588 LS
|
1718 |
|
|
4698 588 MT 4712 588 LS
|
1719 |
|
|
5096 588 MT 5110 588 LS
|
1720 |
|
|
5494 588 MT 5508 588 LS
|
1721 |
|
|
5892 588 MT 5906 588 LS
|
1722 |
|
|
6290 588 MT 6304 588 LS
|
1723 |
|
|
3312 698 MT 6297 698 LS
|
1724 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) 3275 841 WT TSE RSS
|
1725 |
|
|
3504 732 MT 3518 732 LS
|
1726 |
|
|
3902 732 MT 3916 732 LS
|
1727 |
|
|
4300 732 MT 4314 732 LS
|
1728 |
|
|
4698 732 MT 4712 732 LS
|
1729 |
|
|
5096 732 MT 5110 732 LS
|
1730 |
|
|
5494 732 MT 5508 732 LS
|
1731 |
|
|
5892 732 MT 5906 732 LS
|
1732 |
|
|
6290 732 MT 6304 732 LS
|
1733 |
|
|
3312 842 MT 6297 842 LS
|
1734 |
|
|
% draw footer
|
1735 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 2 Page: 4) 300 4799 WT TSW RSS
|
1736 |
|
|
grestore
|
1737 |
|
|
showpage
|
1738 |
|
|
%%Page: 5 5
|
1739 |
|
|
gsave
|
1740 |
|
|
90 rotate 0.12 dup neg scale
|
1741 |
|
|
% dump string table
|
1742 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
1743 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
1744 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
1745 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
1746 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
1747 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
1748 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
1749 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
1750 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
1751 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
1752 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
1753 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
1754 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
1755 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
1756 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
1757 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
1758 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
1759 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
1760 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
1761 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
1762 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
1763 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
1764 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
1765 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
1766 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
1767 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
1768 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
1769 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
1770 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
1771 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
1772 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
1773 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
1774 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
1775 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
1776 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
1777 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
1778 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
1779 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
1780 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
1781 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
1782 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
1783 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
1784 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
1785 |
|
|
% draw waveform shading
|
1786 |
|
|
[] 0 SD
|
1787 |
|
|
2.995 setlinewidth
|
1788 |
|
|
|
1789 |
|
|
|
1790 |
|
|
|
1791 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
1792 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
1793 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
1794 |
|
|
3312 474 MT 3312 554 LS
|
1795 |
|
|
3312 554 MT 3511 554 LS
|
1796 |
|
|
3511 554 MT 3511 474 LS
|
1797 |
|
|
3511 474 MT 3710 474 LS
|
1798 |
|
|
3710 474 MT 3710 554 LS
|
1799 |
|
|
3710 554 MT 3909 554 LS
|
1800 |
|
|
3909 554 MT 3909 474 LS
|
1801 |
|
|
3909 474 MT 4108 474 LS
|
1802 |
|
|
4108 474 MT 4108 554 LS
|
1803 |
|
|
4108 554 MT 4307 554 LS
|
1804 |
|
|
4307 554 MT 4307 474 LS
|
1805 |
|
|
4307 474 MT 4506 474 LS
|
1806 |
|
|
4506 474 MT 4506 554 LS
|
1807 |
|
|
4506 554 MT 4705 554 LS
|
1808 |
|
|
4705 554 MT 4705 474 LS
|
1809 |
|
|
4705 474 MT 4904 474 LS
|
1810 |
|
|
4904 474 MT 4904 554 LS
|
1811 |
|
|
4904 554 MT 5103 554 LS
|
1812 |
|
|
5103 554 MT 5103 474 LS
|
1813 |
|
|
5103 474 MT 5302 474 LS
|
1814 |
|
|
5302 474 MT 5302 554 LS
|
1815 |
|
|
5302 554 MT 5501 554 LS
|
1816 |
|
|
5501 554 MT 5501 474 LS
|
1817 |
|
|
5501 474 MT 5700 474 LS
|
1818 |
|
|
5700 474 MT 5700 554 LS
|
1819 |
|
|
5700 554 MT 5899 554 LS
|
1820 |
|
|
5899 554 MT 5899 474 LS
|
1821 |
|
|
5899 474 MT 6098 474 LS
|
1822 |
|
|
6098 474 MT 6098 554 LS
|
1823 |
|
|
6098 554 MT 6297 554 LS
|
1824 |
|
|
3312 698 MT 6297 698 LS
|
1825 |
|
|
3312 842 MT 6297 842 LS
|
1826 |
|
|
3312 986 MT 6297 986 LS
|
1827 |
|
|
3312 1090 MT 6297 1090 LS
|
1828 |
|
|
3312 1234 MT 6297 1234 LS
|
1829 |
|
|
3312 1378 MT 6297 1378 LS
|
1830 |
|
|
3312 1522 MT 6297 1522 LS
|
1831 |
|
|
3312 1666 MT 6297 1666 LS
|
1832 |
|
|
3312 1810 MT 6297 1810 LS
|
1833 |
|
|
3312 1954 MT 6297 1954 LS
|
1834 |
|
|
3312 2098 MT 6297 2098 LS
|
1835 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
1836 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
1837 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
1838 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
1839 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
1840 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
1841 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
1842 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
1843 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
1844 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
1845 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
1846 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
1847 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
1848 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
1849 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
1850 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
1851 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
1852 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
1853 |
|
|
3312 3106 MT 6297 3106 LS
|
1854 |
|
|
3312 3250 MT 6297 3250 LS
|
1855 |
|
|
3312 3394 MT 6297 3394 LS
|
1856 |
|
|
3312 3538 MT 6297 3538 LS
|
1857 |
|
|
3312 3682 MT 6297 3682 LS
|
1858 |
|
|
3312 3826 MT 6297 3826 LS
|
1859 |
|
|
3312 3929 MT 3312 3929 LT 3504 3929 LT 3511 3970 LT ST
|
1860 |
|
|
3312 4010 MT 3312 4010 LT 3504 4010 LT 3511 3970 LT ST
|
1861 |
|
|
(3) 3326 3970 WT pop 0 originOffset 37 add RSS
|
1862 |
|
|
3511 3970 MT 3511 3970 LT 3518 3929 LT 3902 3929 LT 3909 3970 LT ST
|
1863 |
|
|
3511 3970 MT 3511 3970 LT 3518 4010 LT 3902 4010 LT 3909 3970 LT ST
|
1864 |
|
|
(4) 3525 3970 WT pop 0 originOffset 37 add RSS
|
1865 |
|
|
3909 3970 MT 3909 3970 LT 3916 3929 LT 4300 3929 LT 4307 3970 LT ST
|
1866 |
|
|
3909 3970 MT 3909 3970 LT 3916 4010 LT 4300 4010 LT 4307 3970 LT ST
|
1867 |
|
|
(5) 3923 3970 WT pop 0 originOffset 37 add RSS
|
1868 |
|
|
4307 3970 MT 4307 3970 LT 4314 3929 LT 4698 3929 LT 4705 3970 LT ST
|
1869 |
|
|
4307 3970 MT 4307 3970 LT 4314 4010 LT 4698 4010 LT 4705 3970 LT ST
|
1870 |
|
|
(6) 4321 3970 WT pop 0 originOffset 37 add RSS
|
1871 |
|
|
4705 3970 MT 4705 3970 LT 4712 3929 LT 5096 3929 LT 5103 3970 LT ST
|
1872 |
|
|
4705 3970 MT 4705 3970 LT 4712 4010 LT 5096 4010 LT 5103 3970 LT ST
|
1873 |
|
|
(7) 4719 3970 WT pop 0 originOffset 37 add RSS
|
1874 |
|
|
5103 3970 MT 5103 3970 LT 5110 3929 LT 5494 3929 LT 5501 3970 LT ST
|
1875 |
|
|
5103 3970 MT 5103 3970 LT 5110 4010 LT 5494 4010 LT 5501 3970 LT ST
|
1876 |
|
|
(0) 5117 3970 WT pop 0 originOffset 37 add RSS
|
1877 |
|
|
5501 3970 MT 5501 3970 LT 5508 3929 LT 5892 3929 LT 5899 3970 LT ST
|
1878 |
|
|
5501 3970 MT 5501 3970 LT 5508 4010 LT 5892 4010 LT 5899 3970 LT ST
|
1879 |
|
|
(1) 5515 3970 WT pop 0 originOffset 37 add RSS
|
1880 |
|
|
5899 3970 MT 5899 3970 LT 5906 3929 LT 6297 3929 LT ST
|
1881 |
|
|
5899 3970 MT 5899 3970 LT 5906 4010 LT 6297 4010 LT ST
|
1882 |
|
|
(2) 5913 3970 WT pop 0 originOffset 37 add RSS
|
1883 |
|
|
3312 4073 MT 3312 4073 LT 3504 4073 LT 3511 4114 LT ST
|
1884 |
|
|
3312 4154 MT 3312 4154 LT 3504 4154 LT 3511 4114 LT ST
|
1885 |
|
|
(3) 3326 4114 WT pop 0 originOffset 37 add RSS
|
1886 |
|
|
3511 4114 MT 3511 4114 LT 3518 4073 LT 3902 4073 LT 3909 4114 LT ST
|
1887 |
|
|
3511 4114 MT 3511 4114 LT 3518 4154 LT 3902 4154 LT 3909 4114 LT ST
|
1888 |
|
|
(4) 3525 4114 WT pop 0 originOffset 37 add RSS
|
1889 |
|
|
3909 4114 MT 3909 4114 LT 3916 4073 LT 4300 4073 LT 4307 4114 LT ST
|
1890 |
|
|
3909 4114 MT 3909 4114 LT 3916 4154 LT 4300 4154 LT 4307 4114 LT ST
|
1891 |
|
|
(5) 3923 4114 WT pop 0 originOffset 37 add RSS
|
1892 |
|
|
4307 4114 MT 4307 4114 LT 4314 4073 LT 4698 4073 LT 4705 4114 LT ST
|
1893 |
|
|
4307 4114 MT 4307 4114 LT 4314 4154 LT 4698 4154 LT 4705 4114 LT ST
|
1894 |
|
|
(6) 4321 4114 WT pop 0 originOffset 37 add RSS
|
1895 |
|
|
4705 4114 MT 4705 4114 LT 4712 4073 LT 5096 4073 LT 5103 4114 LT ST
|
1896 |
|
|
4705 4114 MT 4705 4114 LT 4712 4154 LT 5096 4154 LT 5103 4114 LT ST
|
1897 |
|
|
(7) 4719 4114 WT pop 0 originOffset 37 add RSS
|
1898 |
|
|
5103 4114 MT 5103 4114 LT 5110 4073 LT 5494 4073 LT 5501 4114 LT ST
|
1899 |
|
|
5103 4114 MT 5103 4114 LT 5110 4154 LT 5494 4154 LT 5501 4114 LT ST
|
1900 |
|
|
(0) 5117 4114 WT pop 0 originOffset 37 add RSS
|
1901 |
|
|
5501 4114 MT 5501 4114 LT 5508 4073 LT 5892 4073 LT 5899 4114 LT ST
|
1902 |
|
|
5501 4114 MT 5501 4114 LT 5508 4154 LT 5892 4154 LT 5899 4114 LT ST
|
1903 |
|
|
(1) 5515 4114 WT pop 0 originOffset 37 add RSS
|
1904 |
|
|
5899 4114 MT 5899 4114 LT 5906 4073 LT 6297 4073 LT ST
|
1905 |
|
|
5899 4114 MT 5899 4114 LT 5906 4154 LT 6297 4154 LT ST
|
1906 |
|
|
(2) 5913 4114 WT pop 0 originOffset 37 add RSS
|
1907 |
|
|
3312 4258 MT 6297 4258 LS
|
1908 |
|
|
3312 4402 MT 6297 4402 LS
|
1909 |
|
|
% draw timeline
|
1910 |
|
|
3352 4533 MT 3352 4570 LS
|
1911 |
|
|
3392 4533 MT 3392 4570 LS
|
1912 |
|
|
3431 4533 MT 3431 4570 LS
|
1913 |
|
|
3471 4533 MT 3471 4570 LS
|
1914 |
|
|
3511 4533 MT 3511 4570 LS
|
1915 |
|
|
3551 4533 MT 3551 4570 LS
|
1916 |
|
|
3591 4533 MT 3591 4570 LS
|
1917 |
|
|
3631 4533 MT 3631 4570 LS
|
1918 |
|
|
3670 4533 MT 3670 4570 LS
|
1919 |
|
|
3750 4533 MT 3750 4570 LS
|
1920 |
|
|
3790 4533 MT 3790 4570 LS
|
1921 |
|
|
3829 4533 MT 3829 4570 LS
|
1922 |
|
|
3869 4533 MT 3869 4570 LS
|
1923 |
|
|
3909 4533 MT 3909 4570 LS
|
1924 |
|
|
3949 4533 MT 3949 4570 LS
|
1925 |
|
|
3989 4533 MT 3989 4570 LS
|
1926 |
|
|
4029 4533 MT 4029 4570 LS
|
1927 |
|
|
4068 4533 MT 4068 4570 LS
|
1928 |
|
|
3710 4506 MT 3710 4570 LS
|
1929 |
|
|
(160) 3710 4649 WT TS RSS
|
1930 |
|
|
4148 4533 MT 4148 4570 LS
|
1931 |
|
|
4188 4533 MT 4188 4570 LS
|
1932 |
|
|
4227 4533 MT 4227 4570 LS
|
1933 |
|
|
4267 4533 MT 4267 4570 LS
|
1934 |
|
|
4307 4533 MT 4307 4570 LS
|
1935 |
|
|
4347 4533 MT 4347 4570 LS
|
1936 |
|
|
4387 4533 MT 4387 4570 LS
|
1937 |
|
|
4427 4533 MT 4427 4570 LS
|
1938 |
|
|
4466 4533 MT 4466 4570 LS
|
1939 |
|
|
4108 4506 MT 4108 4570 LS
|
1940 |
|
|
4546 4533 MT 4546 4570 LS
|
1941 |
|
|
4586 4533 MT 4586 4570 LS
|
1942 |
|
|
4625 4533 MT 4625 4570 LS
|
1943 |
|
|
4665 4533 MT 4665 4570 LS
|
1944 |
|
|
4705 4533 MT 4705 4570 LS
|
1945 |
|
|
4745 4533 MT 4745 4570 LS
|
1946 |
|
|
4785 4533 MT 4785 4570 LS
|
1947 |
|
|
4825 4533 MT 4825 4570 LS
|
1948 |
|
|
4864 4533 MT 4864 4570 LS
|
1949 |
|
|
4506 4506 MT 4506 4570 LS
|
1950 |
|
|
(180) 4506 4649 WT TS RSS
|
1951 |
|
|
4944 4533 MT 4944 4570 LS
|
1952 |
|
|
4984 4533 MT 4984 4570 LS
|
1953 |
|
|
5023 4533 MT 5023 4570 LS
|
1954 |
|
|
5063 4533 MT 5063 4570 LS
|
1955 |
|
|
5103 4533 MT 5103 4570 LS
|
1956 |
|
|
5143 4533 MT 5143 4570 LS
|
1957 |
|
|
5183 4533 MT 5183 4570 LS
|
1958 |
|
|
5223 4533 MT 5223 4570 LS
|
1959 |
|
|
5262 4533 MT 5262 4570 LS
|
1960 |
|
|
4904 4506 MT 4904 4570 LS
|
1961 |
|
|
5342 4533 MT 5342 4570 LS
|
1962 |
|
|
5382 4533 MT 5382 4570 LS
|
1963 |
|
|
5421 4533 MT 5421 4570 LS
|
1964 |
|
|
5461 4533 MT 5461 4570 LS
|
1965 |
|
|
5501 4533 MT 5501 4570 LS
|
1966 |
|
|
5541 4533 MT 5541 4570 LS
|
1967 |
|
|
5581 4533 MT 5581 4570 LS
|
1968 |
|
|
5621 4533 MT 5621 4570 LS
|
1969 |
|
|
5660 4533 MT 5660 4570 LS
|
1970 |
|
|
5302 4506 MT 5302 4570 LS
|
1971 |
|
|
(200) 5302 4649 WT TS RSS
|
1972 |
|
|
5740 4533 MT 5740 4570 LS
|
1973 |
|
|
5780 4533 MT 5780 4570 LS
|
1974 |
|
|
5819 4533 MT 5819 4570 LS
|
1975 |
|
|
5859 4533 MT 5859 4570 LS
|
1976 |
|
|
5899 4533 MT 5899 4570 LS
|
1977 |
|
|
5939 4533 MT 5939 4570 LS
|
1978 |
|
|
5979 4533 MT 5979 4570 LS
|
1979 |
|
|
6019 4533 MT 6019 4570 LS
|
1980 |
|
|
6058 4533 MT 6058 4570 LS
|
1981 |
|
|
5700 4506 MT 5700 4570 LS
|
1982 |
|
|
6138 4533 MT 6138 4570 LS
|
1983 |
|
|
6178 4533 MT 6178 4570 LS
|
1984 |
|
|
6217 4533 MT 6217 4570 LS
|
1985 |
|
|
6257 4533 MT 6257 4570 LS
|
1986 |
|
|
6297 4533 MT 6297 4570 LS
|
1987 |
|
|
6337 4533 MT 6337 4570 LS
|
1988 |
|
|
6377 4533 MT 6377 4570 LS
|
1989 |
|
|
6417 4533 MT 6417 4570 LS
|
1990 |
|
|
6456 4533 MT 6456 4570 LS
|
1991 |
|
|
6098 4506 MT 6098 4570 LS
|
1992 |
|
|
(220) 6098 4649 WT TS RSS
|
1993 |
|
|
% draw grid
|
1994 |
|
|
3710 300 MT 3710 4506 LS
|
1995 |
|
|
4108 300 MT 4108 4506 LS
|
1996 |
|
|
4506 300 MT 4506 4506 LS
|
1997 |
|
|
4904 300 MT 4904 4506 LS
|
1998 |
|
|
5302 300 MT 5302 4506 LS
|
1999 |
|
|
5700 300 MT 5700 4506 LS
|
2000 |
|
|
6098 300 MT 6098 4506 LS
|
2001 |
|
|
% draw waveforms
|
2002 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) 3275 409 WT TSE RSS
|
2003 |
|
|
3703 300 MT 3717 300 LS
|
2004 |
|
|
4101 300 MT 4115 300 LS
|
2005 |
|
|
4499 300 MT 4513 300 LS
|
2006 |
|
|
4897 300 MT 4911 300 LS
|
2007 |
|
|
5295 300 MT 5309 300 LS
|
2008 |
|
|
5693 300 MT 5707 300 LS
|
2009 |
|
|
6091 300 MT 6105 300 LS
|
2010 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
2011 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
2012 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
2013 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) 3275 553 WT TSE RSS
|
2014 |
|
|
3703 444 MT 3717 444 LS
|
2015 |
|
|
4101 444 MT 4115 444 LS
|
2016 |
|
|
4499 444 MT 4513 444 LS
|
2017 |
|
|
4897 444 MT 4911 444 LS
|
2018 |
|
|
5295 444 MT 5309 444 LS
|
2019 |
|
|
5693 444 MT 5707 444 LS
|
2020 |
|
|
6091 444 MT 6105 444 LS
|
2021 |
|
|
3312 474 MT 3312 554 LS
|
2022 |
|
|
3312 554 MT 3511 554 LS
|
2023 |
|
|
3511 554 MT 3511 474 LS
|
2024 |
|
|
3511 474 MT 3710 474 LS
|
2025 |
|
|
3710 474 MT 3710 554 LS
|
2026 |
|
|
3710 554 MT 3909 554 LS
|
2027 |
|
|
3909 554 MT 3909 474 LS
|
2028 |
|
|
3909 474 MT 4108 474 LS
|
2029 |
|
|
4108 474 MT 4108 554 LS
|
2030 |
|
|
4108 554 MT 4307 554 LS
|
2031 |
|
|
4307 554 MT 4307 474 LS
|
2032 |
|
|
4307 474 MT 4506 474 LS
|
2033 |
|
|
4506 474 MT 4506 554 LS
|
2034 |
|
|
4506 554 MT 4705 554 LS
|
2035 |
|
|
4705 554 MT 4705 474 LS
|
2036 |
|
|
4705 474 MT 4904 474 LS
|
2037 |
|
|
4904 474 MT 4904 554 LS
|
2038 |
|
|
4904 554 MT 5103 554 LS
|
2039 |
|
|
5103 554 MT 5103 474 LS
|
2040 |
|
|
5103 474 MT 5302 474 LS
|
2041 |
|
|
5302 474 MT 5302 554 LS
|
2042 |
|
|
5302 554 MT 5501 554 LS
|
2043 |
|
|
5501 554 MT 5501 474 LS
|
2044 |
|
|
5501 474 MT 5700 474 LS
|
2045 |
|
|
5700 474 MT 5700 554 LS
|
2046 |
|
|
5700 554 MT 5899 554 LS
|
2047 |
|
|
5899 554 MT 5899 474 LS
|
2048 |
|
|
5899 474 MT 6098 474 LS
|
2049 |
|
|
6098 474 MT 6098 554 LS
|
2050 |
|
|
6098 554 MT 6297 554 LS
|
2051 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) 3275 697 WT TSE RSS
|
2052 |
|
|
3703 588 MT 3717 588 LS
|
2053 |
|
|
4101 588 MT 4115 588 LS
|
2054 |
|
|
4499 588 MT 4513 588 LS
|
2055 |
|
|
4897 588 MT 4911 588 LS
|
2056 |
|
|
5295 588 MT 5309 588 LS
|
2057 |
|
|
5693 588 MT 5707 588 LS
|
2058 |
|
|
6091 588 MT 6105 588 LS
|
2059 |
|
|
3312 698 MT 6297 698 LS
|
2060 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) 3275 841 WT TSE RSS
|
2061 |
|
|
3703 732 MT 3717 732 LS
|
2062 |
|
|
4101 732 MT 4115 732 LS
|
2063 |
|
|
4499 732 MT 4513 732 LS
|
2064 |
|
|
4897 732 MT 4911 732 LS
|
2065 |
|
|
5295 732 MT 5309 732 LS
|
2066 |
|
|
5693 732 MT 5707 732 LS
|
2067 |
|
|
6091 732 MT 6105 732 LS
|
2068 |
|
|
3312 842 MT 6297 842 LS
|
2069 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) 3275 985 WT TSE RSS
|
2070 |
|
|
3703 876 MT 3717 876 LS
|
2071 |
|
|
4101 876 MT 4115 876 LS
|
2072 |
|
|
4499 876 MT 4513 876 LS
|
2073 |
|
|
4897 876 MT 4911 876 LS
|
2074 |
|
|
5295 876 MT 5309 876 LS
|
2075 |
|
|
5693 876 MT 5707 876 LS
|
2076 |
|
|
6091 876 MT 6105 876 LS
|
2077 |
|
|
3312 986 MT 6297 986 LS
|
2078 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) 3275 1129 WT TSE RSS
|
2079 |
|
|
3703 1020 MT 3717 1020 LS
|
2080 |
|
|
4101 1020 MT 4115 1020 LS
|
2081 |
|
|
4499 1020 MT 4513 1020 LS
|
2082 |
|
|
4897 1020 MT 4911 1020 LS
|
2083 |
|
|
5295 1020 MT 5309 1020 LS
|
2084 |
|
|
5693 1020 MT 5707 1020 LS
|
2085 |
|
|
6091 1020 MT 6105 1020 LS
|
2086 |
|
|
3312 1090 MT 6297 1090 LS
|
2087 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) 3275 1273 WT TSE RSS
|
2088 |
|
|
3703 1164 MT 3717 1164 LS
|
2089 |
|
|
4101 1164 MT 4115 1164 LS
|
2090 |
|
|
4499 1164 MT 4513 1164 LS
|
2091 |
|
|
4897 1164 MT 4911 1164 LS
|
2092 |
|
|
5295 1164 MT 5309 1164 LS
|
2093 |
|
|
5693 1164 MT 5707 1164 LS
|
2094 |
|
|
6091 1164 MT 6105 1164 LS
|
2095 |
|
|
3312 1234 MT 6297 1234 LS
|
2096 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) 3275 1417 WT TSE RSS
|
2097 |
|
|
3703 1308 MT 3717 1308 LS
|
2098 |
|
|
4101 1308 MT 4115 1308 LS
|
2099 |
|
|
4499 1308 MT 4513 1308 LS
|
2100 |
|
|
4897 1308 MT 4911 1308 LS
|
2101 |
|
|
5295 1308 MT 5309 1308 LS
|
2102 |
|
|
5693 1308 MT 5707 1308 LS
|
2103 |
|
|
6091 1308 MT 6105 1308 LS
|
2104 |
|
|
3312 1378 MT 6297 1378 LS
|
2105 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) 3275 1561 WT TSE RSS
|
2106 |
|
|
3703 1452 MT 3717 1452 LS
|
2107 |
|
|
4101 1452 MT 4115 1452 LS
|
2108 |
|
|
4499 1452 MT 4513 1452 LS
|
2109 |
|
|
4897 1452 MT 4911 1452 LS
|
2110 |
|
|
5295 1452 MT 5309 1452 LS
|
2111 |
|
|
5693 1452 MT 5707 1452 LS
|
2112 |
|
|
6091 1452 MT 6105 1452 LS
|
2113 |
|
|
3312 1522 MT 6297 1522 LS
|
2114 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) 3275 1705 WT TSE RSS
|
2115 |
|
|
3703 1596 MT 3717 1596 LS
|
2116 |
|
|
4101 1596 MT 4115 1596 LS
|
2117 |
|
|
4499 1596 MT 4513 1596 LS
|
2118 |
|
|
4897 1596 MT 4911 1596 LS
|
2119 |
|
|
5295 1596 MT 5309 1596 LS
|
2120 |
|
|
5693 1596 MT 5707 1596 LS
|
2121 |
|
|
6091 1596 MT 6105 1596 LS
|
2122 |
|
|
3312 1666 MT 6297 1666 LS
|
2123 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) 3275 1849 WT TSE RSS
|
2124 |
|
|
3703 1740 MT 3717 1740 LS
|
2125 |
|
|
4101 1740 MT 4115 1740 LS
|
2126 |
|
|
4499 1740 MT 4513 1740 LS
|
2127 |
|
|
4897 1740 MT 4911 1740 LS
|
2128 |
|
|
5295 1740 MT 5309 1740 LS
|
2129 |
|
|
5693 1740 MT 5707 1740 LS
|
2130 |
|
|
6091 1740 MT 6105 1740 LS
|
2131 |
|
|
3312 1810 MT 6297 1810 LS
|
2132 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) 3275 1993 WT TSE RSS
|
2133 |
|
|
3703 1884 MT 3717 1884 LS
|
2134 |
|
|
4101 1884 MT 4115 1884 LS
|
2135 |
|
|
4499 1884 MT 4513 1884 LS
|
2136 |
|
|
4897 1884 MT 4911 1884 LS
|
2137 |
|
|
5295 1884 MT 5309 1884 LS
|
2138 |
|
|
5693 1884 MT 5707 1884 LS
|
2139 |
|
|
6091 1884 MT 6105 1884 LS
|
2140 |
|
|
3312 1954 MT 6297 1954 LS
|
2141 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) 3275 2137 WT TSE RSS
|
2142 |
|
|
3703 2028 MT 3717 2028 LS
|
2143 |
|
|
4101 2028 MT 4115 2028 LS
|
2144 |
|
|
4499 2028 MT 4513 2028 LS
|
2145 |
|
|
4897 2028 MT 4911 2028 LS
|
2146 |
|
|
5295 2028 MT 5309 2028 LS
|
2147 |
|
|
5693 2028 MT 5707 2028 LS
|
2148 |
|
|
6091 2028 MT 6105 2028 LS
|
2149 |
|
|
3312 2098 MT 6297 2098 LS
|
2150 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) 3275 2281 WT TSE RSS
|
2151 |
|
|
3703 2172 MT 3717 2172 LS
|
2152 |
|
|
4101 2172 MT 4115 2172 LS
|
2153 |
|
|
4499 2172 MT 4513 2172 LS
|
2154 |
|
|
4897 2172 MT 4911 2172 LS
|
2155 |
|
|
5295 2172 MT 5309 2172 LS
|
2156 |
|
|
5693 2172 MT 5707 2172 LS
|
2157 |
|
|
6091 2172 MT 6105 2172 LS
|
2158 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
2159 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
2160 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
2161 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) 3275 2425 WT TSE RSS
|
2162 |
|
|
3703 2316 MT 3717 2316 LS
|
2163 |
|
|
4101 2316 MT 4115 2316 LS
|
2164 |
|
|
4499 2316 MT 4513 2316 LS
|
2165 |
|
|
4897 2316 MT 4911 2316 LS
|
2166 |
|
|
5295 2316 MT 5309 2316 LS
|
2167 |
|
|
5693 2316 MT 5707 2316 LS
|
2168 |
|
|
6091 2316 MT 6105 2316 LS
|
2169 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
2170 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
2171 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
2172 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) 3275 2569 WT TSE RSS
|
2173 |
|
|
3703 2460 MT 3717 2460 LS
|
2174 |
|
|
4101 2460 MT 4115 2460 LS
|
2175 |
|
|
4499 2460 MT 4513 2460 LS
|
2176 |
|
|
4897 2460 MT 4911 2460 LS
|
2177 |
|
|
5295 2460 MT 5309 2460 LS
|
2178 |
|
|
5693 2460 MT 5707 2460 LS
|
2179 |
|
|
6091 2460 MT 6105 2460 LS
|
2180 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
2181 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
2182 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
2183 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) 3275 2713 WT TSE RSS
|
2184 |
|
|
3703 2604 MT 3717 2604 LS
|
2185 |
|
|
4101 2604 MT 4115 2604 LS
|
2186 |
|
|
4499 2604 MT 4513 2604 LS
|
2187 |
|
|
4897 2604 MT 4911 2604 LS
|
2188 |
|
|
5295 2604 MT 5309 2604 LS
|
2189 |
|
|
5693 2604 MT 5707 2604 LS
|
2190 |
|
|
6091 2604 MT 6105 2604 LS
|
2191 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
2192 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
2193 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
2194 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) 3275 2857 WT TSE RSS
|
2195 |
|
|
3703 2748 MT 3717 2748 LS
|
2196 |
|
|
4101 2748 MT 4115 2748 LS
|
2197 |
|
|
4499 2748 MT 4513 2748 LS
|
2198 |
|
|
4897 2748 MT 4911 2748 LS
|
2199 |
|
|
5295 2748 MT 5309 2748 LS
|
2200 |
|
|
5693 2748 MT 5707 2748 LS
|
2201 |
|
|
6091 2748 MT 6105 2748 LS
|
2202 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
2203 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
2204 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
2205 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) 3275 3001 WT TSE RSS
|
2206 |
|
|
3703 2892 MT 3717 2892 LS
|
2207 |
|
|
4101 2892 MT 4115 2892 LS
|
2208 |
|
|
4499 2892 MT 4513 2892 LS
|
2209 |
|
|
4897 2892 MT 4911 2892 LS
|
2210 |
|
|
5295 2892 MT 5309 2892 LS
|
2211 |
|
|
5693 2892 MT 5707 2892 LS
|
2212 |
|
|
6091 2892 MT 6105 2892 LS
|
2213 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
2214 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
2215 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
2216 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) 3275 3145 WT TSE RSS
|
2217 |
|
|
3703 3036 MT 3717 3036 LS
|
2218 |
|
|
4101 3036 MT 4115 3036 LS
|
2219 |
|
|
4499 3036 MT 4513 3036 LS
|
2220 |
|
|
4897 3036 MT 4911 3036 LS
|
2221 |
|
|
5295 3036 MT 5309 3036 LS
|
2222 |
|
|
5693 3036 MT 5707 3036 LS
|
2223 |
|
|
6091 3036 MT 6105 3036 LS
|
2224 |
|
|
3312 3106 MT 6297 3106 LS
|
2225 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) 3275 3289 WT TSE RSS
|
2226 |
|
|
3703 3180 MT 3717 3180 LS
|
2227 |
|
|
4101 3180 MT 4115 3180 LS
|
2228 |
|
|
4499 3180 MT 4513 3180 LS
|
2229 |
|
|
4897 3180 MT 4911 3180 LS
|
2230 |
|
|
5295 3180 MT 5309 3180 LS
|
2231 |
|
|
5693 3180 MT 5707 3180 LS
|
2232 |
|
|
6091 3180 MT 6105 3180 LS
|
2233 |
|
|
3312 3250 MT 6297 3250 LS
|
2234 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) 3275 3433 WT TSE RSS
|
2235 |
|
|
3703 3324 MT 3717 3324 LS
|
2236 |
|
|
4101 3324 MT 4115 3324 LS
|
2237 |
|
|
4499 3324 MT 4513 3324 LS
|
2238 |
|
|
4897 3324 MT 4911 3324 LS
|
2239 |
|
|
5295 3324 MT 5309 3324 LS
|
2240 |
|
|
5693 3324 MT 5707 3324 LS
|
2241 |
|
|
6091 3324 MT 6105 3324 LS
|
2242 |
|
|
3312 3394 MT 6297 3394 LS
|
2243 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) 3275 3577 WT TSE RSS
|
2244 |
|
|
3703 3468 MT 3717 3468 LS
|
2245 |
|
|
4101 3468 MT 4115 3468 LS
|
2246 |
|
|
4499 3468 MT 4513 3468 LS
|
2247 |
|
|
4897 3468 MT 4911 3468 LS
|
2248 |
|
|
5295 3468 MT 5309 3468 LS
|
2249 |
|
|
5693 3468 MT 5707 3468 LS
|
2250 |
|
|
6091 3468 MT 6105 3468 LS
|
2251 |
|
|
3312 3538 MT 6297 3538 LS
|
2252 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) 3275 3721 WT TSE RSS
|
2253 |
|
|
3703 3612 MT 3717 3612 LS
|
2254 |
|
|
4101 3612 MT 4115 3612 LS
|
2255 |
|
|
4499 3612 MT 4513 3612 LS
|
2256 |
|
|
4897 3612 MT 4911 3612 LS
|
2257 |
|
|
5295 3612 MT 5309 3612 LS
|
2258 |
|
|
5693 3612 MT 5707 3612 LS
|
2259 |
|
|
6091 3612 MT 6105 3612 LS
|
2260 |
|
|
3312 3682 MT 6297 3682 LS
|
2261 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) 3275 3865 WT TSE RSS
|
2262 |
|
|
3703 3756 MT 3717 3756 LS
|
2263 |
|
|
4101 3756 MT 4115 3756 LS
|
2264 |
|
|
4499 3756 MT 4513 3756 LS
|
2265 |
|
|
4897 3756 MT 4911 3756 LS
|
2266 |
|
|
5295 3756 MT 5309 3756 LS
|
2267 |
|
|
5693 3756 MT 5707 3756 LS
|
2268 |
|
|
6091 3756 MT 6105 3756 LS
|
2269 |
|
|
3312 3826 MT 6297 3826 LS
|
2270 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) 3275 4009 WT TSE RSS
|
2271 |
|
|
3703 3900 MT 3717 3900 LS
|
2272 |
|
|
4101 3900 MT 4115 3900 LS
|
2273 |
|
|
4499 3900 MT 4513 3900 LS
|
2274 |
|
|
4897 3900 MT 4911 3900 LS
|
2275 |
|
|
5295 3900 MT 5309 3900 LS
|
2276 |
|
|
5693 3900 MT 5707 3900 LS
|
2277 |
|
|
6091 3900 MT 6105 3900 LS
|
2278 |
|
|
3312 3929 MT 3312 3929 LT 3504 3929 LT 3511 3970 LT ST
|
2279 |
|
|
3312 4010 MT 3312 4010 LT 3504 4010 LT 3511 3970 LT ST
|
2280 |
|
|
(3) 3326 3970 WT pop 0 originOffset 37 add RSS
|
2281 |
|
|
3511 3970 MT 3511 3970 LT 3518 3929 LT 3902 3929 LT 3909 3970 LT ST
|
2282 |
|
|
3511 3970 MT 3511 3970 LT 3518 4010 LT 3902 4010 LT 3909 3970 LT ST
|
2283 |
|
|
(4) 3525 3970 WT pop 0 originOffset 37 add RSS
|
2284 |
|
|
3909 3970 MT 3909 3970 LT 3916 3929 LT 4300 3929 LT 4307 3970 LT ST
|
2285 |
|
|
3909 3970 MT 3909 3970 LT 3916 4010 LT 4300 4010 LT 4307 3970 LT ST
|
2286 |
|
|
(5) 3923 3970 WT pop 0 originOffset 37 add RSS
|
2287 |
|
|
4307 3970 MT 4307 3970 LT 4314 3929 LT 4698 3929 LT 4705 3970 LT ST
|
2288 |
|
|
4307 3970 MT 4307 3970 LT 4314 4010 LT 4698 4010 LT 4705 3970 LT ST
|
2289 |
|
|
(6) 4321 3970 WT pop 0 originOffset 37 add RSS
|
2290 |
|
|
4705 3970 MT 4705 3970 LT 4712 3929 LT 5096 3929 LT 5103 3970 LT ST
|
2291 |
|
|
4705 3970 MT 4705 3970 LT 4712 4010 LT 5096 4010 LT 5103 3970 LT ST
|
2292 |
|
|
(7) 4719 3970 WT pop 0 originOffset 37 add RSS
|
2293 |
|
|
5103 3970 MT 5103 3970 LT 5110 3929 LT 5494 3929 LT 5501 3970 LT ST
|
2294 |
|
|
5103 3970 MT 5103 3970 LT 5110 4010 LT 5494 4010 LT 5501 3970 LT ST
|
2295 |
|
|
(0) 5117 3970 WT pop 0 originOffset 37 add RSS
|
2296 |
|
|
5501 3970 MT 5501 3970 LT 5508 3929 LT 5892 3929 LT 5899 3970 LT ST
|
2297 |
|
|
5501 3970 MT 5501 3970 LT 5508 4010 LT 5892 4010 LT 5899 3970 LT ST
|
2298 |
|
|
(1) 5515 3970 WT pop 0 originOffset 37 add RSS
|
2299 |
|
|
5899 3970 MT 5899 3970 LT 5906 3929 LT 6297 3929 LT ST
|
2300 |
|
|
5899 3970 MT 5899 3970 LT 5906 4010 LT 6297 4010 LT ST
|
2301 |
|
|
(2) 5913 3970 WT pop 0 originOffset 37 add RSS
|
2302 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) 3275 4153 WT TSE RSS
|
2303 |
|
|
3703 4044 MT 3717 4044 LS
|
2304 |
|
|
4101 4044 MT 4115 4044 LS
|
2305 |
|
|
4499 4044 MT 4513 4044 LS
|
2306 |
|
|
4897 4044 MT 4911 4044 LS
|
2307 |
|
|
5295 4044 MT 5309 4044 LS
|
2308 |
|
|
5693 4044 MT 5707 4044 LS
|
2309 |
|
|
6091 4044 MT 6105 4044 LS
|
2310 |
|
|
3312 4073 MT 3312 4073 LT 3504 4073 LT 3511 4114 LT ST
|
2311 |
|
|
3312 4154 MT 3312 4154 LT 3504 4154 LT 3511 4114 LT ST
|
2312 |
|
|
(3) 3326 4114 WT pop 0 originOffset 37 add RSS
|
2313 |
|
|
3511 4114 MT 3511 4114 LT 3518 4073 LT 3902 4073 LT 3909 4114 LT ST
|
2314 |
|
|
3511 4114 MT 3511 4114 LT 3518 4154 LT 3902 4154 LT 3909 4114 LT ST
|
2315 |
|
|
(4) 3525 4114 WT pop 0 originOffset 37 add RSS
|
2316 |
|
|
3909 4114 MT 3909 4114 LT 3916 4073 LT 4300 4073 LT 4307 4114 LT ST
|
2317 |
|
|
3909 4114 MT 3909 4114 LT 3916 4154 LT 4300 4154 LT 4307 4114 LT ST
|
2318 |
|
|
(5) 3923 4114 WT pop 0 originOffset 37 add RSS
|
2319 |
|
|
4307 4114 MT 4307 4114 LT 4314 4073 LT 4698 4073 LT 4705 4114 LT ST
|
2320 |
|
|
4307 4114 MT 4307 4114 LT 4314 4154 LT 4698 4154 LT 4705 4114 LT ST
|
2321 |
|
|
(6) 4321 4114 WT pop 0 originOffset 37 add RSS
|
2322 |
|
|
4705 4114 MT 4705 4114 LT 4712 4073 LT 5096 4073 LT 5103 4114 LT ST
|
2323 |
|
|
4705 4114 MT 4705 4114 LT 4712 4154 LT 5096 4154 LT 5103 4114 LT ST
|
2324 |
|
|
(7) 4719 4114 WT pop 0 originOffset 37 add RSS
|
2325 |
|
|
5103 4114 MT 5103 4114 LT 5110 4073 LT 5494 4073 LT 5501 4114 LT ST
|
2326 |
|
|
5103 4114 MT 5103 4114 LT 5110 4154 LT 5494 4154 LT 5501 4114 LT ST
|
2327 |
|
|
(0) 5117 4114 WT pop 0 originOffset 37 add RSS
|
2328 |
|
|
5501 4114 MT 5501 4114 LT 5508 4073 LT 5892 4073 LT 5899 4114 LT ST
|
2329 |
|
|
5501 4114 MT 5501 4114 LT 5508 4154 LT 5892 4154 LT 5899 4114 LT ST
|
2330 |
|
|
(1) 5515 4114 WT pop 0 originOffset 37 add RSS
|
2331 |
|
|
5899 4114 MT 5899 4114 LT 5906 4073 LT 6297 4073 LT ST
|
2332 |
|
|
5899 4114 MT 5899 4114 LT 5906 4154 LT 6297 4154 LT ST
|
2333 |
|
|
(2) 5913 4114 WT pop 0 originOffset 37 add RSS
|
2334 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) 3275 4297 WT TSE RSS
|
2335 |
|
|
3703 4188 MT 3717 4188 LS
|
2336 |
|
|
4101 4188 MT 4115 4188 LS
|
2337 |
|
|
4499 4188 MT 4513 4188 LS
|
2338 |
|
|
4897 4188 MT 4911 4188 LS
|
2339 |
|
|
5295 4188 MT 5309 4188 LS
|
2340 |
|
|
5693 4188 MT 5707 4188 LS
|
2341 |
|
|
6091 4188 MT 6105 4188 LS
|
2342 |
|
|
3312 4258 MT 6297 4258 LS
|
2343 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) 3275 4441 WT TSE RSS
|
2344 |
|
|
3703 4332 MT 3717 4332 LS
|
2345 |
|
|
4101 4332 MT 4115 4332 LS
|
2346 |
|
|
4499 4332 MT 4513 4332 LS
|
2347 |
|
|
4897 4332 MT 4911 4332 LS
|
2348 |
|
|
5295 4332 MT 5309 4332 LS
|
2349 |
|
|
5693 4332 MT 5707 4332 LS
|
2350 |
|
|
6091 4332 MT 6105 4332 LS
|
2351 |
|
|
3312 4402 MT 6297 4402 LS
|
2352 |
|
|
% draw footer
|
2353 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 3 Page: 5) 300 4799 WT TSW RSS
|
2354 |
|
|
grestore
|
2355 |
|
|
showpage
|
2356 |
|
|
%%Page: 6 6
|
2357 |
|
|
gsave
|
2358 |
|
|
90 rotate 0.12 dup neg scale
|
2359 |
|
|
% dump string table
|
2360 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
2361 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
2362 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
2363 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
2364 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
2365 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
2366 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
2367 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
2368 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
2369 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
2370 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
2371 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
2372 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
2373 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
2374 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
2375 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
2376 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
2377 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
2378 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
2379 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
2380 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
2381 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
2382 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
2383 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
2384 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
2385 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
2386 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
2387 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
2388 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
2389 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
2390 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
2391 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
2392 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
2393 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
2394 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
2395 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
2396 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
2397 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
2398 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
2399 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
2400 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
2401 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
2402 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
2403 |
|
|
% draw waveform shading
|
2404 |
|
|
[] 0 SD
|
2405 |
|
|
2.995 setlinewidth
|
2406 |
|
|
|
2407 |
|
|
|
2408 |
|
|
|
2409 |
|
|
3312 410 MT 6297 410 LS
|
2410 |
|
|
3312 554 MT 6297 554 LS
|
2411 |
|
|
3312 698 MT 6297 698 LS
|
2412 |
|
|
3312 842 MT 6297 842 LS
|
2413 |
|
|
% draw timeline
|
2414 |
|
|
3352 4533 MT 3352 4570 LS
|
2415 |
|
|
3392 4533 MT 3392 4570 LS
|
2416 |
|
|
3431 4533 MT 3431 4570 LS
|
2417 |
|
|
3471 4533 MT 3471 4570 LS
|
2418 |
|
|
3511 4533 MT 3511 4570 LS
|
2419 |
|
|
3551 4533 MT 3551 4570 LS
|
2420 |
|
|
3591 4533 MT 3591 4570 LS
|
2421 |
|
|
3631 4533 MT 3631 4570 LS
|
2422 |
|
|
3670 4533 MT 3670 4570 LS
|
2423 |
|
|
3750 4533 MT 3750 4570 LS
|
2424 |
|
|
3790 4533 MT 3790 4570 LS
|
2425 |
|
|
3829 4533 MT 3829 4570 LS
|
2426 |
|
|
3869 4533 MT 3869 4570 LS
|
2427 |
|
|
3909 4533 MT 3909 4570 LS
|
2428 |
|
|
3949 4533 MT 3949 4570 LS
|
2429 |
|
|
3989 4533 MT 3989 4570 LS
|
2430 |
|
|
4029 4533 MT 4029 4570 LS
|
2431 |
|
|
4068 4533 MT 4068 4570 LS
|
2432 |
|
|
3710 4506 MT 3710 4570 LS
|
2433 |
|
|
(160) 3710 4649 WT TS RSS
|
2434 |
|
|
4148 4533 MT 4148 4570 LS
|
2435 |
|
|
4188 4533 MT 4188 4570 LS
|
2436 |
|
|
4227 4533 MT 4227 4570 LS
|
2437 |
|
|
4267 4533 MT 4267 4570 LS
|
2438 |
|
|
4307 4533 MT 4307 4570 LS
|
2439 |
|
|
4347 4533 MT 4347 4570 LS
|
2440 |
|
|
4387 4533 MT 4387 4570 LS
|
2441 |
|
|
4427 4533 MT 4427 4570 LS
|
2442 |
|
|
4466 4533 MT 4466 4570 LS
|
2443 |
|
|
4108 4506 MT 4108 4570 LS
|
2444 |
|
|
4546 4533 MT 4546 4570 LS
|
2445 |
|
|
4586 4533 MT 4586 4570 LS
|
2446 |
|
|
4625 4533 MT 4625 4570 LS
|
2447 |
|
|
4665 4533 MT 4665 4570 LS
|
2448 |
|
|
4705 4533 MT 4705 4570 LS
|
2449 |
|
|
4745 4533 MT 4745 4570 LS
|
2450 |
|
|
4785 4533 MT 4785 4570 LS
|
2451 |
|
|
4825 4533 MT 4825 4570 LS
|
2452 |
|
|
4864 4533 MT 4864 4570 LS
|
2453 |
|
|
4506 4506 MT 4506 4570 LS
|
2454 |
|
|
(180) 4506 4649 WT TS RSS
|
2455 |
|
|
4944 4533 MT 4944 4570 LS
|
2456 |
|
|
4984 4533 MT 4984 4570 LS
|
2457 |
|
|
5023 4533 MT 5023 4570 LS
|
2458 |
|
|
5063 4533 MT 5063 4570 LS
|
2459 |
|
|
5103 4533 MT 5103 4570 LS
|
2460 |
|
|
5143 4533 MT 5143 4570 LS
|
2461 |
|
|
5183 4533 MT 5183 4570 LS
|
2462 |
|
|
5223 4533 MT 5223 4570 LS
|
2463 |
|
|
5262 4533 MT 5262 4570 LS
|
2464 |
|
|
4904 4506 MT 4904 4570 LS
|
2465 |
|
|
5342 4533 MT 5342 4570 LS
|
2466 |
|
|
5382 4533 MT 5382 4570 LS
|
2467 |
|
|
5421 4533 MT 5421 4570 LS
|
2468 |
|
|
5461 4533 MT 5461 4570 LS
|
2469 |
|
|
5501 4533 MT 5501 4570 LS
|
2470 |
|
|
5541 4533 MT 5541 4570 LS
|
2471 |
|
|
5581 4533 MT 5581 4570 LS
|
2472 |
|
|
5621 4533 MT 5621 4570 LS
|
2473 |
|
|
5660 4533 MT 5660 4570 LS
|
2474 |
|
|
5302 4506 MT 5302 4570 LS
|
2475 |
|
|
(200) 5302 4649 WT TS RSS
|
2476 |
|
|
5740 4533 MT 5740 4570 LS
|
2477 |
|
|
5780 4533 MT 5780 4570 LS
|
2478 |
|
|
5819 4533 MT 5819 4570 LS
|
2479 |
|
|
5859 4533 MT 5859 4570 LS
|
2480 |
|
|
5899 4533 MT 5899 4570 LS
|
2481 |
|
|
5939 4533 MT 5939 4570 LS
|
2482 |
|
|
5979 4533 MT 5979 4570 LS
|
2483 |
|
|
6019 4533 MT 6019 4570 LS
|
2484 |
|
|
6058 4533 MT 6058 4570 LS
|
2485 |
|
|
5700 4506 MT 5700 4570 LS
|
2486 |
|
|
6138 4533 MT 6138 4570 LS
|
2487 |
|
|
6178 4533 MT 6178 4570 LS
|
2488 |
|
|
6217 4533 MT 6217 4570 LS
|
2489 |
|
|
6257 4533 MT 6257 4570 LS
|
2490 |
|
|
6297 4533 MT 6297 4570 LS
|
2491 |
|
|
6337 4533 MT 6337 4570 LS
|
2492 |
|
|
6377 4533 MT 6377 4570 LS
|
2493 |
|
|
6417 4533 MT 6417 4570 LS
|
2494 |
|
|
6456 4533 MT 6456 4570 LS
|
2495 |
|
|
6098 4506 MT 6098 4570 LS
|
2496 |
|
|
(220) 6098 4649 WT TS RSS
|
2497 |
|
|
% draw grid
|
2498 |
|
|
3710 300 MT 3710 4506 LS
|
2499 |
|
|
4108 300 MT 4108 4506 LS
|
2500 |
|
|
4506 300 MT 4506 4506 LS
|
2501 |
|
|
4904 300 MT 4904 4506 LS
|
2502 |
|
|
5302 300 MT 5302 4506 LS
|
2503 |
|
|
5700 300 MT 5700 4506 LS
|
2504 |
|
|
6098 300 MT 6098 4506 LS
|
2505 |
|
|
% draw waveforms
|
2506 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) 3275 409 WT TSE RSS
|
2507 |
|
|
3703 300 MT 3717 300 LS
|
2508 |
|
|
4101 300 MT 4115 300 LS
|
2509 |
|
|
4499 300 MT 4513 300 LS
|
2510 |
|
|
4897 300 MT 4911 300 LS
|
2511 |
|
|
5295 300 MT 5309 300 LS
|
2512 |
|
|
5693 300 MT 5707 300 LS
|
2513 |
|
|
6091 300 MT 6105 300 LS
|
2514 |
|
|
3312 410 MT 6297 410 LS
|
2515 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) 3275 553 WT TSE RSS
|
2516 |
|
|
3703 444 MT 3717 444 LS
|
2517 |
|
|
4101 444 MT 4115 444 LS
|
2518 |
|
|
4499 444 MT 4513 444 LS
|
2519 |
|
|
4897 444 MT 4911 444 LS
|
2520 |
|
|
5295 444 MT 5309 444 LS
|
2521 |
|
|
5693 444 MT 5707 444 LS
|
2522 |
|
|
6091 444 MT 6105 444 LS
|
2523 |
|
|
3312 554 MT 6297 554 LS
|
2524 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) 3275 697 WT TSE RSS
|
2525 |
|
|
3703 588 MT 3717 588 LS
|
2526 |
|
|
4101 588 MT 4115 588 LS
|
2527 |
|
|
4499 588 MT 4513 588 LS
|
2528 |
|
|
4897 588 MT 4911 588 LS
|
2529 |
|
|
5295 588 MT 5309 588 LS
|
2530 |
|
|
5693 588 MT 5707 588 LS
|
2531 |
|
|
6091 588 MT 6105 588 LS
|
2532 |
|
|
3312 698 MT 6297 698 LS
|
2533 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) 3275 841 WT TSE RSS
|
2534 |
|
|
3703 732 MT 3717 732 LS
|
2535 |
|
|
4101 732 MT 4115 732 LS
|
2536 |
|
|
4499 732 MT 4513 732 LS
|
2537 |
|
|
4897 732 MT 4911 732 LS
|
2538 |
|
|
5295 732 MT 5309 732 LS
|
2539 |
|
|
5693 732 MT 5707 732 LS
|
2540 |
|
|
6091 732 MT 6105 732 LS
|
2541 |
|
|
3312 842 MT 6297 842 LS
|
2542 |
|
|
% draw footer
|
2543 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 3 Page: 6) 300 4799 WT TSW RSS
|
2544 |
|
|
grestore
|
2545 |
|
|
showpage
|
2546 |
|
|
%%Page: 7 7
|
2547 |
|
|
gsave
|
2548 |
|
|
90 rotate 0.12 dup neg scale
|
2549 |
|
|
% dump string table
|
2550 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
2551 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
2552 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
2553 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
2554 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
2555 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
2556 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
2557 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
2558 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
2559 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
2560 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
2561 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
2562 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
2563 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
2564 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
2565 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
2566 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
2567 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
2568 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
2569 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
2570 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
2571 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
2572 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
2573 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
2574 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
2575 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
2576 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
2577 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
2578 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
2579 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
2580 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
2581 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
2582 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
2583 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
2584 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
2585 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
2586 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
2587 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
2588 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
2589 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
2590 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
2591 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
2592 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
2593 |
|
|
% draw waveform shading
|
2594 |
|
|
[] 0 SD
|
2595 |
|
|
2.995 setlinewidth
|
2596 |
|
|
|
2597 |
|
|
|
2598 |
|
|
|
2599 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
2600 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
2601 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
2602 |
|
|
3312 554 MT 3312 474 LS
|
2603 |
|
|
3312 474 MT 3511 474 LS
|
2604 |
|
|
3511 474 MT 3511 554 LS
|
2605 |
|
|
3511 554 MT 3710 554 LS
|
2606 |
|
|
3710 554 MT 3710 474 LS
|
2607 |
|
|
3710 474 MT 3909 474 LS
|
2608 |
|
|
3909 474 MT 3909 554 LS
|
2609 |
|
|
3909 554 MT 4108 554 LS
|
2610 |
|
|
4108 554 MT 4108 474 LS
|
2611 |
|
|
4108 474 MT 4307 474 LS
|
2612 |
|
|
4307 474 MT 4307 554 LS
|
2613 |
|
|
4307 554 MT 4506 554 LS
|
2614 |
|
|
4506 554 MT 4506 474 LS
|
2615 |
|
|
4506 474 MT 4705 474 LS
|
2616 |
|
|
4705 474 MT 4705 554 LS
|
2617 |
|
|
4705 554 MT 4904 554 LS
|
2618 |
|
|
4904 554 MT 4904 474 LS
|
2619 |
|
|
4904 474 MT 5103 474 LS
|
2620 |
|
|
5103 474 MT 5103 554 LS
|
2621 |
|
|
5103 554 MT 5302 554 LS
|
2622 |
|
|
5302 554 MT 5302 474 LS
|
2623 |
|
|
5302 474 MT 5501 474 LS
|
2624 |
|
|
5501 474 MT 5501 554 LS
|
2625 |
|
|
5501 554 MT 5700 554 LS
|
2626 |
|
|
5700 554 MT 5700 474 LS
|
2627 |
|
|
5700 474 MT 5899 474 LS
|
2628 |
|
|
5899 474 MT 5899 554 LS
|
2629 |
|
|
5899 554 MT 6098 554 LS
|
2630 |
|
|
6098 554 MT 6098 474 LS
|
2631 |
|
|
6098 474 MT 6297 474 LS
|
2632 |
|
|
3312 698 MT 6297 698 LS
|
2633 |
|
|
3312 842 MT 6297 842 LS
|
2634 |
|
|
3312 986 MT 6297 986 LS
|
2635 |
|
|
3312 1090 MT 6297 1090 LS
|
2636 |
|
|
3312 1234 MT 6297 1234 LS
|
2637 |
|
|
3312 1378 MT 6297 1378 LS
|
2638 |
|
|
3312 1522 MT 6297 1522 LS
|
2639 |
|
|
3312 1666 MT 6297 1666 LS
|
2640 |
|
|
3312 1810 MT 6297 1810 LS
|
2641 |
|
|
3312 1954 MT 6297 1954 LS
|
2642 |
|
|
3312 2098 MT 6297 2098 LS
|
2643 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
2644 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
2645 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
2646 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
2647 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
2648 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
2649 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
2650 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
2651 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
2652 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
2653 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
2654 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
2655 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
2656 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
2657 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
2658 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
2659 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
2660 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
2661 |
|
|
3312 3106 MT 6297 3106 LS
|
2662 |
|
|
3312 3250 MT 6297 3250 LS
|
2663 |
|
|
3312 3394 MT 6297 3394 LS
|
2664 |
|
|
3312 3538 MT 6297 3538 LS
|
2665 |
|
|
3312 3682 MT 6297 3682 LS
|
2666 |
|
|
3312 3826 MT 6297 3826 LS
|
2667 |
|
|
3312 3929 MT 3312 3929 LT 3703 3929 LT 3710 3970 LT ST
|
2668 |
|
|
3312 4010 MT 3312 4010 LT 3703 4010 LT 3710 3970 LT ST
|
2669 |
|
|
(3) 3326 3970 WT pop 0 originOffset 37 add RSS
|
2670 |
|
|
3710 3970 MT 3710 3970 LT 3717 3929 LT 4101 3929 LT 4108 3970 LT ST
|
2671 |
|
|
3710 3970 MT 3710 3970 LT 3717 4010 LT 4101 4010 LT 4108 3970 LT ST
|
2672 |
|
|
(4) 3724 3970 WT pop 0 originOffset 37 add RSS
|
2673 |
|
|
4108 3970 MT 4108 3970 LT 4115 3929 LT 4499 3929 LT 4506 3970 LT ST
|
2674 |
|
|
4108 3970 MT 4108 3970 LT 4115 4010 LT 4499 4010 LT 4506 3970 LT ST
|
2675 |
|
|
(5) 4122 3970 WT pop 0 originOffset 37 add RSS
|
2676 |
|
|
4506 3970 MT 4506 3970 LT 4513 3929 LT 4897 3929 LT 4904 3970 LT ST
|
2677 |
|
|
4506 3970 MT 4506 3970 LT 4513 4010 LT 4897 4010 LT 4904 3970 LT ST
|
2678 |
|
|
(6) 4520 3970 WT pop 0 originOffset 37 add RSS
|
2679 |
|
|
4904 3970 MT 4904 3970 LT 4911 3929 LT 5295 3929 LT 5302 3970 LT ST
|
2680 |
|
|
4904 3970 MT 4904 3970 LT 4911 4010 LT 5295 4010 LT 5302 3970 LT ST
|
2681 |
|
|
(7) 4918 3970 WT pop 0 originOffset 37 add RSS
|
2682 |
|
|
5302 3970 MT 5302 3970 LT 5309 3929 LT 5693 3929 LT 5700 3970 LT ST
|
2683 |
|
|
5302 3970 MT 5302 3970 LT 5309 4010 LT 5693 4010 LT 5700 3970 LT ST
|
2684 |
|
|
(0) 5316 3970 WT pop 0 originOffset 37 add RSS
|
2685 |
|
|
5700 3970 MT 5700 3970 LT 5707 3929 LT 6091 3929 LT 6098 3970 LT ST
|
2686 |
|
|
5700 3970 MT 5700 3970 LT 5707 4010 LT 6091 4010 LT 6098 3970 LT ST
|
2687 |
|
|
(1) 5714 3970 WT pop 0 originOffset 37 add RSS
|
2688 |
|
|
6098 3970 MT 6098 3970 LT 6105 3929 LT 6297 3929 LT ST
|
2689 |
|
|
6098 3970 MT 6098 3970 LT 6105 4010 LT 6297 4010 LT ST
|
2690 |
|
|
(2) 6112 3970 WT pop 0 originOffset 37 add RSS
|
2691 |
|
|
3312 4073 MT 3312 4073 LT 3703 4073 LT 3710 4114 LT ST
|
2692 |
|
|
3312 4154 MT 3312 4154 LT 3703 4154 LT 3710 4114 LT ST
|
2693 |
|
|
(3) 3326 4114 WT pop 0 originOffset 37 add RSS
|
2694 |
|
|
3710 4114 MT 3710 4114 LT 3717 4073 LT 4101 4073 LT 4108 4114 LT ST
|
2695 |
|
|
3710 4114 MT 3710 4114 LT 3717 4154 LT 4101 4154 LT 4108 4114 LT ST
|
2696 |
|
|
(4) 3724 4114 WT pop 0 originOffset 37 add RSS
|
2697 |
|
|
4108 4114 MT 4108 4114 LT 4115 4073 LT 4499 4073 LT 4506 4114 LT ST
|
2698 |
|
|
4108 4114 MT 4108 4114 LT 4115 4154 LT 4499 4154 LT 4506 4114 LT ST
|
2699 |
|
|
(5) 4122 4114 WT pop 0 originOffset 37 add RSS
|
2700 |
|
|
4506 4114 MT 4506 4114 LT 4513 4073 LT 4897 4073 LT 4904 4114 LT ST
|
2701 |
|
|
4506 4114 MT 4506 4114 LT 4513 4154 LT 4897 4154 LT 4904 4114 LT ST
|
2702 |
|
|
(6) 4520 4114 WT pop 0 originOffset 37 add RSS
|
2703 |
|
|
4904 4114 MT 4904 4114 LT 4911 4073 LT 5295 4073 LT 5302 4114 LT ST
|
2704 |
|
|
4904 4114 MT 4904 4114 LT 4911 4154 LT 5295 4154 LT 5302 4114 LT ST
|
2705 |
|
|
(7) 4918 4114 WT pop 0 originOffset 37 add RSS
|
2706 |
|
|
5302 4114 MT 5302 4114 LT 5309 4073 LT 5693 4073 LT 5700 4114 LT ST
|
2707 |
|
|
5302 4114 MT 5302 4114 LT 5309 4154 LT 5693 4154 LT 5700 4114 LT ST
|
2708 |
|
|
(0) 5316 4114 WT pop 0 originOffset 37 add RSS
|
2709 |
|
|
5700 4114 MT 5700 4114 LT 5707 4073 LT 6091 4073 LT 6098 4114 LT ST
|
2710 |
|
|
5700 4114 MT 5700 4114 LT 5707 4154 LT 6091 4154 LT 6098 4114 LT ST
|
2711 |
|
|
(1) 5714 4114 WT pop 0 originOffset 37 add RSS
|
2712 |
|
|
6098 4114 MT 6098 4114 LT 6105 4073 LT 6297 4073 LT ST
|
2713 |
|
|
6098 4114 MT 6098 4114 LT 6105 4154 LT 6297 4154 LT ST
|
2714 |
|
|
(2) 6112 4114 WT pop 0 originOffset 37 add RSS
|
2715 |
|
|
3312 4258 MT 6297 4258 LS
|
2716 |
|
|
3312 4402 MT 6297 4402 LS
|
2717 |
|
|
% draw timeline
|
2718 |
|
|
3351 4533 MT 3351 4570 LS
|
2719 |
|
|
3391 4533 MT 3391 4570 LS
|
2720 |
|
|
3431 4533 MT 3431 4570 LS
|
2721 |
|
|
3470 4533 MT 3470 4570 LS
|
2722 |
|
|
3551 4533 MT 3551 4570 LS
|
2723 |
|
|
3591 4533 MT 3591 4570 LS
|
2724 |
|
|
3630 4533 MT 3630 4570 LS
|
2725 |
|
|
3670 4533 MT 3670 4570 LS
|
2726 |
|
|
3710 4533 MT 3710 4570 LS
|
2727 |
|
|
3750 4533 MT 3750 4570 LS
|
2728 |
|
|
3790 4533 MT 3790 4570 LS
|
2729 |
|
|
3830 4533 MT 3830 4570 LS
|
2730 |
|
|
3869 4533 MT 3869 4570 LS
|
2731 |
|
|
3511 4506 MT 3511 4570 LS
|
2732 |
|
|
3949 4533 MT 3949 4570 LS
|
2733 |
|
|
3989 4533 MT 3989 4570 LS
|
2734 |
|
|
4028 4533 MT 4028 4570 LS
|
2735 |
|
|
4068 4533 MT 4068 4570 LS
|
2736 |
|
|
4108 4533 MT 4108 4570 LS
|
2737 |
|
|
4148 4533 MT 4148 4570 LS
|
2738 |
|
|
4188 4533 MT 4188 4570 LS
|
2739 |
|
|
4228 4533 MT 4228 4570 LS
|
2740 |
|
|
4267 4533 MT 4267 4570 LS
|
2741 |
|
|
3909 4506 MT 3909 4570 LS
|
2742 |
|
|
(240) 3909 4649 WT TS RSS
|
2743 |
|
|
4347 4533 MT 4347 4570 LS
|
2744 |
|
|
4387 4533 MT 4387 4570 LS
|
2745 |
|
|
4426 4533 MT 4426 4570 LS
|
2746 |
|
|
4466 4533 MT 4466 4570 LS
|
2747 |
|
|
4506 4533 MT 4506 4570 LS
|
2748 |
|
|
4546 4533 MT 4546 4570 LS
|
2749 |
|
|
4586 4533 MT 4586 4570 LS
|
2750 |
|
|
4626 4533 MT 4626 4570 LS
|
2751 |
|
|
4665 4533 MT 4665 4570 LS
|
2752 |
|
|
4307 4506 MT 4307 4570 LS
|
2753 |
|
|
4745 4533 MT 4745 4570 LS
|
2754 |
|
|
4785 4533 MT 4785 4570 LS
|
2755 |
|
|
4824 4533 MT 4824 4570 LS
|
2756 |
|
|
4864 4533 MT 4864 4570 LS
|
2757 |
|
|
4904 4533 MT 4904 4570 LS
|
2758 |
|
|
4944 4533 MT 4944 4570 LS
|
2759 |
|
|
4984 4533 MT 4984 4570 LS
|
2760 |
|
|
5024 4533 MT 5024 4570 LS
|
2761 |
|
|
5063 4533 MT 5063 4570 LS
|
2762 |
|
|
4705 4506 MT 4705 4570 LS
|
2763 |
|
|
(260) 4705 4649 WT TS RSS
|
2764 |
|
|
5143 4533 MT 5143 4570 LS
|
2765 |
|
|
5183 4533 MT 5183 4570 LS
|
2766 |
|
|
5222 4533 MT 5222 4570 LS
|
2767 |
|
|
5262 4533 MT 5262 4570 LS
|
2768 |
|
|
5302 4533 MT 5302 4570 LS
|
2769 |
|
|
5342 4533 MT 5342 4570 LS
|
2770 |
|
|
5382 4533 MT 5382 4570 LS
|
2771 |
|
|
5422 4533 MT 5422 4570 LS
|
2772 |
|
|
5461 4533 MT 5461 4570 LS
|
2773 |
|
|
5103 4506 MT 5103 4570 LS
|
2774 |
|
|
5541 4533 MT 5541 4570 LS
|
2775 |
|
|
5581 4533 MT 5581 4570 LS
|
2776 |
|
|
5620 4533 MT 5620 4570 LS
|
2777 |
|
|
5660 4533 MT 5660 4570 LS
|
2778 |
|
|
5700 4533 MT 5700 4570 LS
|
2779 |
|
|
5740 4533 MT 5740 4570 LS
|
2780 |
|
|
5780 4533 MT 5780 4570 LS
|
2781 |
|
|
5820 4533 MT 5820 4570 LS
|
2782 |
|
|
5859 4533 MT 5859 4570 LS
|
2783 |
|
|
5501 4506 MT 5501 4570 LS
|
2784 |
|
|
(280) 5501 4649 WT TS RSS
|
2785 |
|
|
5939 4533 MT 5939 4570 LS
|
2786 |
|
|
5979 4533 MT 5979 4570 LS
|
2787 |
|
|
6018 4533 MT 6018 4570 LS
|
2788 |
|
|
6058 4533 MT 6058 4570 LS
|
2789 |
|
|
6098 4533 MT 6098 4570 LS
|
2790 |
|
|
6138 4533 MT 6138 4570 LS
|
2791 |
|
|
6178 4533 MT 6178 4570 LS
|
2792 |
|
|
6218 4533 MT 6218 4570 LS
|
2793 |
|
|
6257 4533 MT 6257 4570 LS
|
2794 |
|
|
5899 4506 MT 5899 4570 LS
|
2795 |
|
|
6337 4533 MT 6337 4570 LS
|
2796 |
|
|
6377 4533 MT 6377 4570 LS
|
2797 |
|
|
6416 4533 MT 6416 4570 LS
|
2798 |
|
|
6456 4533 MT 6456 4570 LS
|
2799 |
|
|
6496 4533 MT 6496 4570 LS
|
2800 |
|
|
6536 4533 MT 6536 4570 LS
|
2801 |
|
|
6576 4533 MT 6576 4570 LS
|
2802 |
|
|
6616 4533 MT 6616 4570 LS
|
2803 |
|
|
6655 4533 MT 6655 4570 LS
|
2804 |
|
|
6297 4506 MT 6297 4570 LS
|
2805 |
|
|
(300) 6297 4649 WT TS RSS
|
2806 |
|
|
% draw grid
|
2807 |
|
|
3511 300 MT 3511 4506 LS
|
2808 |
|
|
3909 300 MT 3909 4506 LS
|
2809 |
|
|
4307 300 MT 4307 4506 LS
|
2810 |
|
|
4705 300 MT 4705 4506 LS
|
2811 |
|
|
5103 300 MT 5103 4506 LS
|
2812 |
|
|
5501 300 MT 5501 4506 LS
|
2813 |
|
|
5899 300 MT 5899 4506 LS
|
2814 |
|
|
6297 300 MT 6297 4506 LS
|
2815 |
|
|
% draw waveforms
|
2816 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) 3275 409 WT TSE RSS
|
2817 |
|
|
3504 300 MT 3518 300 LS
|
2818 |
|
|
3902 300 MT 3916 300 LS
|
2819 |
|
|
4300 300 MT 4314 300 LS
|
2820 |
|
|
4698 300 MT 4712 300 LS
|
2821 |
|
|
5096 300 MT 5110 300 LS
|
2822 |
|
|
5494 300 MT 5508 300 LS
|
2823 |
|
|
5892 300 MT 5906 300 LS
|
2824 |
|
|
6290 300 MT 6304 300 LS
|
2825 |
|
|
3312 329 MT 3312 329 LT 6297 329 LT ST
|
2826 |
|
|
3312 410 MT 3312 410 LT 6297 410 LT ST
|
2827 |
|
|
(00000020) 3326 370 WT pop 0 originOffset 37 add RSS
|
2828 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) 3275 553 WT TSE RSS
|
2829 |
|
|
3504 444 MT 3518 444 LS
|
2830 |
|
|
3902 444 MT 3916 444 LS
|
2831 |
|
|
4300 444 MT 4314 444 LS
|
2832 |
|
|
4698 444 MT 4712 444 LS
|
2833 |
|
|
5096 444 MT 5110 444 LS
|
2834 |
|
|
5494 444 MT 5508 444 LS
|
2835 |
|
|
5892 444 MT 5906 444 LS
|
2836 |
|
|
6290 444 MT 6304 444 LS
|
2837 |
|
|
3312 554 MT 3312 474 LS
|
2838 |
|
|
3312 474 MT 3511 474 LS
|
2839 |
|
|
3511 474 MT 3511 554 LS
|
2840 |
|
|
3511 554 MT 3710 554 LS
|
2841 |
|
|
3710 554 MT 3710 474 LS
|
2842 |
|
|
3710 474 MT 3909 474 LS
|
2843 |
|
|
3909 474 MT 3909 554 LS
|
2844 |
|
|
3909 554 MT 4108 554 LS
|
2845 |
|
|
4108 554 MT 4108 474 LS
|
2846 |
|
|
4108 474 MT 4307 474 LS
|
2847 |
|
|
4307 474 MT 4307 554 LS
|
2848 |
|
|
4307 554 MT 4506 554 LS
|
2849 |
|
|
4506 554 MT 4506 474 LS
|
2850 |
|
|
4506 474 MT 4705 474 LS
|
2851 |
|
|
4705 474 MT 4705 554 LS
|
2852 |
|
|
4705 554 MT 4904 554 LS
|
2853 |
|
|
4904 554 MT 4904 474 LS
|
2854 |
|
|
4904 474 MT 5103 474 LS
|
2855 |
|
|
5103 474 MT 5103 554 LS
|
2856 |
|
|
5103 554 MT 5302 554 LS
|
2857 |
|
|
5302 554 MT 5302 474 LS
|
2858 |
|
|
5302 474 MT 5501 474 LS
|
2859 |
|
|
5501 474 MT 5501 554 LS
|
2860 |
|
|
5501 554 MT 5700 554 LS
|
2861 |
|
|
5700 554 MT 5700 474 LS
|
2862 |
|
|
5700 474 MT 5899 474 LS
|
2863 |
|
|
5899 474 MT 5899 554 LS
|
2864 |
|
|
5899 554 MT 6098 554 LS
|
2865 |
|
|
6098 554 MT 6098 474 LS
|
2866 |
|
|
6098 474 MT 6297 474 LS
|
2867 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) 3275 697 WT TSE RSS
|
2868 |
|
|
3504 588 MT 3518 588 LS
|
2869 |
|
|
3902 588 MT 3916 588 LS
|
2870 |
|
|
4300 588 MT 4314 588 LS
|
2871 |
|
|
4698 588 MT 4712 588 LS
|
2872 |
|
|
5096 588 MT 5110 588 LS
|
2873 |
|
|
5494 588 MT 5508 588 LS
|
2874 |
|
|
5892 588 MT 5906 588 LS
|
2875 |
|
|
6290 588 MT 6304 588 LS
|
2876 |
|
|
3312 698 MT 6297 698 LS
|
2877 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) 3275 841 WT TSE RSS
|
2878 |
|
|
3504 732 MT 3518 732 LS
|
2879 |
|
|
3902 732 MT 3916 732 LS
|
2880 |
|
|
4300 732 MT 4314 732 LS
|
2881 |
|
|
4698 732 MT 4712 732 LS
|
2882 |
|
|
5096 732 MT 5110 732 LS
|
2883 |
|
|
5494 732 MT 5508 732 LS
|
2884 |
|
|
5892 732 MT 5906 732 LS
|
2885 |
|
|
6290 732 MT 6304 732 LS
|
2886 |
|
|
3312 842 MT 6297 842 LS
|
2887 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) 3275 985 WT TSE RSS
|
2888 |
|
|
3504 876 MT 3518 876 LS
|
2889 |
|
|
3902 876 MT 3916 876 LS
|
2890 |
|
|
4300 876 MT 4314 876 LS
|
2891 |
|
|
4698 876 MT 4712 876 LS
|
2892 |
|
|
5096 876 MT 5110 876 LS
|
2893 |
|
|
5494 876 MT 5508 876 LS
|
2894 |
|
|
5892 876 MT 5906 876 LS
|
2895 |
|
|
6290 876 MT 6304 876 LS
|
2896 |
|
|
3312 986 MT 6297 986 LS
|
2897 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) 3275 1129 WT TSE RSS
|
2898 |
|
|
3504 1020 MT 3518 1020 LS
|
2899 |
|
|
3902 1020 MT 3916 1020 LS
|
2900 |
|
|
4300 1020 MT 4314 1020 LS
|
2901 |
|
|
4698 1020 MT 4712 1020 LS
|
2902 |
|
|
5096 1020 MT 5110 1020 LS
|
2903 |
|
|
5494 1020 MT 5508 1020 LS
|
2904 |
|
|
5892 1020 MT 5906 1020 LS
|
2905 |
|
|
6290 1020 MT 6304 1020 LS
|
2906 |
|
|
3312 1090 MT 6297 1090 LS
|
2907 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) 3275 1273 WT TSE RSS
|
2908 |
|
|
3504 1164 MT 3518 1164 LS
|
2909 |
|
|
3902 1164 MT 3916 1164 LS
|
2910 |
|
|
4300 1164 MT 4314 1164 LS
|
2911 |
|
|
4698 1164 MT 4712 1164 LS
|
2912 |
|
|
5096 1164 MT 5110 1164 LS
|
2913 |
|
|
5494 1164 MT 5508 1164 LS
|
2914 |
|
|
5892 1164 MT 5906 1164 LS
|
2915 |
|
|
6290 1164 MT 6304 1164 LS
|
2916 |
|
|
3312 1234 MT 6297 1234 LS
|
2917 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) 3275 1417 WT TSE RSS
|
2918 |
|
|
3504 1308 MT 3518 1308 LS
|
2919 |
|
|
3902 1308 MT 3916 1308 LS
|
2920 |
|
|
4300 1308 MT 4314 1308 LS
|
2921 |
|
|
4698 1308 MT 4712 1308 LS
|
2922 |
|
|
5096 1308 MT 5110 1308 LS
|
2923 |
|
|
5494 1308 MT 5508 1308 LS
|
2924 |
|
|
5892 1308 MT 5906 1308 LS
|
2925 |
|
|
6290 1308 MT 6304 1308 LS
|
2926 |
|
|
3312 1378 MT 6297 1378 LS
|
2927 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) 3275 1561 WT TSE RSS
|
2928 |
|
|
3504 1452 MT 3518 1452 LS
|
2929 |
|
|
3902 1452 MT 3916 1452 LS
|
2930 |
|
|
4300 1452 MT 4314 1452 LS
|
2931 |
|
|
4698 1452 MT 4712 1452 LS
|
2932 |
|
|
5096 1452 MT 5110 1452 LS
|
2933 |
|
|
5494 1452 MT 5508 1452 LS
|
2934 |
|
|
5892 1452 MT 5906 1452 LS
|
2935 |
|
|
6290 1452 MT 6304 1452 LS
|
2936 |
|
|
3312 1522 MT 6297 1522 LS
|
2937 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) 3275 1705 WT TSE RSS
|
2938 |
|
|
3504 1596 MT 3518 1596 LS
|
2939 |
|
|
3902 1596 MT 3916 1596 LS
|
2940 |
|
|
4300 1596 MT 4314 1596 LS
|
2941 |
|
|
4698 1596 MT 4712 1596 LS
|
2942 |
|
|
5096 1596 MT 5110 1596 LS
|
2943 |
|
|
5494 1596 MT 5508 1596 LS
|
2944 |
|
|
5892 1596 MT 5906 1596 LS
|
2945 |
|
|
6290 1596 MT 6304 1596 LS
|
2946 |
|
|
3312 1666 MT 6297 1666 LS
|
2947 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) 3275 1849 WT TSE RSS
|
2948 |
|
|
3504 1740 MT 3518 1740 LS
|
2949 |
|
|
3902 1740 MT 3916 1740 LS
|
2950 |
|
|
4300 1740 MT 4314 1740 LS
|
2951 |
|
|
4698 1740 MT 4712 1740 LS
|
2952 |
|
|
5096 1740 MT 5110 1740 LS
|
2953 |
|
|
5494 1740 MT 5508 1740 LS
|
2954 |
|
|
5892 1740 MT 5906 1740 LS
|
2955 |
|
|
6290 1740 MT 6304 1740 LS
|
2956 |
|
|
3312 1810 MT 6297 1810 LS
|
2957 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) 3275 1993 WT TSE RSS
|
2958 |
|
|
3504 1884 MT 3518 1884 LS
|
2959 |
|
|
3902 1884 MT 3916 1884 LS
|
2960 |
|
|
4300 1884 MT 4314 1884 LS
|
2961 |
|
|
4698 1884 MT 4712 1884 LS
|
2962 |
|
|
5096 1884 MT 5110 1884 LS
|
2963 |
|
|
5494 1884 MT 5508 1884 LS
|
2964 |
|
|
5892 1884 MT 5906 1884 LS
|
2965 |
|
|
6290 1884 MT 6304 1884 LS
|
2966 |
|
|
3312 1954 MT 6297 1954 LS
|
2967 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) 3275 2137 WT TSE RSS
|
2968 |
|
|
3504 2028 MT 3518 2028 LS
|
2969 |
|
|
3902 2028 MT 3916 2028 LS
|
2970 |
|
|
4300 2028 MT 4314 2028 LS
|
2971 |
|
|
4698 2028 MT 4712 2028 LS
|
2972 |
|
|
5096 2028 MT 5110 2028 LS
|
2973 |
|
|
5494 2028 MT 5508 2028 LS
|
2974 |
|
|
5892 2028 MT 5906 2028 LS
|
2975 |
|
|
6290 2028 MT 6304 2028 LS
|
2976 |
|
|
3312 2098 MT 6297 2098 LS
|
2977 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) 3275 2281 WT TSE RSS
|
2978 |
|
|
3504 2172 MT 3518 2172 LS
|
2979 |
|
|
3902 2172 MT 3916 2172 LS
|
2980 |
|
|
4300 2172 MT 4314 2172 LS
|
2981 |
|
|
4698 2172 MT 4712 2172 LS
|
2982 |
|
|
5096 2172 MT 5110 2172 LS
|
2983 |
|
|
5494 2172 MT 5508 2172 LS
|
2984 |
|
|
5892 2172 MT 5906 2172 LS
|
2985 |
|
|
6290 2172 MT 6304 2172 LS
|
2986 |
|
|
3312 2201 MT 3312 2201 LT 6297 2201 LT ST
|
2987 |
|
|
3312 2282 MT 3312 2282 LT 6297 2282 LT ST
|
2988 |
|
|
(00000000) 3326 2242 WT pop 0 originOffset 37 add RSS
|
2989 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) 3275 2425 WT TSE RSS
|
2990 |
|
|
3504 2316 MT 3518 2316 LS
|
2991 |
|
|
3902 2316 MT 3916 2316 LS
|
2992 |
|
|
4300 2316 MT 4314 2316 LS
|
2993 |
|
|
4698 2316 MT 4712 2316 LS
|
2994 |
|
|
5096 2316 MT 5110 2316 LS
|
2995 |
|
|
5494 2316 MT 5508 2316 LS
|
2996 |
|
|
5892 2316 MT 5906 2316 LS
|
2997 |
|
|
6290 2316 MT 6304 2316 LS
|
2998 |
|
|
3312 2345 MT 3312 2345 LT 6297 2345 LT ST
|
2999 |
|
|
3312 2426 MT 3312 2426 LT 6297 2426 LT ST
|
3000 |
|
|
(00000000) 3326 2386 WT pop 0 originOffset 37 add RSS
|
3001 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) 3275 2569 WT TSE RSS
|
3002 |
|
|
3504 2460 MT 3518 2460 LS
|
3003 |
|
|
3902 2460 MT 3916 2460 LS
|
3004 |
|
|
4300 2460 MT 4314 2460 LS
|
3005 |
|
|
4698 2460 MT 4712 2460 LS
|
3006 |
|
|
5096 2460 MT 5110 2460 LS
|
3007 |
|
|
5494 2460 MT 5508 2460 LS
|
3008 |
|
|
5892 2460 MT 5906 2460 LS
|
3009 |
|
|
6290 2460 MT 6304 2460 LS
|
3010 |
|
|
3312 2489 MT 3312 2489 LT 6297 2489 LT ST
|
3011 |
|
|
3312 2570 MT 3312 2570 LT 6297 2570 LT ST
|
3012 |
|
|
(0) 3326 2530 WT pop 0 originOffset 37 add RSS
|
3013 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) 3275 2713 WT TSE RSS
|
3014 |
|
|
3504 2604 MT 3518 2604 LS
|
3015 |
|
|
3902 2604 MT 3916 2604 LS
|
3016 |
|
|
4300 2604 MT 4314 2604 LS
|
3017 |
|
|
4698 2604 MT 4712 2604 LS
|
3018 |
|
|
5096 2604 MT 5110 2604 LS
|
3019 |
|
|
5494 2604 MT 5508 2604 LS
|
3020 |
|
|
5892 2604 MT 5906 2604 LS
|
3021 |
|
|
6290 2604 MT 6304 2604 LS
|
3022 |
|
|
3312 2633 MT 3312 2633 LT 6297 2633 LT ST
|
3023 |
|
|
3312 2714 MT 3312 2714 LT 6297 2714 LT ST
|
3024 |
|
|
(0) 3326 2674 WT pop 0 originOffset 37 add RSS
|
3025 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) 3275 2857 WT TSE RSS
|
3026 |
|
|
3504 2748 MT 3518 2748 LS
|
3027 |
|
|
3902 2748 MT 3916 2748 LS
|
3028 |
|
|
4300 2748 MT 4314 2748 LS
|
3029 |
|
|
4698 2748 MT 4712 2748 LS
|
3030 |
|
|
5096 2748 MT 5110 2748 LS
|
3031 |
|
|
5494 2748 MT 5508 2748 LS
|
3032 |
|
|
5892 2748 MT 5906 2748 LS
|
3033 |
|
|
6290 2748 MT 6304 2748 LS
|
3034 |
|
|
3312 2777 MT 3312 2777 LT 6297 2777 LT ST
|
3035 |
|
|
3312 2858 MT 3312 2858 LT 6297 2858 LT ST
|
3036 |
|
|
(0) 3326 2818 WT pop 0 originOffset 37 add RSS
|
3037 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) 3275 3001 WT TSE RSS
|
3038 |
|
|
3504 2892 MT 3518 2892 LS
|
3039 |
|
|
3902 2892 MT 3916 2892 LS
|
3040 |
|
|
4300 2892 MT 4314 2892 LS
|
3041 |
|
|
4698 2892 MT 4712 2892 LS
|
3042 |
|
|
5096 2892 MT 5110 2892 LS
|
3043 |
|
|
5494 2892 MT 5508 2892 LS
|
3044 |
|
|
5892 2892 MT 5906 2892 LS
|
3045 |
|
|
6290 2892 MT 6304 2892 LS
|
3046 |
|
|
3312 2921 MT 3312 2921 LT 6297 2921 LT ST
|
3047 |
|
|
3312 3002 MT 3312 3002 LT 6297 3002 LT ST
|
3048 |
|
|
(0) 3326 2962 WT pop 0 originOffset 37 add RSS
|
3049 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) 3275 3145 WT TSE RSS
|
3050 |
|
|
3504 3036 MT 3518 3036 LS
|
3051 |
|
|
3902 3036 MT 3916 3036 LS
|
3052 |
|
|
4300 3036 MT 4314 3036 LS
|
3053 |
|
|
4698 3036 MT 4712 3036 LS
|
3054 |
|
|
5096 3036 MT 5110 3036 LS
|
3055 |
|
|
5494 3036 MT 5508 3036 LS
|
3056 |
|
|
5892 3036 MT 5906 3036 LS
|
3057 |
|
|
6290 3036 MT 6304 3036 LS
|
3058 |
|
|
3312 3106 MT 6297 3106 LS
|
3059 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) 3275 3289 WT TSE RSS
|
3060 |
|
|
3504 3180 MT 3518 3180 LS
|
3061 |
|
|
3902 3180 MT 3916 3180 LS
|
3062 |
|
|
4300 3180 MT 4314 3180 LS
|
3063 |
|
|
4698 3180 MT 4712 3180 LS
|
3064 |
|
|
5096 3180 MT 5110 3180 LS
|
3065 |
|
|
5494 3180 MT 5508 3180 LS
|
3066 |
|
|
5892 3180 MT 5906 3180 LS
|
3067 |
|
|
6290 3180 MT 6304 3180 LS
|
3068 |
|
|
3312 3250 MT 6297 3250 LS
|
3069 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) 3275 3433 WT TSE RSS
|
3070 |
|
|
3504 3324 MT 3518 3324 LS
|
3071 |
|
|
3902 3324 MT 3916 3324 LS
|
3072 |
|
|
4300 3324 MT 4314 3324 LS
|
3073 |
|
|
4698 3324 MT 4712 3324 LS
|
3074 |
|
|
5096 3324 MT 5110 3324 LS
|
3075 |
|
|
5494 3324 MT 5508 3324 LS
|
3076 |
|
|
5892 3324 MT 5906 3324 LS
|
3077 |
|
|
6290 3324 MT 6304 3324 LS
|
3078 |
|
|
3312 3394 MT 6297 3394 LS
|
3079 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) 3275 3577 WT TSE RSS
|
3080 |
|
|
3504 3468 MT 3518 3468 LS
|
3081 |
|
|
3902 3468 MT 3916 3468 LS
|
3082 |
|
|
4300 3468 MT 4314 3468 LS
|
3083 |
|
|
4698 3468 MT 4712 3468 LS
|
3084 |
|
|
5096 3468 MT 5110 3468 LS
|
3085 |
|
|
5494 3468 MT 5508 3468 LS
|
3086 |
|
|
5892 3468 MT 5906 3468 LS
|
3087 |
|
|
6290 3468 MT 6304 3468 LS
|
3088 |
|
|
3312 3538 MT 6297 3538 LS
|
3089 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) 3275 3721 WT TSE RSS
|
3090 |
|
|
3504 3612 MT 3518 3612 LS
|
3091 |
|
|
3902 3612 MT 3916 3612 LS
|
3092 |
|
|
4300 3612 MT 4314 3612 LS
|
3093 |
|
|
4698 3612 MT 4712 3612 LS
|
3094 |
|
|
5096 3612 MT 5110 3612 LS
|
3095 |
|
|
5494 3612 MT 5508 3612 LS
|
3096 |
|
|
5892 3612 MT 5906 3612 LS
|
3097 |
|
|
6290 3612 MT 6304 3612 LS
|
3098 |
|
|
3312 3682 MT 6297 3682 LS
|
3099 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) 3275 3865 WT TSE RSS
|
3100 |
|
|
3504 3756 MT 3518 3756 LS
|
3101 |
|
|
3902 3756 MT 3916 3756 LS
|
3102 |
|
|
4300 3756 MT 4314 3756 LS
|
3103 |
|
|
4698 3756 MT 4712 3756 LS
|
3104 |
|
|
5096 3756 MT 5110 3756 LS
|
3105 |
|
|
5494 3756 MT 5508 3756 LS
|
3106 |
|
|
5892 3756 MT 5906 3756 LS
|
3107 |
|
|
6290 3756 MT 6304 3756 LS
|
3108 |
|
|
3312 3826 MT 6297 3826 LS
|
3109 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) 3275 4009 WT TSE RSS
|
3110 |
|
|
3504 3900 MT 3518 3900 LS
|
3111 |
|
|
3902 3900 MT 3916 3900 LS
|
3112 |
|
|
4300 3900 MT 4314 3900 LS
|
3113 |
|
|
4698 3900 MT 4712 3900 LS
|
3114 |
|
|
5096 3900 MT 5110 3900 LS
|
3115 |
|
|
5494 3900 MT 5508 3900 LS
|
3116 |
|
|
5892 3900 MT 5906 3900 LS
|
3117 |
|
|
6290 3900 MT 6304 3900 LS
|
3118 |
|
|
3312 3929 MT 3312 3929 LT 3703 3929 LT 3710 3970 LT ST
|
3119 |
|
|
3312 4010 MT 3312 4010 LT 3703 4010 LT 3710 3970 LT ST
|
3120 |
|
|
(3) 3326 3970 WT pop 0 originOffset 37 add RSS
|
3121 |
|
|
3710 3970 MT 3710 3970 LT 3717 3929 LT 4101 3929 LT 4108 3970 LT ST
|
3122 |
|
|
3710 3970 MT 3710 3970 LT 3717 4010 LT 4101 4010 LT 4108 3970 LT ST
|
3123 |
|
|
(4) 3724 3970 WT pop 0 originOffset 37 add RSS
|
3124 |
|
|
4108 3970 MT 4108 3970 LT 4115 3929 LT 4499 3929 LT 4506 3970 LT ST
|
3125 |
|
|
4108 3970 MT 4108 3970 LT 4115 4010 LT 4499 4010 LT 4506 3970 LT ST
|
3126 |
|
|
(5) 4122 3970 WT pop 0 originOffset 37 add RSS
|
3127 |
|
|
4506 3970 MT 4506 3970 LT 4513 3929 LT 4897 3929 LT 4904 3970 LT ST
|
3128 |
|
|
4506 3970 MT 4506 3970 LT 4513 4010 LT 4897 4010 LT 4904 3970 LT ST
|
3129 |
|
|
(6) 4520 3970 WT pop 0 originOffset 37 add RSS
|
3130 |
|
|
4904 3970 MT 4904 3970 LT 4911 3929 LT 5295 3929 LT 5302 3970 LT ST
|
3131 |
|
|
4904 3970 MT 4904 3970 LT 4911 4010 LT 5295 4010 LT 5302 3970 LT ST
|
3132 |
|
|
(7) 4918 3970 WT pop 0 originOffset 37 add RSS
|
3133 |
|
|
5302 3970 MT 5302 3970 LT 5309 3929 LT 5693 3929 LT 5700 3970 LT ST
|
3134 |
|
|
5302 3970 MT 5302 3970 LT 5309 4010 LT 5693 4010 LT 5700 3970 LT ST
|
3135 |
|
|
(0) 5316 3970 WT pop 0 originOffset 37 add RSS
|
3136 |
|
|
5700 3970 MT 5700 3970 LT 5707 3929 LT 6091 3929 LT 6098 3970 LT ST
|
3137 |
|
|
5700 3970 MT 5700 3970 LT 5707 4010 LT 6091 4010 LT 6098 3970 LT ST
|
3138 |
|
|
(1) 5714 3970 WT pop 0 originOffset 37 add RSS
|
3139 |
|
|
6098 3970 MT 6098 3970 LT 6105 3929 LT 6297 3929 LT ST
|
3140 |
|
|
6098 3970 MT 6098 3970 LT 6105 4010 LT 6297 4010 LT ST
|
3141 |
|
|
(2) 6112 3970 WT pop 0 originOffset 37 add RSS
|
3142 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) 3275 4153 WT TSE RSS
|
3143 |
|
|
3504 4044 MT 3518 4044 LS
|
3144 |
|
|
3902 4044 MT 3916 4044 LS
|
3145 |
|
|
4300 4044 MT 4314 4044 LS
|
3146 |
|
|
4698 4044 MT 4712 4044 LS
|
3147 |
|
|
5096 4044 MT 5110 4044 LS
|
3148 |
|
|
5494 4044 MT 5508 4044 LS
|
3149 |
|
|
5892 4044 MT 5906 4044 LS
|
3150 |
|
|
6290 4044 MT 6304 4044 LS
|
3151 |
|
|
3312 4073 MT 3312 4073 LT 3703 4073 LT 3710 4114 LT ST
|
3152 |
|
|
3312 4154 MT 3312 4154 LT 3703 4154 LT 3710 4114 LT ST
|
3153 |
|
|
(3) 3326 4114 WT pop 0 originOffset 37 add RSS
|
3154 |
|
|
3710 4114 MT 3710 4114 LT 3717 4073 LT 4101 4073 LT 4108 4114 LT ST
|
3155 |
|
|
3710 4114 MT 3710 4114 LT 3717 4154 LT 4101 4154 LT 4108 4114 LT ST
|
3156 |
|
|
(4) 3724 4114 WT pop 0 originOffset 37 add RSS
|
3157 |
|
|
4108 4114 MT 4108 4114 LT 4115 4073 LT 4499 4073 LT 4506 4114 LT ST
|
3158 |
|
|
4108 4114 MT 4108 4114 LT 4115 4154 LT 4499 4154 LT 4506 4114 LT ST
|
3159 |
|
|
(5) 4122 4114 WT pop 0 originOffset 37 add RSS
|
3160 |
|
|
4506 4114 MT 4506 4114 LT 4513 4073 LT 4897 4073 LT 4904 4114 LT ST
|
3161 |
|
|
4506 4114 MT 4506 4114 LT 4513 4154 LT 4897 4154 LT 4904 4114 LT ST
|
3162 |
|
|
(6) 4520 4114 WT pop 0 originOffset 37 add RSS
|
3163 |
|
|
4904 4114 MT 4904 4114 LT 4911 4073 LT 5295 4073 LT 5302 4114 LT ST
|
3164 |
|
|
4904 4114 MT 4904 4114 LT 4911 4154 LT 5295 4154 LT 5302 4114 LT ST
|
3165 |
|
|
(7) 4918 4114 WT pop 0 originOffset 37 add RSS
|
3166 |
|
|
5302 4114 MT 5302 4114 LT 5309 4073 LT 5693 4073 LT 5700 4114 LT ST
|
3167 |
|
|
5302 4114 MT 5302 4114 LT 5309 4154 LT 5693 4154 LT 5700 4114 LT ST
|
3168 |
|
|
(0) 5316 4114 WT pop 0 originOffset 37 add RSS
|
3169 |
|
|
5700 4114 MT 5700 4114 LT 5707 4073 LT 6091 4073 LT 6098 4114 LT ST
|
3170 |
|
|
5700 4114 MT 5700 4114 LT 5707 4154 LT 6091 4154 LT 6098 4114 LT ST
|
3171 |
|
|
(1) 5714 4114 WT pop 0 originOffset 37 add RSS
|
3172 |
|
|
6098 4114 MT 6098 4114 LT 6105 4073 LT 6297 4073 LT ST
|
3173 |
|
|
6098 4114 MT 6098 4114 LT 6105 4154 LT 6297 4154 LT ST
|
3174 |
|
|
(2) 6112 4114 WT pop 0 originOffset 37 add RSS
|
3175 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) 3275 4297 WT TSE RSS
|
3176 |
|
|
3504 4188 MT 3518 4188 LS
|
3177 |
|
|
3902 4188 MT 3916 4188 LS
|
3178 |
|
|
4300 4188 MT 4314 4188 LS
|
3179 |
|
|
4698 4188 MT 4712 4188 LS
|
3180 |
|
|
5096 4188 MT 5110 4188 LS
|
3181 |
|
|
5494 4188 MT 5508 4188 LS
|
3182 |
|
|
5892 4188 MT 5906 4188 LS
|
3183 |
|
|
6290 4188 MT 6304 4188 LS
|
3184 |
|
|
3312 4258 MT 6297 4258 LS
|
3185 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) 3275 4441 WT TSE RSS
|
3186 |
|
|
3504 4332 MT 3518 4332 LS
|
3187 |
|
|
3902 4332 MT 3916 4332 LS
|
3188 |
|
|
4300 4332 MT 4314 4332 LS
|
3189 |
|
|
4698 4332 MT 4712 4332 LS
|
3190 |
|
|
5096 4332 MT 5110 4332 LS
|
3191 |
|
|
5494 4332 MT 5508 4332 LS
|
3192 |
|
|
5892 4332 MT 5906 4332 LS
|
3193 |
|
|
6290 4332 MT 6304 4332 LS
|
3194 |
|
|
3312 4402 MT 6297 4402 LS
|
3195 |
|
|
% draw footer
|
3196 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 4 Page: 7) 300 4799 WT TSW RSS
|
3197 |
|
|
grestore
|
3198 |
|
|
showpage
|
3199 |
|
|
%%Page: 8 8
|
3200 |
|
|
gsave
|
3201 |
|
|
90 rotate 0.12 dup neg scale
|
3202 |
|
|
% dump string table
|
3203 |
|
|
/NP {newpath} def/SD {setdash} def/CL {setrgbcolor} def/GR {setgray} def
|
3204 |
|
|
/SX {exch LEdge sub XScale mul MaxLabelWidth add LMargin add LEdge LabelWidth sub add exch} def/CSX {exch dup LabelWidth gt {exch SX} {exch} ifelse} def
|
3205 |
|
|
/MT {SX moveto} def/LS {SX lineto stroke} def/LT {SX lineto} def/LFS {SX lineto fill stroke} def/RSS {rmoveto show stroke} def/ST {stroke} def/WT {CSX moveto dup stringwidth pop} def/TSW {pop 0 originOffset} def
|
3206 |
|
|
/TSE {MaxLabelWidth LabelWidth sub LMargin add 0 rmoveto neg originOffset} def/TS {-2 div originOffset CSX} def
|
3207 |
|
|
/MLW {stringwidth pop dup MaxLabelWidth gt {/MaxLabelWidth exch def}{pop} ifelse XS} def
|
3208 |
|
|
/XS {/XScale LabelWidth LMargin sub MaxLabelWidth LEdge LabelWidth sub add sub REdge LEdge sub div 1 add def} def
|
3209 |
|
|
/ARC {5 -2 roll SX 5 2 roll arc} def
|
3210 |
|
|
/XScale 1 def/MaxLabelWidth 0 def/LMargin 300 def/LEdge 3312 def/REdge 5699 def/LabelWidth 3275 def
|
3211 |
|
|
/Helvetica findfont [74 0 0 -74 0 0] makefont setfont
|
3212 |
|
|
/originOffset currentfont /FontBBox get 1 get currentfont /FontMatrix get 3 get mul neg def
|
3213 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/width) MLW
|
3214 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/clk) MLW
|
3215 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rst) MLW
|
3216 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/id_freeze) MLW
|
3217 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_freeze) MLW
|
3218 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa) MLW
|
3219 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab) MLW
|
3220 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_dataa2) MLW
|
3221 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/rf_datab2) MLW
|
3222 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw) MLW
|
3223 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw) MLW
|
3224 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/ex_forw2) MLW
|
3225 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/wb_forw2) MLW
|
3226 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm) MLW
|
3227 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/simm2) MLW
|
3228 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a) MLW
|
3229 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b) MLW
|
3230 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_a2) MLW
|
3231 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/sel_b2) MLW
|
3232 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a) MLW
|
3233 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b) MLW
|
3234 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_a2) MLW
|
3235 |
|
|
(...r1200_cpu/or1200_cpu/or1200_operandmuxes/operand_b2) MLW
|
3236 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b) MLW
|
3237 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_b2) MLW
|
3238 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_in) MLW
|
3239 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/thread_out) MLW
|
3240 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a) MLW
|
3241 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/muxed_a2) MLW
|
3242 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) MLW
|
3243 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) MLW
|
3244 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) MLW
|
3245 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) MLW
|
3246 |
|
|
% draw waveform shading
|
3247 |
|
|
[] 0 SD
|
3248 |
|
|
2.995 setlinewidth
|
3249 |
|
|
|
3250 |
|
|
|
3251 |
|
|
|
3252 |
|
|
3312 410 MT 6297 410 LS
|
3253 |
|
|
3312 554 MT 6297 554 LS
|
3254 |
|
|
3312 698 MT 6297 698 LS
|
3255 |
|
|
3312 842 MT 6297 842 LS
|
3256 |
|
|
% draw timeline
|
3257 |
|
|
3351 4533 MT 3351 4570 LS
|
3258 |
|
|
3391 4533 MT 3391 4570 LS
|
3259 |
|
|
3431 4533 MT 3431 4570 LS
|
3260 |
|
|
3470 4533 MT 3470 4570 LS
|
3261 |
|
|
3551 4533 MT 3551 4570 LS
|
3262 |
|
|
3591 4533 MT 3591 4570 LS
|
3263 |
|
|
3630 4533 MT 3630 4570 LS
|
3264 |
|
|
3670 4533 MT 3670 4570 LS
|
3265 |
|
|
3710 4533 MT 3710 4570 LS
|
3266 |
|
|
3750 4533 MT 3750 4570 LS
|
3267 |
|
|
3790 4533 MT 3790 4570 LS
|
3268 |
|
|
3830 4533 MT 3830 4570 LS
|
3269 |
|
|
3869 4533 MT 3869 4570 LS
|
3270 |
|
|
3511 4506 MT 3511 4570 LS
|
3271 |
|
|
3949 4533 MT 3949 4570 LS
|
3272 |
|
|
3989 4533 MT 3989 4570 LS
|
3273 |
|
|
4028 4533 MT 4028 4570 LS
|
3274 |
|
|
4068 4533 MT 4068 4570 LS
|
3275 |
|
|
4108 4533 MT 4108 4570 LS
|
3276 |
|
|
4148 4533 MT 4148 4570 LS
|
3277 |
|
|
4188 4533 MT 4188 4570 LS
|
3278 |
|
|
4228 4533 MT 4228 4570 LS
|
3279 |
|
|
4267 4533 MT 4267 4570 LS
|
3280 |
|
|
3909 4506 MT 3909 4570 LS
|
3281 |
|
|
(240) 3909 4649 WT TS RSS
|
3282 |
|
|
4347 4533 MT 4347 4570 LS
|
3283 |
|
|
4387 4533 MT 4387 4570 LS
|
3284 |
|
|
4426 4533 MT 4426 4570 LS
|
3285 |
|
|
4466 4533 MT 4466 4570 LS
|
3286 |
|
|
4506 4533 MT 4506 4570 LS
|
3287 |
|
|
4546 4533 MT 4546 4570 LS
|
3288 |
|
|
4586 4533 MT 4586 4570 LS
|
3289 |
|
|
4626 4533 MT 4626 4570 LS
|
3290 |
|
|
4665 4533 MT 4665 4570 LS
|
3291 |
|
|
4307 4506 MT 4307 4570 LS
|
3292 |
|
|
4745 4533 MT 4745 4570 LS
|
3293 |
|
|
4785 4533 MT 4785 4570 LS
|
3294 |
|
|
4824 4533 MT 4824 4570 LS
|
3295 |
|
|
4864 4533 MT 4864 4570 LS
|
3296 |
|
|
4904 4533 MT 4904 4570 LS
|
3297 |
|
|
4944 4533 MT 4944 4570 LS
|
3298 |
|
|
4984 4533 MT 4984 4570 LS
|
3299 |
|
|
5024 4533 MT 5024 4570 LS
|
3300 |
|
|
5063 4533 MT 5063 4570 LS
|
3301 |
|
|
4705 4506 MT 4705 4570 LS
|
3302 |
|
|
(260) 4705 4649 WT TS RSS
|
3303 |
|
|
5143 4533 MT 5143 4570 LS
|
3304 |
|
|
5183 4533 MT 5183 4570 LS
|
3305 |
|
|
5222 4533 MT 5222 4570 LS
|
3306 |
|
|
5262 4533 MT 5262 4570 LS
|
3307 |
|
|
5302 4533 MT 5302 4570 LS
|
3308 |
|
|
5342 4533 MT 5342 4570 LS
|
3309 |
|
|
5382 4533 MT 5382 4570 LS
|
3310 |
|
|
5422 4533 MT 5422 4570 LS
|
3311 |
|
|
5461 4533 MT 5461 4570 LS
|
3312 |
|
|
5103 4506 MT 5103 4570 LS
|
3313 |
|
|
5541 4533 MT 5541 4570 LS
|
3314 |
|
|
5581 4533 MT 5581 4570 LS
|
3315 |
|
|
5620 4533 MT 5620 4570 LS
|
3316 |
|
|
5660 4533 MT 5660 4570 LS
|
3317 |
|
|
5700 4533 MT 5700 4570 LS
|
3318 |
|
|
5740 4533 MT 5740 4570 LS
|
3319 |
|
|
5780 4533 MT 5780 4570 LS
|
3320 |
|
|
5820 4533 MT 5820 4570 LS
|
3321 |
|
|
5859 4533 MT 5859 4570 LS
|
3322 |
|
|
5501 4506 MT 5501 4570 LS
|
3323 |
|
|
(280) 5501 4649 WT TS RSS
|
3324 |
|
|
5939 4533 MT 5939 4570 LS
|
3325 |
|
|
5979 4533 MT 5979 4570 LS
|
3326 |
|
|
6018 4533 MT 6018 4570 LS
|
3327 |
|
|
6058 4533 MT 6058 4570 LS
|
3328 |
|
|
6098 4533 MT 6098 4570 LS
|
3329 |
|
|
6138 4533 MT 6138 4570 LS
|
3330 |
|
|
6178 4533 MT 6178 4570 LS
|
3331 |
|
|
6218 4533 MT 6218 4570 LS
|
3332 |
|
|
6257 4533 MT 6257 4570 LS
|
3333 |
|
|
5899 4506 MT 5899 4570 LS
|
3334 |
|
|
6337 4533 MT 6337 4570 LS
|
3335 |
|
|
6377 4533 MT 6377 4570 LS
|
3336 |
|
|
6416 4533 MT 6416 4570 LS
|
3337 |
|
|
6456 4533 MT 6456 4570 LS
|
3338 |
|
|
6496 4533 MT 6496 4570 LS
|
3339 |
|
|
6536 4533 MT 6536 4570 LS
|
3340 |
|
|
6576 4533 MT 6576 4570 LS
|
3341 |
|
|
6616 4533 MT 6616 4570 LS
|
3342 |
|
|
6655 4533 MT 6655 4570 LS
|
3343 |
|
|
6297 4506 MT 6297 4570 LS
|
3344 |
|
|
(300) 6297 4649 WT TS RSS
|
3345 |
|
|
% draw grid
|
3346 |
|
|
3511 300 MT 3511 4506 LS
|
3347 |
|
|
3909 300 MT 3909 4506 LS
|
3348 |
|
|
4307 300 MT 4307 4506 LS
|
3349 |
|
|
4705 300 MT 4705 4506 LS
|
3350 |
|
|
5103 300 MT 5103 4506 LS
|
3351 |
|
|
5501 300 MT 5501 4506 LS
|
3352 |
|
|
5899 300 MT 5899 4506 LS
|
3353 |
|
|
6297 300 MT 6297 4506 LS
|
3354 |
|
|
% draw waveforms
|
3355 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a) 3275 409 WT TSE RSS
|
3356 |
|
|
3504 300 MT 3518 300 LS
|
3357 |
|
|
3902 300 MT 3916 300 LS
|
3358 |
|
|
4300 300 MT 4314 300 LS
|
3359 |
|
|
4698 300 MT 4712 300 LS
|
3360 |
|
|
5096 300 MT 5110 300 LS
|
3361 |
|
|
5494 300 MT 5508 300 LS
|
3362 |
|
|
5892 300 MT 5906 300 LS
|
3363 |
|
|
6290 300 MT 6304 300 LS
|
3364 |
|
|
3312 410 MT 6297 410 LS
|
3365 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b) 3275 553 WT TSE RSS
|
3366 |
|
|
3504 444 MT 3518 444 LS
|
3367 |
|
|
3902 444 MT 3916 444 LS
|
3368 |
|
|
4300 444 MT 4314 444 LS
|
3369 |
|
|
4698 444 MT 4712 444 LS
|
3370 |
|
|
5096 444 MT 5110 444 LS
|
3371 |
|
|
5494 444 MT 5508 444 LS
|
3372 |
|
|
5892 444 MT 5906 444 LS
|
3373 |
|
|
6290 444 MT 6304 444 LS
|
3374 |
|
|
3312 554 MT 6297 554 LS
|
3375 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_a2) 3275 697 WT TSE RSS
|
3376 |
|
|
3504 588 MT 3518 588 LS
|
3377 |
|
|
3902 588 MT 3916 588 LS
|
3378 |
|
|
4300 588 MT 4314 588 LS
|
3379 |
|
|
4698 588 MT 4712 588 LS
|
3380 |
|
|
5096 588 MT 5110 588 LS
|
3381 |
|
|
5494 588 MT 5508 588 LS
|
3382 |
|
|
5892 588 MT 5906 588 LS
|
3383 |
|
|
6290 588 MT 6304 588 LS
|
3384 |
|
|
3312 698 MT 6297 698 LS
|
3385 |
|
|
(/tb_or1200_cpu/or1200_cpu/or1200_operandmuxes/saved_b2) 3275 841 WT TSE RSS
|
3386 |
|
|
3504 732 MT 3518 732 LS
|
3387 |
|
|
3902 732 MT 3916 732 LS
|
3388 |
|
|
4300 732 MT 4314 732 LS
|
3389 |
|
|
4698 732 MT 4712 732 LS
|
3390 |
|
|
5096 732 MT 5110 732 LS
|
3391 |
|
|
5494 732 MT 5508 732 LS
|
3392 |
|
|
5892 732 MT 5906 732 LS
|
3393 |
|
|
6290 732 MT 6304 732 LS
|
3394 |
|
|
3312 842 MT 6297 842 LS
|
3395 |
|
|
% draw footer
|
3396 |
|
|
(Entity:tb_or1200_cpu Architecture: Date: Sat Aug 14 01:14:01 EDT 2004 Row: 4 Page: 8) 300 4799 WT TSW RSS
|
3397 |
|
|
grestore
|
3398 |
|
|
showpage
|
3399 |
|
|
%%EOF
|