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conte |
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/* */
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/* Basic NCSU Synthesis Script */
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/* */
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/* Set up for the 0.25um CMOSX library */
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/* */
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/* Revision History */
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/* 1/5/97 : Author P. Franzon */
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/* 1/2/98 : More heavilly commented */
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/* 8/8/04 : Modified by Balaji V. Iyer */
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/* (bviyer@ncsu.edu) */
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/* for the OPEN RISC 2 way Multithreading */
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/* project */
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/* Advisor: Dr. Tom Conte */
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/* */
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/********************************************************/
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/*//////////////////////////////////////////////////////////////////*/
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/*// //*/
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/*// Copyright (C) 2000 Authors and OPENCORES.ORG //*/
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/*// //*/
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/*// This source file may be used and distributed without //*/
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/*// restriction provided that this copyright statement is not //*/
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/*// removed from the file and that any derivative work contains //*/
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/*// the original copyright notice and the associated disclaimer. //*/
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/*// //*/
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/*// This source file is free software; you can redistribute it //*/
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/*// and/or modify it under the terms of the GNU Lesser General //*/
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/*// Public License as published by the Free Software Foundation; //*/
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/*// either version 2.1 of the License, or (at your option) any //*/
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/*// later version. //*/
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/*// //*/
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/*// This source is distributed in the hope that it will be //*/
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/*// useful, but WITHOUT ANY WARRANTY; without even the implied //*/
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/*// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //*/
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/*// PURPOSE. See the GNU Lesser General Public License for more //*/
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/*// details. //*/
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/*// //*/
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/*// You should have received a copy of the GNU Lesser General //*/
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/*// Public License along with this source; if not, download it //*/
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/*// from http://www.opencores.org/lgpl.shtml //*/
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/*// //*/
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/*//////////////////////////////////////////////////////////////////*/
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/********************************************************/
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/* */
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/* Read in Verilog file and map (synthesize) */
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/* onto a generic library */
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/* */
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/* MAKE SURE THAT YOU CORRECT ALL WARNINGS THAT APPEAR */
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/* during the execution of the read command are fixed */
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/* or understood to have no impact */
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/* */
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/* ALSO CHECK your latch/flip-flop list for unintended */
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/* latches */
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/* */
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/********************************************************/
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Read -f Verilog or1200_genpc.v
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Read -f Verilog or1200_amultp2_32x32.v
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Read -f Verilog or1200_if.v
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Read -f Verilog or1200_ctrl.v
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Read -f Verilog or1200_alu.v
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Read -f Verilog or1200_mult_mac.v
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Read -f Verilog or1200_except.v
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Read -f Verilog or1200_dpram_32x32.v
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Read -f Verilog or1200_rf.v
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Read -f Verilog or1200_rf_top.v
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Read -f Verilog or1200_mem2reg.v
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Read -f Verilog or1200_reg2mem.v
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Read -f Verilog or1200_lsu.v
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Read -f Verilog or1200_operandmuxes.v
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Read -f Verilog or1200_wbmux.v
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Read -f Verilog or1200_cfgr.v
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Read -f Verilog or1200_freeze.v
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Read -f Verilog or1200_sprs.v
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Read -f Verilog or1200_cpu.v
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current_design = or1200_cpu
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/********************************************************/
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/* */
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/* Our first Optimization 'compile' is intended to */
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/* produce a design that will meet hold-time */
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/* under worst-case conditions: */
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/* - slowest process corner */
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/* - highest operating temperature and lowest Vcc */
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/* - expected worst case clock skew */
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/* */
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/********************************************************/
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/*------------------------------------------------------*/
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/* Specify the worst case (slowest) libraries and */
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/* slowest temperature/Vcc conditions */
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/*------------------------------------------------------*/
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link_library = {"ncsulib25_worst.db"}
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target_library = {"ncsulib25_worst.db"}
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/* set_operating_conditions -library "ms080cmosxCells_XXW" "T125_V4.5" */
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/*------------------------------------------------------*/
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/* Specify a 250 ns clock period with 50% duty cycle */
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/* and a skew of 1 ns */
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/*------------------------------------------------------*/
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Create_clock -period 250000 -waveform {0 125000} clk
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set_clock_skew -uncertainty 1000 clk
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/*------------------------------------------------------*/
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/* Most libraries have bugs in them. */
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/* This library has cells that don't have a layout version */
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/* - the PULLUP cell is one of them */
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/*------------------------------------------------------*/
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/* set_dont_use ms080cmosxCells_XXW/PULLUP */
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/********************************************************/
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/* */
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/* Now set up the 'CONSTRAINTS' on the design: */
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/* 1. How much of the clock period is lost in the */
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/* modules connected to it */
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/* 2. What type of cells are driving the inputs */
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/* 3. What type of cells and how many (fanout) must it */
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/* be able to drive */
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/* */
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/********************************************************/
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/*------------------------------------------------------*/
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/* ASSUME being driven by a slowest D-flip-flop */
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/* The DFF cell has a clock-Q delay of 1.75 ns */
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/* Allow another 0.25 ns for wiring delay */
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/* NOTE: THESE ARE INITIAL ASSUMPTIONS ONLY */
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/*------------------------------------------------------*/
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set_input_delay 1100 -clock clk all_inputs() - clk
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/*------------------------------------------------------*/
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/* ASSUME this module is driving a D-flip-flip */
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/* The DFF cell has a set-up time of 1.4 ns */
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/* Allow another 0.25 ns for wiring delay */
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/* NOTE: THESE ARE INITIAL ASSUMPTIONS ONLY */
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/*------------------------------------------------------*/
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set_output_delay 950 -clock clk all_outputs()
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/*------------------------------------------------------*/
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/* ASSUME being driven by a D-flip-flop */
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/*------------------------------------------------------*/
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set_driving_cell -no_design_rule -cell "dp_2" -pin "q" all_inputs() - clk
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/*------------------------------------------------------*/
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/* ASSUME the woest case output load is */
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/* 3 D-flip-flop (D-inputs) and */
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/* and 0.5 units of wiring capacitance */
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/*------------------------------------------------------*/
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port_load = 0.5 + 3 * load_of (ncsulib25_worst/dp_2/ip)
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set_load port_load all_outputs()
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/********************************************************/
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/* */
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/* Now set the GOALS for the compile */
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/* */
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/* In most cases you want minimum area, so set the */
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/* goal for maximum area to be 0 */
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/* */
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/********************************************************/
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set_max_area 0
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link
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uniquify
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/*------------------------------------------------------*/
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/* During the initial map (synthesis), Synopsys might */
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/* have built parts (such as adders) using its */
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/* DesignWare(TM) library. In order to remap the */
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/* design to our CMOSX library AND to create scope */
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/* for logic reduction, I want to 'flatten out' the */
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/* DesignWare components. i.e. Make one flat design */
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/* */
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/* 'replace_synthetic' is the cleanest way of doing this*/
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/*------------------------------------------------------*/
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replace_synthetic -ungroup
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/*------------------------------------------------------*/
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/* check the design before otimization */
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/*------------------------------------------------------*/
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check_design
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check_timing
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/********************************************************/
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/* */
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/* Now resynthesize the design to meet constraints, */
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/* and try to best achieve the goal, and using the */
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/* CMOSX parts. In large designs, compile can take */
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/* a lllooonnnnggg time */
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/* */
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/********************************************************/
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/*------------------------------------------------------*/
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/* -map_effort specifies how much optimization effort */
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/* there is low, medium, and high */
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/* use high to squeeze out those last picoseconds */
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/* -verify_effort specifies how much effort to spend */
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/* making sure that the input and output designs */
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/* are equivalent logically */
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/*------------------------------------------------------*/
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compile -map_effort high /* -verify -verify_effort medium */
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/*------------------------------------------------------*/
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/* Now trace the critical (slowest) path and see if */
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/* the timing works. */
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/* */
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/* If the slack is NOT met, you HAVE A PROBLEM and */
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/* need to redesign or try some other minimization */
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/* tricks that Synopsys can do */
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/*------------------------------------------------------*/
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report_timing
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report_area
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/********************************************************/
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/* */
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/* This is your section to do different things to */
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/* improve timing or area - RTFM */
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/* */
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/********************************************************/
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/********************************************************/
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/* */
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/* Now resynthesize the design for the fastest corner */
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/* making sure that hold time conditions are met */
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/* */
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/********************************************************/
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/*------------------------------------------------------*/
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/* Specify the fastest process corner and lowest temp */
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/* And highest (fastest) Vcc */
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/*------------------------------------------------------*/
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/* link_library = {"ms080cmosxCells_XXB.db"} */
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/* target_library = {"ms080cmosxCells_XXB.db"} */
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/* set_operating_conditions -library "ms080cmosxCells_XXB" "T-55_V5.5" */
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/*------------------------------------------------------*/
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/* Since we have a 'new' library, we need to do this */
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/* again */
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/*------------------------------------------------------*/
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/* set_dont_use ms080cmosxCells_XXB/PULLUP */
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/*------------------------------------------------------*/
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/* Set the design rule to 'fix hold time violations' */
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/* Then compile the design again, telling Synopsys to */
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/* Only change the design if there are hold time */
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/* violations. */
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/*------------------------------------------------------*/
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/* set_fix_hold clk */
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/* compile -only_design_rule -incremental */
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/*------------------------------------------------------*/
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/* Report the fastest path. Make sure the hold */
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/* is actually met. */
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/*------------------------------------------------------*/
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/* report_timing -delay min */
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/*------------------------------------------------------*/
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/* Write out the 'fastest' (minimum) timing file */
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/* in Standard Delay Format. We might use this in later*/
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/* verification. */
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/*------------------------------------------------------*/
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/* write_timing -output or1200_rf_top_min.sdf -format sdf */
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/*------------------------------------------------------*/
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/* Since Synopsys has to insert logic to meet hold */
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/* violations, we might find that we have setup */
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/* violations now. SO lets recheck with the slowest */
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/* corner etc. */
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/* */
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/* YOU problems if the slack is NOT MET */
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/* */
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/* 'translate' means 'translate to new library' */
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/*------------------------------------------------------*/
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/* link_library = {"ms080cmosxCells_XXB.db"} */
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/* target_library = {"ms080cmosxCells_XXW.db"} */
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/* set_operating_conditions -library "ms080cmosxCells_XXW" "T125_V4.5" */
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/* translate */
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/* report_timing */
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/*------------------------------------------------------*/
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/* Write out the resulting netlist in Verliog format */
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/*------------------------------------------------------*/
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/* write -f verilog -o or1200_rf_top_final.v */
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/*------------------------------------------------------*/
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/* Write out the 'slowest' (maximum) timing file */
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/* in Standard Delay Format. We might use this in later*/
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/* verification. */
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/*------------------------------------------------------*/
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/* write_timing -output or1200_rf_top_max.sdf -format sdf */
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