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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_cpu.v] - Blame information for rev 4

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Line No. Rev Author Line
1 2 conte
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////  Modified by:                                                ////
18
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
19
////  Advisor:                                                    ////
20
////      - Dr. Tom Conte                                         ////
21
////                                                              ////
22
//////////////////////////////////////////////////////////////////////
23
////                                                              ////
24
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
25
////                                                              ////
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//// This source file may be used and distributed without         ////
27
//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
30
////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
33
//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
36
////                                                              ////
37
//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
42
////                                                              ////
43
//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48
//
49
// CVS Revision History
50
//
51
// $Log: not supported by cvs2svn $
52
// Revision 1.15  2004/05/09 19:49:04  lampret
53
// Added some l.cust5 custom instructions as example
54
//
55
// Revision 1.14  2004/04/05 08:29:57  lampret
56
// Merged branch_qmem into main tree.
57
//
58
// Revision 1.12.4.2  2004/02/11 01:40:11  lampret
59
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
60
//
61
// Revision 1.12.4.1  2003/12/09 11:46:48  simons
62
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
63
//
64
// Revision 1.12  2002/09/07 05:42:02  lampret
65
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
66
//
67
// Revision 1.11  2002/08/28 01:44:25  lampret
68
// Removed some commented RTL. Fixed SR/ESR flag bug.
69
//
70
// Revision 1.10  2002/07/14 22:17:17  lampret
71
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
72
//
73
// Revision 1.9  2002/03/29 16:29:37  lampret
74
// Fixed some ports in instnatiations that were removed from the modules
75
//
76
// Revision 1.8  2002/03/29 15:16:54  lampret
77
// Some of the warnings fixed.
78
//
79
// Revision 1.7  2002/02/11 04:33:17  lampret
80
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
81
//
82
// Revision 1.6  2002/02/01 19:56:54  lampret
83
// Fixed combinational loops.
84
//
85
// Revision 1.5  2002/01/28 01:15:59  lampret
86
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
87
//
88
// Revision 1.4  2002/01/18 14:21:43  lampret
89
// Fixed 'the NPC single-step fix'.
90
//
91
// Revision 1.3  2002/01/18 07:56:00  lampret
92
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
93
//
94
// Revision 1.2  2002/01/14 06:18:22  lampret
95
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
96
//
97
// Revision 1.1  2002/01/03 08:16:15  lampret
98
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
99
//
100
// Revision 1.19  2001/11/30 18:59:47  simons
101
// *** empty log message ***
102
//
103
// Revision 1.18  2001/11/23 21:42:31  simons
104
// Program counter divided to PPC and NPC.
105
//
106
// Revision 1.17  2001/11/23 08:38:51  lampret
107
// Changed DSR/DRR behavior and exception detection.
108
//
109
// Revision 1.16  2001/11/20 00:57:22  lampret
110
// Fixed width of du_except.
111
//
112
// Revision 1.15  2001/11/18 09:58:28  lampret
113
// Fixed some l.trap typos.
114
//
115
// Revision 1.14  2001/11/18 08:36:28  lampret
116
// For GDB changed single stepping and disabled trap exception.
117
//
118
// Revision 1.13  2001/11/13 10:02:21  lampret
119
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
120
//
121
// Revision 1.12  2001/11/12 01:45:40  lampret
122
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
123
//
124
// Revision 1.11  2001/11/10 03:43:57  lampret
125
// Fixed exceptions.
126
//
127
// Revision 1.10  2001/10/21 17:57:16  lampret
128
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
129
//
130
// Revision 1.9  2001/10/14 13:12:09  lampret
131
// MP3 version.
132
//
133
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
134
// no message
135
//
136
// Revision 1.4  2001/08/17 08:01:19  lampret
137
// IC enable/disable.
138
//
139
// Revision 1.3  2001/08/13 03:36:20  lampret
140
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
141
//
142
// Revision 1.2  2001/08/09 13:39:33  lampret
143
// Major clean-up.
144
//
145
// Revision 1.1  2001/07/20 00:46:03  lampret
146
// Development version of RTL. Libraries are missing.
147
//
148
//
149
 
150
// synopsys translate_off
151
`include "timescale.v"
152
// synopsys translate_on
153
`include "or1200_defines.v"
154
 
155
module or1200_cpu(
156
        // Clk & Rst
157
        clk, rst,
158
 
159
        // Insn interface
160
        ic_en,
161
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
162
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
163
        immu_en,
164
 
165
        // Debug unit
166
        ex_insn, ex_freeze, id_pc, branch_op,
167
        ex_insn2,               // bviyer
168
        spr_dat_npc, rf_dataw,
169
        du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
170
        du_except, du_dat_cpu,
171
 
172
        // Data interface
173
        dc_en,
174
        dcpu_adr_o,dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
175
        dcpu_adr_o2,dcpu_cycstb_o2, dcpu_we_o2,
176
        dcpu_sel_o2, dcpu_tag_o2, dcpu_dat_o2,
177
        dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
178
        // dcpu_dat_i2,dcpu_ack_i2,dcpu_rty_i2,dcpu_err_i2,dcpu_tag_i2,
179
        dmmu_en,
180
 
181
        // Interrupt & tick exceptions
182
        sig_int, sig_tick,
183
 
184
        // SPR interface
185
        supv, spr_addr, spr_addr2, spr_dat_cpu, spr_dat_pic, spr_dat_tt,
186
        spr_dat_pm,
187
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_cs2, spr_we
188
);
189
 
190
parameter dw = 32; //`OR1200_OPERAND_WIDTH;
191
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
192
 
193
//
194
// I/O ports
195
//
196
 
197
//
198
// Clk & Rst
199
//
200
input                           clk;
201
input                           rst;
202
 
203
//
204
// Insn (IC) interface
205
//
206
output                          ic_en;
207
output  [31:0]                   icpu_adr_o;
208
output                          icpu_cycstb_o;
209
output  [3:0]                    icpu_sel_o;
210
output  [3:0]                    icpu_tag_o;
211
// bviyer: increased the size of this to 64
212
input   [63:0]                   icpu_dat_i;
213
 
214
input                           icpu_ack_i;
215
input                           icpu_rty_i;
216
input                           icpu_err_i;
217
input   [31:0]                   icpu_adr_i;
218
input   [3:0]                    icpu_tag_i;
219
 
220
//
221
// Insn (IMMU) interface
222
//
223
output                          immu_en;
224
 
225
//
226
// Debug interface
227
//
228
output  [31:0]                   ex_insn;
229
output  [31:0]                   ex_insn2;
230
output                          ex_freeze;
231
output  [31:0]                   id_pc;
232
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
233
 
234
input                           du_stall;
235
input   [dw-1:0]         du_addr;
236
input   [dw-1:0]         du_dat_du;
237
input                           du_read;
238
input                           du_write;
239
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
240
input                           du_hwbkpt;
241
output  [12:0]                   du_except;
242
output  [dw-1:0]         du_dat_cpu;
243
output  [dw-1:0]         rf_dataw;
244
 
245
//
246
// Data (DC) interface
247
//
248
output  [31:0]                   dcpu_adr_o;
249
output                          dcpu_cycstb_o;
250
output                          dcpu_we_o;
251
output  [3:0]                    dcpu_sel_o;
252
output  [3:0]                    dcpu_tag_o;
253
output  [31:0]                   dcpu_dat_o;
254
//bviyer
255
output  [31:0]                   dcpu_adr_o2;
256
output                          dcpu_cycstb_o2;
257
output                          dcpu_we_o2;
258
output  [3:0]                    dcpu_sel_o2;
259
output  [3:0]                    dcpu_tag_o2;
260
output  [31:0]                   dcpu_dat_o2;
261
input   [31:0]                   dcpu_dat_i;
262
input                           dcpu_ack_i;
263
input                           dcpu_rty_i;
264
input                           dcpu_err_i;
265
input   [3:0]                    dcpu_tag_i;
266
output                          dc_en;
267
 
268
//
269
// Data (DMMU) interface
270
//
271
output                          dmmu_en;
272
 
273
//
274
// SPR interface
275
//
276
output                          supv;
277
input   [dw-1:0]         spr_dat_pic;
278
input   [dw-1:0]         spr_dat_tt;
279
input   [dw-1:0]         spr_dat_pm;
280
input   [dw-1:0]         spr_dat_dmmu;
281
input   [dw-1:0]         spr_dat_immu;
282
input   [dw-1:0]         spr_dat_du;
283
output  [dw-1:0]         spr_addr;
284
output  [dw-1:0]         spr_addr2;
285
output  [dw-1:0]         spr_dat_cpu;
286
output  [dw-1:0]         spr_dat_npc;
287
output  [dw-1:0]         spr_cs;
288
output  [dw-1:0]         spr_cs2;
289
output                          spr_we;
290
 
291
//
292
// Interrupt exceptions
293
//
294
input                           sig_int;
295
input                           sig_tick;
296
 
297
//
298
// Internal wires
299
//
300
wire    [31:0]                   if_insn;
301
wire    [31:0]                   if_insn2; // bviyer
302
wire    [31:0]                   if_pc;
303
wire    [31:2]                  lr_sav;
304
wire    [31:2]                  lr_sav2;  // bviyer
305
wire    [aw-1:0]         rf_addrw;
306
wire    [aw-1:0]         rf_addrw2;      // bviyer
307
wire    [aw-1:0]                 rf_addra;
308
wire    [aw-1:0]                 rf_addra2;      // bviyer
309
wire    [aw-1:0]                 rf_addrb;
310
wire    [aw-1:0]                 rf_addrb2;      // bviyer
311
wire                            rf_rda;
312
wire                            rf_rda2;        // bviyer
313
wire                            rf_rdb;
314
wire                            rf_rdb2;        // bviyer
315
wire    [dw-1:0]         simm;
316
wire    [dw-1:0]         simm2;          // bviyer
317
wire    [dw-1:2]                branch_addrofs;
318
wire    [dw-1:2]                branch_addrofs2;
319
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
320
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op2; // bviyer
321
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
322
wire    [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op2; // bviyer
323
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
324
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op2;       // bviyer
325
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
326
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op2; // bviyer
327
wire    [`OR1200_LSUOP_WIDTH-1:0]        lsu_op;
328
wire    [`OR1200_LSUOP_WIDTH-1:0]        lsu_op2; // bviyer
329
wire                            genpc_freeze;
330
wire                            if_freeze;
331
wire                            id_freeze;
332
wire                            ex_freeze;
333
wire                            wb_freeze;
334
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
335
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
336
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a2;         // bviyer
337
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b2;         // bviyer
338
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
339
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op2; // bviyer
340
wire    [dw-1:0]         rf_dataw;
341
wire    [dw-1:0]         rf_dataa;
342
wire    [dw-1:0]         rf_datab;
343
wire    [dw-1:0]         muxed_b;
344
wire    [dw-1:0]         wb_forw;
345
wire                            wbforw_valid;
346
wire                            wbforw2_valid; // bviyer
347
wire    [dw-1:0]         operand_a;
348
wire    [dw-1:0]         operand_b;
349
wire    [dw-1:0]         alu_dataout;
350
wire    [dw-1:0]         lsu_dataout;
351
wire    [dw-1:0]         sprs_dataout;
352
wire    [31:0]                   lsu_addrofs;
353
// added by bviyer
354
wire    [dw-1:0]         rf_dataw2;
355
wire    [dw-1:0]         rf_dataa2;
356
wire    [dw-1:0]         rf_datab2;
357
wire    [dw-1:0]         muxed_b2;
358
wire    [dw-1:0]         wb_forw2;
359
wire                            wbforw_valid2;
360
wire    [dw-1:0]         operand_a2;
361
wire    [dw-1:0]         operand_b2;
362
wire    [dw-1:0]         alu_dataout2;
363
wire    [dw-1:0]         lsu_dataout2;
364
wire    [dw-1:0]         sprs_dataout2;
365
wire    [31:0]                   lsu_addrofs2;
366
 
367
reg     [31:0]                   input_to_except_unit;   // bviyer
368
 
369
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
370
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle2;
371
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
372
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type2; // bviyer
373
wire    [4:0]                    cust5_op;
374
wire    [4:0]                    cust5_op2; // bviyer
375
wire    [6:0]                    cust5_limm;
376
wire    [6:0]                    cust5_limm2; // bviyer
377
wire                            flushpipe;
378
wire                            extend_flush;
379
wire                            branch_taken;
380
wire                            flag;
381
wire                            flag2;
382
wire                            flagforw;
383
wire                            flagforw2;      // bviyer
384
wire                            flag_we;
385
wire                            flag_we2;       // bviyer
386
wire                            carry;
387
wire                            cyforw;
388
wire                            cyforw2;        // bviyer
389
wire                            cy_we;
390
wire                            cy_we2;         // bviyer
391
wire                            lsu_stall;
392
wire                            lsu_stall2;     // bviyer
393
wire                            epcr_we;
394
wire                            eear_we;
395
wire                            esr_we;
396
wire                            pc_we;
397
wire    [31:0]                   epcr;
398
wire    [31:0]                   eear;
399
wire    [`OR1200_SR_WIDTH-1:0]   esr;
400
wire                            sr_we;
401
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
402
wire    [`OR1200_SR_WIDTH-1:0]   sr;
403
wire                            except_start;
404
wire                            except_started;
405
wire    [31:0]                   wb_insn;
406
wire    [31:0]                   wb_insn2;       // bviyer
407
wire    [15:0]                   spr_addrimm;
408
wire    [15:0]                   spr_addrimm2;   // bviyer
409
wire                            sig_syscall;
410
wire                            sig_syscall2; // bviyer
411
wire                            sig_trap;
412
wire                            sig_trap2;      // bviyer
413
wire    [31:0]                   spr_dat_cfgr;
414
wire    [31:0]                   spr_dat_cfgr2;  // bviyer
415
wire    [31:0]                   spr_dat_rf;
416
wire    [31:0]                  spr_dat_npc;
417
wire    [31:0]                   spr_dat_ppc;
418
wire    [31:0]                   spr_dat_mac;
419
wire                            force_dslot_fetch;
420
wire                            force_dslot_fetch2; // bviyer
421
wire                            no_more_dslot;
422
wire                            no_more_dslot2; // bviyer
423
wire                            ex_void;
424
wire                            ex_void2;       // bviyer
425
wire                            if_stall;
426
wire                            id_macrc_op;
427
wire                            id_macrc_op2;   // bviyer
428
wire                            ex_macrc_op;
429
wire                            ex_macrc_op2;   // bviyer
430
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
431
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op2;       // bviyer
432
wire    [31:0]                   mult_mac_result;
433
wire    [31:0]                   mult_mac_result2; // bviyer
434
wire                            mac_stall;
435
wire    [12:0]                   except_stop;
436
wire                            genpc_refetch;
437
wire                            rfe;
438
wire                            rfe2;
439
wire                            lsu_unstall;
440
wire                            lsu_unstall2;   // bviyer
441
wire                            except_align;
442
wire                            except_align2;  // bviyer
443
wire                            except_dtlbmiss;
444
wire                            except_dtlbmiss2;       // bviyer
445
wire                            except_dmmufault;
446
wire                            except_dmmufault2;      // bviyer
447
wire                            except_illegal;
448
wire                            except_illegal2; // bviyer
449
wire                            except_itlbmiss;
450
wire                            except_immufault;
451
wire                            except_ibuserr;
452
wire                            except_dbuserr;
453
wire                            except_dbuserr2;        // bviyer
454
wire                            abort_ex;
455
 
456
wire [31:0]                      temp_dcpu_adr_o;
457
wire [31:0]                      temp_dcpu_adr_o2;
458
 
459
 
460
 
461
//bviyer: threads
462
 
463
wire [2:0] wb_thread_from_wbmux;
464
wire [2:0] thread_out_to_if;
465
wire [2:0] thread_out_to_genpc;
466
wire [2:0] thread_out_to_ctrl;
467
wire [2:0] thread_out_to_register_file_top;
468
wire [2:0] thread_out_to_register_file_top2;
469
wire [2:0] thread_out_fetch_unit;
470
wire [2:0] thread_out_to_operand_muxes;
471
wire [2:0] thread_out_to_units;
472
wire [2:0] thread_out_to_wb_a;
473
wire [2:0] thread_out_to_wb_b;
474
wire [2:0] thread_out_to_wb_c;
475
wire [2:0] thread_out_to_wb_d;
476
wire [2:0] thread_out_to_wb_e;
477
wire [2:0] thread_out_to_wb_f;
478
wire [2:0] thread_out_to_wb_g;
479
wire [2:0] thread_out_to_wb_h;
480
 
481
 
482
 
483
 
484
//
485
// Send exceptions to Debug Unit
486
//
487
assign du_except = except_stop;
488
 
489
//
490
// Data cache enable
491
//
492
assign dc_en = sr[`OR1200_SR_DCE];
493
 
494
//
495
// Instruction cache enable
496
//
497
assign ic_en = sr[`OR1200_SR_ICE];
498
 
499
//
500
// DMMU enable
501
//
502
assign dmmu_en = sr[`OR1200_SR_DME];
503
 
504
//
505
// IMMU enable
506
//
507
assign immu_en = sr[`OR1200_SR_IME];
508
 
509
//
510
// SUPV bit
511
//
512
assign supv = sr[`OR1200_SR_SM];
513
 
514
//
515
// Instantiation of pc generation block // by bviyer
516
//
517
or1200_genpc or1200_genpc(
518
        .clk(clk),
519
        .rst(rst),
520
        .icpu_adr_o(icpu_adr_o),
521
        .icpu_cycstb_o(icpu_cycstb_o),
522
        .icpu_sel_o(icpu_sel_o),
523
        .icpu_tag_o(icpu_tag_o),
524
        .icpu_rty_i(icpu_rty_i),
525
        .icpu_adr_i(icpu_adr_i),
526
 
527
        .branch_op(branch_op),
528
        .except_type(except_type),
529
        .except_start(except_start),
530
        .except_prefix(sr[`OR1200_SR_EPH]),
531
        .branch_addrofs(branch_addrofs),
532
        .lr_restor(operand_b),
533
        .flag(flag),
534
        .taken(branch_taken),
535
        .binsn_addr(lr_sav),
536
        .epcr(epcr),
537
        .spr_dat_i(spr_dat_cpu),
538
        .spr_pc_we(pc_we),
539
        .genpc_refetch(genpc_refetch),
540
        .genpc_freeze(genpc_freeze),
541
        .genpc_stop_prefetch(1'b0),
542
        .no_more_dslot(no_more_dslot | no_more_dslot2),
543
// added by bviyer
544
        .branch_thread(thread_out_to_register_file_top),
545
        .except_thread(thread_out_to_genpc),
546
        .wb_thread(wb_thread_from_wbmux),
547
        .thread_out(thread_out_to_if)
548
);
549
 
550
//
551
// Instantiation of instruction fetch block
552
//
553
or1200_if or1200_if(
554
        .clk(clk),
555
        .rst(rst),
556
// bviyer: increased the size of this
557
        .icpu_dat_i(icpu_dat_i),
558
        .icpu_ack_i(icpu_ack_i),
559
        .icpu_err_i(icpu_err_i),
560
        .icpu_adr_i(icpu_adr_o),        // should be icpu_adr_o they messed up
561
        .icpu_tag_i(icpu_tag_i),
562
 
563
        .if_freeze(if_freeze),
564
 
565
        .if_insn(if_insn),
566
 
567
// bviyer: added if_insn2
568
        .if_insn2(if_insn2),
569
        .if_pc(if_pc),
570
        .flushpipe(flushpipe),
571
        .if_stall(if_stall),
572
        .no_more_dslot(no_more_dslot),
573
        .genpc_refetch(genpc_refetch),
574
        .rfe(rfe | rfe2),
575
        .except_itlbmiss(except_itlbmiss),
576
        .except_immufault(except_immufault),
577
        .except_ibuserr(except_ibuserr),
578
        .thread_in(thread_out_to_if),
579
        .thread_out(thread_out_to_ctrl)
580
);
581
 
582
 
583
//
584
// Instantiation of instruction decode/control logic
585
//
586
or1200_ctrl or1200_ctrl(
587
        .clk(clk),
588
        .rst(rst),
589
        .id_freeze(id_freeze),
590
        .ex_freeze(ex_freeze),
591
        .wb_freeze(wb_freeze),
592
        .flushpipe(flushpipe),
593
        .if_insn(if_insn),
594
        .ex_insn(ex_insn),
595
        .branch_op(branch_op),
596
        .branch_taken(branch_taken),
597
        .rf_addra(rf_addra),
598
        .rf_addrb(rf_addrb),
599
        .rf_rda(rf_rda),
600
        .rf_rdb(rf_rdb),
601
        .alu_op(alu_op),
602
        .mac_op(mac_op),
603
        .shrot_op(shrot_op),
604
        .comp_op(comp_op),
605
        .rf_addrw(rf_addrw),
606
        .rfwb_op(rfwb_op),
607
        .wb_insn(wb_insn),
608
        .simm(simm),
609
        .branch_addrofs(branch_addrofs),
610
        .lsu_addrofs(lsu_addrofs),
611
        .sel_a(sel_a),
612
        .sel_b(sel_b),
613
        .lsu_op(lsu_op),
614
        .cust5_op(cust5_op),
615
        .cust5_limm(cust5_limm),
616
        .multicycle(multicycle),
617
        .spr_addrimm(spr_addrimm),
618
        .wbforw_valid(wbforw_valid),
619
        .sig_syscall(sig_syscall),
620
        .sig_trap(sig_trap),
621
        .force_dslot_fetch(force_dslot_fetch),
622
        .no_more_dslot(no_more_dslot),
623
        .ex_void(ex_void),
624
        .id_macrc_op(id_macrc_op),
625
        .ex_macrc_op(ex_macrc_op),
626
        .rfe(rfe),
627
        .du_hwbkpt(du_hwbkpt),
628
        .except_illegal(except_illegal),
629
        .thread_in(thread_out_to_ctrl),
630
        .thread_out(thread_out_to_register_file_top)
631
);
632
 
633
//
634
//
635
// Instantiation of instruction decode/control logic
636
//
637
// bviyer: there are two decode units becuase we have two instructions coming in at one time thisway we can decode
638
// them both at the same time
639
or1200_ctrl or1200_ctrl2(
640
        .clk(clk),
641
        .rst(rst),
642
        .id_freeze(id_freeze),
643
        .ex_freeze(ex_freeze),
644
        .wb_freeze(wb_freeze),
645
        .flushpipe(flushpipe),
646
        .if_insn(if_insn2),
647
        .ex_insn(ex_insn2),
648
        .branch_op(branch_op2),
649
        .branch_taken(branch_taken),
650
        .rf_addra(rf_addra2),
651
        .rf_addrb(rf_addrb2),
652
        .rf_rda(rf_rda2),
653
        .rf_rdb(rf_rdb2),
654
        .alu_op(alu_op2),
655
        .mac_op(mac_op2),
656
        .shrot_op(shrot_op2),
657
        .comp_op(comp_op2),
658
        .rf_addrw(rf_addrw2),
659
        .rfwb_op(rfwb_op2),
660
        .wb_insn(wb_insn2),
661
        .simm(simm2),
662
        .branch_addrofs(branch_addrofs2),
663
        .lsu_addrofs(lsu_addrofs2),
664
        .sel_a(sel_a2),
665
        .sel_b(sel_b2),
666
        .lsu_op(lsu_op2),
667
        .cust5_op(cust5_op2),
668
        .cust5_limm(cust5_limm2),
669
        .multicycle(multicycle2),
670
        .spr_addrimm(spr_addrimm2),
671
        .wbforw_valid(wbforw_valid),
672
        .sig_syscall(sig_syscall2),
673
        .sig_trap(sig_trap2),
674
        .force_dslot_fetch(force_dslot_fetch2),
675
        .no_more_dslot(no_more_dslot2),
676
        .ex_void(ex_void2),
677
        .id_macrc_op(id_macrc_op2),
678
        .ex_macrc_op(ex_macrc_op2),
679
        .rfe(rfe2),
680
        .du_hwbkpt(du_hwbkpt),
681
        .except_illegal(except_illegal2),
682
        .thread_in(thread_out_to_ctrl),
683
        .thread_out(thread_out_to_register_file_top2)
684
// bviyer: one thing to note about the thread out of the 2 ctrl is that
685
// they both have to be the same value. This is how the compiler was designed
686
// and so we can have just pick either one to insert into the register file top
687
// and we can still get the same result
688
);
689
//
690
// Instantiation of register file
691
//
692
or1200_rf_top or1200_rf_top(
693
  .clk(clk),
694
  .rst(rst),
695
  .supv(sr[`OR1200_SR_SM]),
696
  .wb_freeze(wb_freeze),
697
  .addrw(rf_addrw),
698
  .dataw(rf_dataw),
699
  .id_freeze(id_freeze),
700
  .we(rfwb_op[0]),
701
  .flushpipe(flushpipe),
702
  .addra(rf_addra),
703
  .rda(rf_rda),
704
  .rdb(rf_rdb),
705
  .dataa(rf_dataa),
706
  .addrb(rf_addrb),
707
  .datab(rf_datab),
708
  .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
709
  .spr_write(spr_we),
710
  .spr_addr(spr_addr),
711
  .spr_dat_i(spr_dat_cpu),
712
  .spr_dat_o(spr_dat_rf),
713
//bviyer: these are the thigns I added
714
 
715
  .addrw2(rf_addrw2),
716
  .dataw2(rf_dataw2),
717
  .we2(rfwb_op2[0]),
718
  .addra2(rf_addra2),
719
  .addrb2(rf_addrb2),
720
  .dataa2(rf_dataa2),
721
  .datab2(rf_datab2),
722
  .rda2(rf_rda2),
723
  .rdb2(rf_rdb2),
724
  .current_thread_read(thread_out_to_register_file_top2),
725
  .current_thread_read_out(thread_out_to_operand_muxes),
726
  .current_thread_write(wb_thread_from_wbmux)
727
);
728
 
729
// bviyer: we no longer have one registers but 8, so we have to go through
730
// one register "top" to determine which register to assign the values to
731
// 
732
 
733
//
734
// Instantiation of operand muxes
735
//
736
or1200_operandmuxes or1200_operandmuxes(
737
        .clk(clk),
738
        .rst(rst),
739
        .id_freeze(id_freeze),
740
        .ex_freeze(ex_freeze),
741
        .rf_dataa(rf_dataa),
742
        .rf_datab(rf_datab),
743
        .ex_forw(rf_dataw),
744
        .wb_forw(wb_forw),
745
        .simm(simm),
746
        .sel_a(sel_a),
747
        .sel_b(sel_b),
748
        .operand_a(operand_a),
749
        .operand_b(operand_b),
750
        .muxed_b(muxed_b),
751
// added by bviyer
752
        .rf_dataa2(rf_dataa2),
753
        .rf_datab2(rf_datab2),
754
        .ex_forw2(rf_dataw2),
755
        .wb_forw2(wb_forw2),
756
        .simm2(simm2),
757
        .sel_a2(sel_a2),
758
        .sel_b2(sel_b2),
759
        .operand_a2(operand_a2),
760
        .operand_b2(operand_b2),
761
        .muxed_b2(muxed_b2),
762
        .thread_in(thread_out_to_operand_muxes),
763
        .thread_out(thread_out_to_units)
764
);
765
 
766
//
767
// Instantiation of CPU's ALU
768
//
769
or1200_alu or1200_alu(
770
        .a(operand_a),
771
        .b(operand_b),
772
        .mult_mac_result(mult_mac_result),
773
        .macrc_op(ex_macrc_op),
774
        .alu_op(alu_op),
775
        .shrot_op(shrot_op),
776
        .comp_op(comp_op),
777
        .cust5_op(cust5_op),
778
        .cust5_limm(cust5_limm),
779
        .result(alu_dataout),
780
        .flagforw(flagforw),
781
        .flag_we(flag_we),
782
        .cyforw(cyforw),
783
        .cy_we(cy_we),
784
        .carry(carry),
785
        .thread_in(thread_out_to_units),
786
        .thread_out(thread_out_to_wb_a)
787
);
788
 
789
//
790
//
791
// Instantiation of CPU's ALU
792
// bviyer: creating a 2nd ALU
793
or1200_alu or1200_alu2(
794
        .a(operand_a2),
795
        .b(operand_b2),
796
        .mult_mac_result(mult_mac_result2),
797
        .macrc_op(ex_macrc_op2),
798
        .alu_op(alu_op2),
799
        .shrot_op(shrot_op2),
800
        .comp_op(comp_op2),
801
        .cust5_op(cust5_op2),
802
        .cust5_limm(cust5_limm2),
803
        .result(alu_dataout2),
804
        .flagforw(flagforw2),
805
        .flag_we(flag_we2),
806
        .cyforw(cyforw2),
807
        .cy_we(cy_we2),
808
        .carry(carry),
809
        .thread_in(thread_out_to_units),
810
        .thread_out(thread_out_to_wb_b)
811
);
812
 
813
//
814
// Instantiation of CPU's multimac unit
815
//
816
or1200_mult_mac or1200_mult_mac(
817
        .clk(clk),
818
        .rst(rst),
819
        .ex_freeze(ex_freeze),
820
        .id_macrc_op(id_macrc_op),
821
        .macrc_op(ex_macrc_op),
822
        .a(operand_a),
823
        .b(operand_b),
824
        .mac_op(mac_op),
825
        .alu_op(alu_op),
826
        .result(mult_mac_result),
827
        .mac_stall_r(mac_stall),
828
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
829
        .spr_write(spr_we),
830
        .spr_addr(spr_addr),
831
        .spr_dat_i(spr_dat_cpu),
832
        .spr_dat_o(spr_dat_mac),
833
        .thread_in(thread_out_to_units),
834
        .thread_out(thread_out_to_wb_c)
835
);
836
//
837
// Instantiation of CPU's multimac unit
838
// bviyer: creating a 2nd multi_mac (a way to run the DSP Applications
839
or1200_mult_mac or1200_mult_mac2(
840
        .clk(clk),
841
        .rst(rst),
842
        .ex_freeze(ex_freeze),
843
        .id_macrc_op(id_macrc_op2),
844
        .macrc_op(ex_macrc_op2),
845
        .a(operand_a2),
846
        .b(operand_b2),
847
        .mac_op(mac_op2),
848
        .alu_op(alu_op2),
849
        .result(mult_mac_result2),
850
        .mac_stall_r(mac_stall),
851
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
852
        .spr_write(spr_we),
853
        .spr_addr(spr_addr2),
854
        .spr_dat_i(spr_dat_cpu),
855
        .spr_dat_o(spr_dat_mac),
856
        .thread_in(thread_out_to_units),
857
        .thread_out(thread_out_to_wb_d)
858
);
859
 
860
//
861
// Instantiation of CPU's SPRS block
862
//
863
or1200_sprs or1200_sprs(
864
        .clk(clk),
865
        .rst(rst),
866
        .addrbase(operand_a),
867
        .addrofs(spr_addrimm),
868
        .dat_i(operand_b),
869
        .alu_op(alu_op),
870
        .flagforw(flagforw | flagforw2),
871
        .flag_we(flag_we | flag_we2),
872
        .flag(flag),
873
        .cyforw(cyforw | cyforw2),
874
        .cy_we(cy_we | cy_we2),
875
        .carry(carry),
876
        .to_wbmux(sprs_dataout),
877
        .du_addr(du_addr),
878
        .du_dat_du(du_dat_du),
879
        .du_read(du_read),
880
        .du_write(du_write),
881
        .du_dat_cpu(du_dat_cpu),
882
        .spr_addr(spr_addr),
883
        .spr_addr2(spr_addr2),
884
        .spr_dat_pic(spr_dat_pic),
885
        .spr_dat_tt(spr_dat_tt),
886
        .spr_dat_pm(spr_dat_pm),
887
        .spr_dat_cfgr(spr_dat_cfgr),
888
        .spr_dat_cfgr2(spr_dat_cfgr2),
889
        .spr_dat_rf(spr_dat_rf),
890
        .spr_dat_npc(spr_dat_npc),
891
        .spr_dat_ppc(spr_dat_ppc),
892
        .spr_dat_mac(spr_dat_mac),
893
        .spr_dat_dmmu(spr_dat_dmmu),
894
        .spr_dat_immu(spr_dat_immu),
895
        .spr_dat_du(spr_dat_du),
896
        .spr_dat_o(spr_dat_cpu),
897
        .spr_cs(spr_cs),
898
        .spr_we(spr_we),
899
        .epcr_we(epcr_we),
900
        .eear_we(eear_we),
901
        .esr_we(esr_we),
902
        .pc_we(pc_we),
903
        .epcr(epcr),
904
        .eear(eear),
905
        .esr(esr),
906
        .except_started(except_started),
907
 
908
        .sr_we(sr_we),
909
        .to_sr(to_sr),
910
        .sr(sr),
911
        .branch_op(branch_op),
912
        .thread_in(thread_out_to_units),
913
        .thread_out(thread_out_to_wb_e)
914
);
915
 
916
//
917
// Instantiation of load/store unit
918
//
919
or1200_lsu or1200_lsu(
920
        .addrbase(operand_a),
921
        .addrofs(lsu_addrofs),
922
        .lsu_op(lsu_op),
923
        .lsu_datain(operand_b),
924
        .lsu_dataout(lsu_dataout),
925
        .lsu_stall(lsu_stall),
926
        .lsu_unstall(lsu_unstall),
927
        .du_stall(du_stall),
928
        .except_align(except_align),
929
        .except_dtlbmiss(except_dtlbmiss),
930
        .except_dmmufault(except_dmmufault),
931
        .except_dbuserr(except_dbuserr),
932
        .dcpu_adr_o(temp_dcpu_adr_o),
933
        .dcpu_cycstb_o(dcpu_cycstb_o),
934
        .dcpu_we_o(dcpu_we_o),
935
        .dcpu_sel_o(dcpu_sel_o),
936
        .dcpu_tag_o(dcpu_tag_o),
937
        .dcpu_dat_o(dcpu_dat_o),
938
        .dcpu_dat_i(dcpu_dat_i),
939
        .dcpu_ack_i(dcpu_ack_i),
940
        .dcpu_rty_i(dcpu_rty_i),
941
        .dcpu_err_i(dcpu_err_i),
942
        .dcpu_tag_i(dcpu_tag_i),
943
        .thread_in(thread_out_to_units),
944
        .thread_out(thread_out_to_wb_g)
945
);
946
 
947
assign dcpu_adr_o = temp_dcpu_adr_o;
948
assign dcpu_adr_o2= temp_dcpu_adr_o2;
949
 
950
always @(temp_dcpu_adr_o or temp_dcpu_adr_o2 or except_dtlbmiss or except_dtlbmiss2 or except_dmmufault or except_dmmufault2 or except_dbuserr or except_dbuserr2)
951
  if ((except_dtlbmiss | except_dmmufault | except_dbuserr) == 1'b1)
952
        input_to_except_unit = temp_dcpu_adr_o;
953
  else
954
        input_to_except_unit= temp_dcpu_adr_o2;
955
 
956
 
957
//
958
// Instantiation of load/store unit
959
//
960
or1200_lsu or1200_lsu2(
961
        .addrbase(operand_a2),
962
        .addrofs(lsu_addrofs2),
963
        .lsu_op(lsu_op2),
964
        .lsu_datain(operand_b2),
965
        .lsu_dataout(lsu_dataout2),
966
        .lsu_stall(lsu_stall2),
967
        .lsu_unstall(lsu_unstall2),
968
        .du_stall(du_stall),
969
        .except_align(except_align2),
970
        .except_dtlbmiss(except_dtlbmiss2),
971
        .except_dmmufault(except_dmmufault2),
972
        .except_dbuserr(except_dbuserr2),
973
 
974
        .dcpu_adr_o(temp_dcpu_adr_o2),
975
        .dcpu_cycstb_o(dcpu_cycstb_o2),
976
        .dcpu_we_o(dcpu_we_o2),
977
        .dcpu_sel_o(dcpu_sel_o2),
978
        .dcpu_tag_o(dcpu_tag_o2),
979
        .dcpu_dat_o(dcpu_dat_o2),
980
        .dcpu_dat_i(dcpu_dat_i),
981
        .dcpu_ack_i(dcpu_ack_i),
982
        .dcpu_rty_i(dcpu_rty_i),
983
        .dcpu_err_i(dcpu_err_i),
984
        .dcpu_tag_i(dcpu_tag_i),
985
        .thread_in(thread_out_to_units),
986
        .thread_out(thread_out_to_wb_h)
987
);
988
 
989
//
990
// Instantiation of write-back muxes
991
//
992
or1200_wbmux or1200_wbmux(
993
        .clk(clk),
994
        .rst(rst),
995
        .wb_freeze(wb_freeze),
996
        .rfwb_op(rfwb_op),
997
        .muxin_a(alu_dataout),
998
        .muxin_b(lsu_dataout),
999
        .muxin_c(sprs_dataout),
1000
        .muxin_d({lr_sav, 2'b0}),
1001
        .muxout(rf_dataw),
1002
        .muxreg(wb_forw),
1003
        .muxreg_valid(wbforw_valid),
1004
// added by bviyer
1005
        .rfwb_op2(rfwb_op2),
1006
        .muxin_a2(alu_dataout2),
1007
        .muxin_b2(lsu_dataout2),
1008
        .muxin_c2(sprs_dataout2),
1009
        .muxin_d2({lr_sav2,2'b0}),
1010
        .muxout2(rf_dataw2),
1011
        .muxreg2(wb_forw2),
1012
        .muxreg2_valid(wbforw_valid2),
1013
        .thread_in (thread_out_to_units),
1014
        .thread_out(wb_thread_from_wbmux)
1015
);
1016
 
1017
//
1018
// Instantiation of freeze logic
1019
//
1020
or1200_freeze or1200_freeze(
1021
        .clk(clk),
1022
        .rst(rst),
1023
        .multicycle(multicycle),
1024
        .flushpipe(flushpipe),
1025
        .extend_flush(extend_flush),
1026
        .lsu_stall(lsu_stall),
1027
        .if_stall(if_stall),
1028
        .lsu_unstall(lsu_unstall),
1029
        .force_dslot_fetch(force_dslot_fetch | force_dslot_fetch2),
1030
        .abort_ex(abort_ex),
1031
        .du_stall(du_stall),
1032
        .mac_stall(mac_stall),
1033
        .genpc_freeze(genpc_freeze),
1034
        .if_freeze(if_freeze),
1035
        .id_freeze(id_freeze),
1036
        .ex_freeze(ex_freeze),
1037
        .wb_freeze(wb_freeze),
1038
        .icpu_ack_i(icpu_ack_i),
1039
        .icpu_err_i(icpu_err_i)
1040
);
1041
 
1042
//
1043
// Instantiation of exception block
1044
//
1045
 
1046
// there is only one exception because if either of the two instruction 
1047
// causes an exceptions we squash the whole thing
1048
or1200_except or1200_except(
1049
        .clk(clk),
1050
        .rst(rst),
1051
        .sig_ibuserr(except_ibuserr),
1052
        .sig_dbuserr(except_dbuserr | except_dbuserr2),
1053
        .sig_illegal(except_illegal | except_illegal2),
1054
        .sig_align(except_align | except_align2),
1055
        .sig_range(1'b0),
1056
        .sig_dtlbmiss(except_dtlbmiss | except_dtlbmiss2),
1057
        .sig_dmmufault(except_dmmufault | except_dmmufault2),
1058
        .sig_int(sig_int),
1059
        .sig_syscall(sig_syscall | sig_syscall2),
1060
        .sig_trap(sig_trap | sig_trap2),
1061
        .sig_itlbmiss(except_itlbmiss),
1062
        .sig_immufault(except_immufault),
1063
        .sig_tick(sig_tick),
1064
        .branch_taken(branch_taken),
1065
        .icpu_ack_i(icpu_ack_i),
1066
        .icpu_err_i(icpu_err_i),
1067
        .dcpu_ack_i(dcpu_ack_i),
1068
        .dcpu_err_i(dcpu_err_i),
1069
        .genpc_freeze(genpc_freeze),
1070
        .id_freeze(id_freeze),
1071
        .ex_freeze(ex_freeze),
1072
        .wb_freeze(wb_freeze),
1073
        .if_stall(if_stall),
1074
        .if_pc(if_pc),
1075
        .id_pc(id_pc),
1076
        .lr_sav(lr_sav),
1077
        .flushpipe(flushpipe),
1078
        .extend_flush(extend_flush),
1079
        .except_type(except_type),
1080
        .except_start(except_start),
1081
        .except_started(except_started),
1082
        .except_stop(except_stop),
1083
        .ex_void(ex_void | ex_void2),
1084
        .spr_dat_ppc(spr_dat_ppc),
1085
        .spr_dat_npc(spr_dat_npc),
1086
 
1087
        .datain(operand_b),
1088
        .du_dsr(du_dsr),
1089
        .epcr_we(epcr_we),
1090
        .eear_we(eear_we),
1091
        .esr_we(esr_we),
1092
        .pc_we(pc_we),
1093
        .epcr(epcr),
1094
        .eear(eear),
1095
        .esr(esr),
1096
 
1097
        .lsu_addr(input_to_except_unit),
1098
        .sr_we(sr_we),
1099
        .to_sr(to_sr),
1100
        .sr(sr),
1101
        .abort_ex(abort_ex),
1102
        .thread_in(thread_out_to_units),
1103
        .thread_out(thread_out_to_genpc)
1104
);
1105
 
1106
//
1107
// Instantiation of configuration registers
1108
//
1109
or1200_cfgr or1200_cfgr(
1110
        .spr_addr(spr_addr),
1111
        .spr_dat_o(spr_dat_cfgr)
1112
);
1113
 
1114
//
1115
// Instantiation of configuration registers
1116
//
1117
or1200_cfgr or1200_cfgr2(
1118
        .spr_addr(spr_addr2),
1119
        .spr_dat_o(spr_dat_cfgr2)
1120
);
1121
 
1122
endmodule

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