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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_dc_top.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all DC blocks.                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.8  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.6.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.6.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.6  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.5  2002/08/18 19:54:47  lampret
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// Added store buffer.
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//
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// Revision 1.4  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.3  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.9  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
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// no message
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//
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// Revision 1.4  2001/08/13 03:36:20  lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/22 03:31:53  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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102
//
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// Data cache
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//
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module or1200_dc_top(
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        // Rst, clk and clock control
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        clk, rst,
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        // External i/f
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        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
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        dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
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113
        // Internal i/f
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        dc_en,
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        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
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        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
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        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
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119
`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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124
        // SPRs
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        spr_cs, spr_write, spr_dat_i
126
);
127
 
128
parameter dw = 32; // `OR1200_OPERAND_WIDTH;
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130
//
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// I/O
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//
133
 
134
//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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140
//
141
// External I/F
142
//
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output  [dw-1:0]         dcsb_dat_o;
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output  [31:0]                   dcsb_adr_o;
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output                          dcsb_cyc_o;
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output                          dcsb_stb_o;
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output                          dcsb_we_o;
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output  [3:0]                    dcsb_sel_o;
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output                          dcsb_cab_o;
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input   [dw-1:0]         dcsb_dat_i;
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input                           dcsb_ack_i;
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input                           dcsb_err_i;
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154
//
155
// Internal I/F
156
//
157
input                           dc_en;
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input   [31:0]                   dcqmem_adr_i;
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input                           dcqmem_cycstb_i;
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input                           dcqmem_ci_i;
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input                           dcqmem_we_i;
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input   [3:0]                    dcqmem_sel_i;
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input   [3:0]                    dcqmem_tag_i;
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input   [dw-1:0]         dcqmem_dat_i;
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output  [dw-1:0]         dcqmem_dat_o;
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output                          dcqmem_ack_o;
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output                          dcqmem_rty_o;
168
output                          dcqmem_err_o;
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output  [3:0]                    dcqmem_tag_o;
170
 
171
`ifdef OR1200_BIST
172
//
173
// RAM BIST
174
//
175
input mbist_si_i;
176
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
177
output mbist_so_o;
178
`endif
179
 
180
//
181
// SPR access
182
//
183
input                           spr_cs;
184
input                           spr_write;
185
input   [31:0]                   spr_dat_i;
186
 
187
//
188
// Internal wires and regs
189
//
190
wire                            tag_v;
191
wire    [`OR1200_DCTAG_W-2:0]    tag;
192
wire    [dw-1:0]         to_dcram;
193
wire    [dw-1:0]         from_dcram;
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wire    [31:0]                   saved_addr;
195
wire    [3:0]                    dcram_we;
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wire                            dctag_we;
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wire    [31:0]                   dc_addr;
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wire                            dcfsm_biu_read;
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wire                            dcfsm_biu_write;
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reg                             tagcomp_miss;
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wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
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wire                            dctag_en;
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wire                            dctag_v;
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wire                            dc_inv;
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wire                            dcfsm_first_hit_ack;
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wire                            dcfsm_first_miss_ack;
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wire                            dcfsm_first_miss_err;
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wire                            dcfsm_burst;
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wire                            dcfsm_tag_we;
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`ifdef OR1200_BIST
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//
212
// RAM BIST
213
//
214
wire                            mbist_ram_so;
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wire                            mbist_tag_so;
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wire                            mbist_ram_si = mbist_si_i;
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wire                            mbist_tag_si = mbist_ram_so;
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assign                          mbist_so_o = mbist_tag_so;
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`endif
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221
//
222
// Simple assignments
223
//
224
assign dcsb_adr_o = dc_addr;
225
assign dc_inv = spr_cs & spr_write;
226
assign dctag_we = dcfsm_tag_we | dc_inv;
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assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
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assign dctag_en = dc_inv | dc_en;
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assign dctag_v = ~dc_inv;
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231
//
232
// Data to BIU is from DCRAM when DC is enabled or from LSU when
233
// DC is disabled
234
//
235
assign dcsb_dat_o = dcqmem_dat_i;
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237
//
238
// Bypases of the DC when DC is disabled
239
//
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assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
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assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
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assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
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assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
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assign dcqmem_rty_o = ~dcqmem_ack_o;
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assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
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248
//
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// DC/LSU normal and error termination
250
//
251
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
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assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
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254
//
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// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
256
//
257
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
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259
//
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// Select between input data generated by LSU or by BIU
261
//
262
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
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264
//
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// Select between data generated by DCRAM or passed by BIU
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//
267
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
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//
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// Tag comparison
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//
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always @(tag or saved_addr or tag_v) begin
273
        if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
274
                tagcomp_miss = 1'b1;
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        else
276
                tagcomp_miss = 1'b0;
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end
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//
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// Instantiation of DC Finite State Machine
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//
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or1200_dc_fsm or1200_dc_fsm(
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        .clk(clk),
284
        .rst(rst),
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        .dc_en(dc_en),
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        .dcqmem_cycstb_i(dcqmem_cycstb_i),
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        .dcqmem_ci_i(dcqmem_ci_i),
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        .dcqmem_we_i(dcqmem_we_i),
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        .dcqmem_sel_i(dcqmem_sel_i),
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        .tagcomp_miss(tagcomp_miss),
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        .biudata_valid(dcsb_ack_i),
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        .biudata_error(dcsb_err_i),
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        .start_addr(dcqmem_adr_i),
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        .saved_addr(saved_addr),
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        .dcram_we(dcram_we),
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        .biu_read(dcfsm_biu_read),
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        .biu_write(dcfsm_biu_write),
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        .first_hit_ack(dcfsm_first_hit_ack),
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        .first_miss_ack(dcfsm_first_miss_ack),
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        .first_miss_err(dcfsm_first_miss_err),
301
        .burst(dcfsm_burst),
302
        .tag_we(dcfsm_tag_we),
303
        .dc_addr(dc_addr)
304
);
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306
//
307
// Instantiation of DC main memory
308
//
309
or1200_dc_ram or1200_dc_ram(
310
        .clk(clk),
311
        .rst(rst),
312
`ifdef OR1200_BIST
313
        // RAM BIST
314
        .mbist_si_i(mbist_ram_si),
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        .mbist_so_o(mbist_ram_so),
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        .mbist_ctrl_i(mbist_ctrl_i),
317
`endif
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        .addr(dc_addr[`OR1200_DCINDXH:2]),
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        .en(dc_en),
320
        .we(dcram_we),
321
        .datain(to_dcram),
322
        .dataout(from_dcram)
323
);
324
 
325
//
326
// Instantiation of DC TAG memory
327
//
328
or1200_dc_tag or1200_dc_tag(
329
        .clk(clk),
330
        .rst(rst),
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`ifdef OR1200_BIST
332
        // RAM BIST
333
        .mbist_si_i(mbist_tag_si),
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        .mbist_so_o(mbist_tag_so),
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        .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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        .addr(dctag_addr),
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        .en(dctag_en),
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        .we(dctag_we),
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        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
341
        .tag_v(tag_v),
342
        .tag(tag)
343
);
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endmodule

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