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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_defines.v] - Blame information for rev 4

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1 2 conte
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Parameters of the OR1200 core                               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////  Modified by:                                                ////
17
////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
18
////  Advisor:                                                    ////
19
////      - Dr. Tom Conte                                         ////
20
////                                                              ////
21
//////////////////////////////////////////////////////////////////////
22
////                                                              ////
23
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
24
////                                                              ////
25
//// This source file may be used and distributed without         ////
26
//// restriction provided that this copyright statement is not    ////
27
//// removed from the file and that any derivative work contains  ////
28
//// the original copyright notice and the associated disclaimer. ////
29
////                                                              ////
30
//// This source file is free software; you can redistribute it   ////
31
//// and/or modify it under the terms of the GNU Lesser General   ////
32
//// Public License as published by the Free Software Foundation; ////
33
//// either version 2.1 of the License, or (at your option) any   ////
34
//// later version.                                               ////
35
////                                                              ////
36
//// This source is distributed in the hope that it will be       ////
37
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
38
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
39
//// PURPOSE.  See the GNU Lesser General Public License for more ////
40
//// details.                                                     ////
41
////                                                              ////
42
//// You should have received a copy of the GNU Lesser General    ////
43
//// Public License along with this source; if not, download it   ////
44
//// from http://www.opencores.org/lgpl.shtml                     ////
45
////                                                              ////
46
//////////////////////////////////////////////////////////////////////
47
//
48
// CVS Revision History
49
//
50
// $Log: not supported by cvs2svn $
51
// Revision 1.41  2004/05/09 20:03:20  lampret
52
// By default l.cust5 insns are disabled
53
//
54
// Revision 1.40  2004/05/09 19:49:04  lampret
55
// Added some l.cust5 custom instructions as example
56
//
57
// Revision 1.39  2004/04/08 11:00:46  simont
58
// Add support for 512B instruction cache.
59
//
60
// Revision 1.38  2004/04/05 08:29:57  lampret
61
// Merged branch_qmem into main tree.
62
//
63
// Revision 1.35.4.6  2004/02/11 01:40:11  lampret
64
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
65
//
66
// Revision 1.35.4.5  2004/01/15 06:46:38  markom
67
// interface to debug changed; no more opselect; stb-ack protocol
68
//
69
// Revision 1.35.4.4  2004/01/11 22:45:46  andreje
70
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
71
//
72
// Revision 1.35.4.3  2003/12/17 13:43:38  simons
73
// Exception prefix configuration changed.
74
//
75
// Revision 1.35.4.2  2003/12/05 00:05:03  lampret
76
// Static exception prefix.
77
//
78
// Revision 1.35.4.1  2003/07/08 15:36:37  lampret
79
// Added embedded memory QMEM.
80
//
81
// Revision 1.35  2003/04/24 00:16:07  lampret
82
// No functional changes. Added defines to disable implementation of multiplier/MAC
83
//
84
// Revision 1.34  2003/04/20 22:23:57  lampret
85
// No functional change. Only added customization for exception vectors.
86
//
87
// Revision 1.33  2003/04/07 20:56:07  lampret
88
// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
89
//
90
// Revision 1.32  2003/04/07 01:26:57  lampret
91
// RFRAM defines comments updated. Altera LPM option added.
92
//
93
// Revision 1.31  2002/12/08 08:57:56  lampret
94
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
95
//
96
// Revision 1.30  2002/10/28 15:09:22  mohor
97
// Previous check-in was done by mistake.
98
//
99
// Revision 1.29  2002/10/28 15:03:50  mohor
100
// Signal scanb_sen renamed to scanb_en.
101
//
102
// Revision 1.28  2002/10/17 20:04:40  lampret
103
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
104
//
105
// Revision 1.27  2002/09/16 03:13:23  lampret
106
// Removed obsolete comment.
107
//
108
// Revision 1.26  2002/09/08 05:52:16  lampret
109
// Added optional l.div/l.divu insns. By default they are disabled.
110
//
111
// Revision 1.25  2002/09/07 19:16:10  lampret
112
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
113
//
114
// Revision 1.24  2002/09/07 05:42:02  lampret
115
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
116
//
117
// Revision 1.23  2002/09/04 00:50:34  lampret
118
// Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.
119
//
120
// Revision 1.22  2002/09/03 22:28:21  lampret
121
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
122
//
123
// Revision 1.21  2002/08/22 02:18:55  lampret
124
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
125
//
126
// Revision 1.20  2002/08/18 21:59:45  lampret
127
// Disable SB until it is tested
128
//
129
// Revision 1.19  2002/08/18 19:53:08  lampret
130
// Added store buffer.
131
//
132
// Revision 1.18  2002/08/15 06:04:11  lampret
133
// Fixed Xilinx trace buffer address. REported by Taylor Su.
134
//
135
// Revision 1.17  2002/08/12 05:31:44  lampret
136
// Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section.
137
//
138
// Revision 1.16  2002/07/14 22:17:17  lampret
139
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
140
//
141
// Revision 1.15  2002/06/08 16:20:21  lampret
142
// Added defines for enabling generic FF based memory macro for register file.
143
//
144
// Revision 1.14  2002/03/29 16:24:06  lampret
145
// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives
146
//
147
// Revision 1.13  2002/03/29 15:16:55  lampret
148
// Some of the warnings fixed.
149
//
150
// Revision 1.12  2002/03/28 19:25:42  lampret
151
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
152
//
153
// Revision 1.11  2002/03/28 19:13:17  lampret
154
// Updated defines.
155
//
156
// Revision 1.10  2002/03/14 00:30:24  lampret
157
// Added alternative for critical path in DU.
158
//
159
// Revision 1.9  2002/03/11 01:26:26  lampret
160
// Fixed async loop. Changed multiplier type for ASIC.
161
//
162
// Revision 1.8  2002/02/11 04:33:17  lampret
163
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
164
//
165
// Revision 1.7  2002/02/01 19:56:54  lampret
166
// Fixed combinational loops.
167
//
168
// Revision 1.6  2002/01/19 14:10:22  lampret
169
// Fixed OR1200_XILINX_RAM32X1D.
170
//
171
// Revision 1.5  2002/01/18 07:56:00  lampret
172
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
173
//
174
// Revision 1.4  2002/01/14 09:44:12  lampret
175
// Default ASIC configuration does not sample WB inputs.
176
//
177
// Revision 1.3  2002/01/08 00:51:08  lampret
178
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
179
//
180
// Revision 1.2  2002/01/03 21:23:03  lampret
181
// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.
182
//
183
// Revision 1.1  2002/01/03 08:16:15  lampret
184
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
185
//
186
// Revision 1.20  2001/12/04 05:02:36  lampret
187
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
188
//
189
// Revision 1.19  2001/11/27 19:46:57  lampret
190
// Now FPGA and ASIC target are separate.
191
//
192
// Revision 1.18  2001/11/23 21:42:31  simons
193
// Program counter divided to PPC and NPC.
194
//
195
// Revision 1.17  2001/11/23 08:38:51  lampret
196
// Changed DSR/DRR behavior and exception detection.
197
//
198
// Revision 1.16  2001/11/20 21:30:38  lampret
199
// Added OR1200_REGISTERED_INPUTS.
200
//
201
// Revision 1.15  2001/11/19 14:29:48  simons
202
// Cashes disabled.
203
//
204
// Revision 1.14  2001/11/13 10:02:21  lampret
205
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
206
//
207
// Revision 1.13  2001/11/12 01:45:40  lampret
208
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
209
//
210
// Revision 1.12  2001/11/10 03:43:57  lampret
211
// Fixed exceptions.
212
//
213
// Revision 1.11  2001/11/02 18:57:14  lampret
214
// Modified virtual silicon instantiations.
215
//
216
// Revision 1.10  2001/10/21 17:57:16  lampret
217
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
218
//
219
// Revision 1.9  2001/10/19 23:28:46  lampret
220
// Fixed some synthesis warnings. Configured with caches and MMUs.
221
//
222
// Revision 1.8  2001/10/14 13:12:09  lampret
223
// MP3 version.
224
//
225
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
226
// no message
227
//
228
// Revision 1.3  2001/08/17 08:01:19  lampret
229
// IC enable/disable.
230
//
231
// Revision 1.2  2001/08/13 03:36:20  lampret
232
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
233
//
234
// Revision 1.1  2001/08/09 13:39:33  lampret
235
// Major clean-up.
236
//
237
// Revision 1.2  2001/07/22 03:31:54  lampret
238
// Fixed RAM's oen bug. Cache bypass under development.
239
//
240
// Revision 1.1  2001/07/20 00:46:03  lampret
241
// Development version of RTL. Libraries are missing.
242
//
243
//
244
 
245
`ifdef DEFINE_FILE
246
`else
247
`define DEFINE_FILE
248
 
249
// `define BALAJI_TESTING       // this is mainly used to see if the thread is
250
                                // switching every cycle, please turn this off
251
                                // when you are running this chip for something
252
                                // useful. 
253
 
254
 
255
//
256
// Dump VCD
257
//
258
//`define OR1200_VCD_DUMP
259
 
260
//
261
// Generate debug messages during simulation
262
//
263
//`define OR1200_VERBOSE
264
 
265
//  `define OR1200_ASIC
266
////////////////////////////////////////////////////////
267
//
268
// Typical configuration for an ASIC
269
//
270
`ifdef OR1200_ASIC
271
 
272
//
273
// Target ASIC memories
274
//
275
//`define OR1200_ARTISAN_SSP
276
//`define OR1200_ARTISAN_SDP
277
//`define OR1200_ARTISAN_STP
278
`define OR1200_VIRTUALSILICON_SSP
279
//`define OR1200_VIRTUALSILICON_STP_T1
280
//`define OR1200_VIRTUALSILICON_STP_T2
281
 
282
//
283
// Do not implement Data cache
284
//
285
//`define OR1200_NO_DC
286
 
287
//
288
// Do not implement Insn cache
289
//
290
//`define OR1200_NO_IC
291
 
292
//
293
// Do not implement Data MMU
294
//
295
//`define OR1200_NO_DMMU
296
 
297
//
298
// Do not implement Insn MMU
299
//
300
//`define OR1200_NO_IMMU
301
 
302
//
303
// Select between ASIC optimized and generic multiplier
304
//
305
//`define OR1200_ASIC_MULTP2_32X32
306
`define OR1200_GENERIC_MULTP2_32X32
307
 
308
//
309
// Size/type of insn/data cache if implemented
310
//
311
// `define OR1200_IC_1W_512B
312
// `define OR1200_IC_1W_4KB
313
`define OR1200_IC_1W_8KB
314
// `define OR1200_DC_1W_4KB
315
`define OR1200_DC_1W_8KB
316
 
317
`else
318
 
319
 
320
/////////////////////////////////////////////////////////
321
//
322
// Typical configuration for an FPGA
323
//
324
 
325
//
326
// Target FPGA memories
327
//
328
//`define OR1200_ALTERA_LPM
329
// `define OR1200_XILINX_RAMB4
330
//`define OR1200_XILINX_RAM32X1D
331
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
332
 
333
//
334
// Do not implement Data cache
335
//
336
//`define OR1200_NO_DC
337
 
338
//
339
// Do not implement Insn cache
340
//
341
//`define OR1200_NO_IC
342
 
343
//
344
// Do not implement Data MMU
345
//
346
//`define OR1200_NO_DMMU
347
 
348
//
349
// Do not implement Insn MMU
350
//
351
//`define OR1200_NO_IMMU
352
 
353
//
354
// Select between ASIC and generic multiplier
355
//
356
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
357
//
358
//`define OR1200_ASIC_MULTP2_32X32
359
`define OR1200_GENERIC_MULTP2_32X32
360
 
361
//
362
// Size/type of insn/data cache if implemented
363
// (consider available FPGA memory resources)
364
//
365
//`define OR1200_IC_1W_512B
366
`define OR1200_IC_1W_4KB
367
//`define OR1200_IC_1W_8KB
368
`define OR1200_DC_1W_4KB
369
//`define OR1200_DC_1W_8KB
370
 
371
`endif
372
 
373
 
374
//////////////////////////////////////////////////////////
375
//
376
// Do not change below unless you know what you are doing
377
//
378
 
379
//
380
// Enable RAM BIST
381
//
382
// At the moment this only works for Virtual Silicon
383
// single port RAMs. For other RAMs it has not effect.
384
// Special wrapper for VS RAMs needs to be provided
385
// with scan flops to facilitate bist scan.
386
//
387
//`define OR1200_BIST
388
 
389
//
390
// Register OR1200 WISHBONE outputs
391
// (must be defined/enabled)
392
//
393
`define OR1200_REGISTERED_OUTPUTS
394
 
395
//
396
// Register OR1200 WISHBONE inputs
397
//
398
// (must be undefined/disabled)
399
//
400
//`define OR1200_REGISTERED_INPUTS
401
 
402
//
403
// Disable bursts if they are not supported by the
404
// memory subsystem (only affect cache line fill)
405
//
406
//`define OR1200_NO_BURSTS
407
//
408
 
409
//
410
// WISHBONE retry counter range
411
//
412
// 2^value range for retry counter. Retry counter
413
// is activated whenever *wb_rty_i is asserted and
414
// until retry counter expires, corresponding
415
// WISHBONE interface is deactivated.
416
//
417
// To disable retry counters and *wb_rty_i all together,
418
// undefine this macro.
419
//
420
//`define OR1200_WB_RETRY 7
421
 
422
//
423
// WISHBONE Consecutive Address Burst
424
//
425
// This was used prior to WISHBONE B3 specification
426
// to identify bursts. It is no longer needed but
427
// remains enabled for compatibility with old designs.
428
//
429
// To remove *wb_cab_o ports undefine this macro.
430
//
431
`define OR1200_WB_CAB
432
 
433
//
434
// WISHBONE B3 compatible interface
435
//
436
// This follows the WISHBONE B3 specification.
437
// It is not enabled by default because most
438
// designs still don't use WB b3.
439
//
440
// To enable *wb_cti_o/*wb_bte_o ports,
441
// define this macro.
442
//
443
//`define OR1200_WB_B3
444
 
445
//
446
// Enable additional synthesis directives if using
447
// _Synopsys_ synthesis tool
448
//
449
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
450
 
451
//
452
// Enables default statement in some case blocks
453
// and disables Synopsys synthesis directive full_case
454
//
455
// By default it is enabled. When disabled it
456
// can increase clock frequency.
457
//
458
`define OR1200_CASE_DEFAULT
459
 
460
//
461
// Operand width / register file address width
462
//
463
// (DO NOT CHANGE)
464
// 
465
// yes I changed it.. by Balaji V. Iyer, (bviyer@ncsu.edu)
466
// this is the only way to make it two way VLIW
467
// 
468
`define OR1200_OPERAND_WIDTH            64
469
`define OR1200_REGFILE_ADDR_WIDTH       5
470
 
471
//
472
// l.add/l.addi/l.and and optional l.addc/l.addic
473
// also set (compare) flag when result of their
474
// operation equals zero
475
//
476
// At the time of writing this, default or32
477
// C/C++ compiler doesn't generate code that
478
// would benefit from this optimization.
479
//
480
// By default this optimization is disabled to
481
// save area.
482
//
483
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
484
 
485
//
486
// Implement l.addc/l.addic instructions
487
//
488
// By default implementation of l.addc/l.addic
489
// instructions is enabled in case you need them.
490
// If you don't use them, then disable implementation
491
// to save area.
492
//
493
`define OR1200_IMPL_ADDC
494
 
495
//
496
// Implement carry bit SR[CY]
497
//
498
// By default implementation of SR[CY] is enabled
499
// to be compliant with the simulator. However
500
// SR[CY] is explicitly only used by l.addc/l.addic
501
// instructions and if these two insns are not
502
// implemented there is not much point having SR[CY].
503
//
504
`define OR1200_IMPL_CY
505
 
506
//
507
// Implement optional l.div/l.divu instructions
508
//
509
// By default divide instructions are not implemented
510
// to save area and increase clock frequency. or32 C/C++
511
// compiler can use soft library for division.
512
//
513
// To implement divide, multiplier needs to be implemented.
514
//
515
//`define OR1200_IMPL_DIV
516
 
517
//
518
// Implement rotate in the ALU
519
//
520
// At the time of writing this, or32
521
// C/C++ compiler doesn't generate rotate
522
// instructions. However or32 assembler
523
// can assemble code that uses rotate insn.
524
// This means that rotate instructions
525
// must be used manually inserted.
526
//
527
// By default implementation of rotate
528
// is disabled to save area and increase
529
// clock frequency.
530
//
531
//`define OR1200_IMPL_ALU_ROTATE
532
 
533
//
534
// Type of ALU compare to implement
535
//
536
// Try either one to find what yields
537
// higher clock frequencyin your case.
538
//
539
//`define OR1200_IMPL_ALU_COMP1
540
`define OR1200_IMPL_ALU_COMP2
541
 
542
//
543
// Implement multiplier
544
//
545
// By default multiplier is implemented
546
//
547
`define OR1200_MULT_IMPLEMENTED
548
 
549
//
550
// Implement multiply-and-accumulate
551
//
552
// By default MAC is implemented. To
553
// implement MAC, multiplier needs to be
554
// implemented.
555
//
556
`define OR1200_MAC_IMPLEMENTED
557
 
558
//
559
// Low power, slower multiplier
560
//
561
// Select between low-power (larger) multiplier
562
// and faster multiplier. The actual difference
563
// is only AND logic that prevents distribution
564
// of operands into the multiplier when instruction
565
// in execution is not multiply instruction
566
//
567
//`define OR1200_LOWPWR_MULT
568
 
569
//
570
// Clock ratio RISC clock versus WB clock
571
//
572
// If you plan to run WB:RISC clock fixed to 1:1, disable
573
// both defines
574
//
575
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
576
// and use clmode to set ratio
577
//
578
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
579
// clmode to set ratio
580
//
581
`define OR1200_CLKDIV_2_SUPPORTED
582
//`define OR1200_CLKDIV_4_SUPPORTED
583
 
584
//
585
// Type of register file RAM
586
//
587
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
588
// `define OR1200_RFRAM_TWOPORT
589
//
590
// Memory macro dual port (see or1200_dpram_32x32.v)
591
`define OR1200_RFRAM_DUALPORT
592
//
593
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
594
//`define OR1200_RFRAM_GENERIC
595
 
596
//
597
// Type of mem2reg aligner to implement.
598
//
599
// Once OR1200_IMPL_MEM2REG2 yielded faster
600
// circuit, however with today tools it will
601
// most probably give you slower circuit.
602
//
603
`define OR1200_IMPL_MEM2REG1
604
//`define OR1200_IMPL_MEM2REG2
605
 
606
//
607
// ALUOPs
608
//
609
`define OR1200_ALUOP_WIDTH      4
610
`define OR1200_ALUOP_NOP        4'd4
611
/* Order defined by arith insns that have two source operands both in regs
612
   (see binutils/include/opcode/or32.h) */
613
`define OR1200_ALUOP_ADD        4'd0
614
`define OR1200_ALUOP_ADDC       4'd1
615
`define OR1200_ALUOP_SUB        4'd2
616
`define OR1200_ALUOP_AND        4'd3
617
`define OR1200_ALUOP_OR         4'd4
618
`define OR1200_ALUOP_XOR        4'd5
619
`define OR1200_ALUOP_MUL        4'd6
620
`define OR1200_ALUOP_CUST5      4'd7
621
`define OR1200_ALUOP_SHROT      4'd8
622
`define OR1200_ALUOP_DIV        4'd9
623
`define OR1200_ALUOP_DIVU       4'd10
624
/* Order not specifically defined. */
625
`define OR1200_ALUOP_IMM        4'd11
626
`define OR1200_ALUOP_MOVHI      4'd12
627
`define OR1200_ALUOP_COMP       4'd13
628
`define OR1200_ALUOP_MTSR       4'd14
629
`define OR1200_ALUOP_MFSR       4'd15
630
 
631
//
632
// MACOPs
633
//
634
`define OR1200_MACOP_WIDTH      2
635
`define OR1200_MACOP_NOP        2'b00
636
`define OR1200_MACOP_MAC        2'b01
637
`define OR1200_MACOP_MSB        2'b10
638
 
639
//
640
// Shift/rotate ops
641
//
642
`define OR1200_SHROTOP_WIDTH    2
643
`define OR1200_SHROTOP_NOP      2'd0
644
`define OR1200_SHROTOP_SLL      2'd0
645
`define OR1200_SHROTOP_SRL      2'd1
646
`define OR1200_SHROTOP_SRA      2'd2
647
`define OR1200_SHROTOP_ROR      2'd3
648
 
649
// Execution cycles per instruction
650
`define OR1200_MULTICYCLE_WIDTH 2
651
`define OR1200_ONE_CYCLE                2'd0
652
`define OR1200_TWO_CYCLES               2'd1
653
 
654
// Operand MUX selects
655
`define OR1200_SEL_WIDTH                2
656
`define OR1200_SEL_RF                   2'd0
657
`define OR1200_SEL_IMM                  2'd1
658
`define OR1200_SEL_EX_FORW              2'd2
659
`define OR1200_SEL_WB_FORW              2'd3
660
 
661
//
662
// BRANCHOPs
663
//
664
`define OR1200_BRANCHOP_WIDTH           3
665
`define OR1200_BRANCHOP_NOP             3'd0
666
`define OR1200_BRANCHOP_J               3'd1
667
`define OR1200_BRANCHOP_JR              3'd2
668
`define OR1200_BRANCHOP_BAL             3'd3
669
`define OR1200_BRANCHOP_BF              3'd4
670
`define OR1200_BRANCHOP_BNF             3'd5
671
`define OR1200_BRANCHOP_RFE             3'd6
672
 
673
//
674
// LSUOPs
675
//
676
// Bit 0: sign extend
677
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
678
// Bit 3: 0 load, 1 store
679
`define OR1200_LSUOP_WIDTH              4
680
`define OR1200_LSUOP_NOP                4'b0000
681
`define OR1200_LSUOP_LBZ                4'b0010
682
`define OR1200_LSUOP_LBS                4'b0011
683
`define OR1200_LSUOP_LHZ                4'b0100
684
`define OR1200_LSUOP_LHS                4'b0101
685
`define OR1200_LSUOP_LWZ                4'b0110
686
`define OR1200_LSUOP_LWS                4'b0111
687
`define OR1200_LSUOP_LD         4'b0001
688
`define OR1200_LSUOP_SD         4'b1000
689
`define OR1200_LSUOP_SB         4'b1010
690
`define OR1200_LSUOP_SH         4'b1100
691
`define OR1200_LSUOP_SW         4'b1110
692
 
693
// FETCHOPs
694
`define OR1200_FETCHOP_WIDTH            1
695
`define OR1200_FETCHOP_NOP              1'b0
696
`define OR1200_FETCHOP_LW               1'b1
697
 
698
//
699
// Register File Write-Back OPs
700
//
701
// Bit 0: register file write enable
702
// Bits 2-1: write-back mux selects
703
`define OR1200_RFWBOP_WIDTH             3
704
`define OR1200_RFWBOP_NOP               3'b000
705
`define OR1200_RFWBOP_ALU               3'b001
706
`define OR1200_RFWBOP_LSU               3'b011
707
`define OR1200_RFWBOP_SPRS              3'b101
708
`define OR1200_RFWBOP_LR                3'b111
709
 
710
// Compare instructions
711
`define OR1200_COP_SFEQ       3'b000
712
`define OR1200_COP_SFNE       3'b001
713
`define OR1200_COP_SFGT       3'b010
714
`define OR1200_COP_SFGE       3'b011
715
`define OR1200_COP_SFLT       3'b100
716
`define OR1200_COP_SFLE       3'b101
717
`define OR1200_COP_X          3'b111
718
`define OR1200_SIGNED_COMPARE 'd3
719
`define OR1200_COMPOP_WIDTH     4
720
 
721
//
722
// TAGs for instruction bus
723
//
724
`define OR1200_ITAG_IDLE        4'h0    // idle bus
725
`define OR1200_ITAG_NI          4'h1    // normal insn
726
`define OR1200_ITAG_BE          4'hb    // Bus error exception
727
`define OR1200_ITAG_PE          4'hc    // Page fault exception
728
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
729
 
730
//
731
// TAGs for data bus
732
//
733
`define OR1200_DTAG_IDLE        4'h0    // idle bus
734
`define OR1200_DTAG_ND          4'h1    // normal data
735
`define OR1200_DTAG_AE          4'ha    // Alignment exception
736
`define OR1200_DTAG_BE          4'hb    // Bus error exception
737
`define OR1200_DTAG_PE          4'hc    // Page fault exception
738
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
739
 
740
 
741
//////////////////////////////////////////////
742
//
743
// ORBIS32 ISA specifics
744
//
745
 
746
// SHROT_OP position in machine word
747
`define OR1200_SHROTOP_POS              7:6
748
 
749
// ALU instructions multicycle field in machine word
750
`define OR1200_ALUMCYC_POS              9:8
751
 
752
//
753
// Instruction opcode groups (basic)
754
//
755
`define OR1200_OR32_J                 6'b000000
756
`define OR1200_OR32_JAL               6'b000001
757
`define OR1200_OR32_BNF               6'b000011
758
`define OR1200_OR32_BF                6'b000100
759
`define OR1200_OR32_NOP               6'b000101
760
`define OR1200_OR32_MOVHI             6'b000110
761
`define OR1200_OR32_XSYNC             6'b001000
762
`define OR1200_OR32_RFE               6'b001001
763
/* */
764
`define OR1200_OR32_JR                6'b010001
765
`define OR1200_OR32_JALR              6'b010010
766
`define OR1200_OR32_MACI              6'b010011
767
/* */
768
`define OR1200_OR32_LWZ               6'b100001
769
`define OR1200_OR32_LBZ               6'b100011
770
`define OR1200_OR32_LBS               6'b100100
771
`define OR1200_OR32_LHZ               6'b100101
772
`define OR1200_OR32_LHS               6'b100110
773
`define OR1200_OR32_ADDI              6'b100111
774
`define OR1200_OR32_ADDIC             6'b101000
775
`define OR1200_OR32_ANDI              6'b101001
776
`define OR1200_OR32_ORI               6'b101010
777
`define OR1200_OR32_XORI              6'b101011
778
`define OR1200_OR32_MULI              6'b101100
779
`define OR1200_OR32_MFSPR             6'b101101
780
`define OR1200_OR32_SH_ROTI           6'b101110
781
`define OR1200_OR32_SFXXI             6'b101111
782
/* */
783
`define OR1200_OR32_MTSPR             6'b110000
784
`define OR1200_OR32_MACMSB            6'b110001
785
/* */
786
`define OR1200_OR32_SW                6'b110101
787
`define OR1200_OR32_SB                6'b110110
788
`define OR1200_OR32_SH                6'b110111
789
`define OR1200_OR32_ALU               6'b111000
790
`define OR1200_OR32_SFXX              6'b111001
791
//`define OR1200_OR32_CUST5             6'b111100
792
 
793
 
794
/////////////////////////////////////////////////////
795
//
796
// Exceptions
797
//
798
 
799
//
800
// Exception vectors per OR1K architecture:
801
// 0xPPPPP100 - reset
802
// 0xPPPPP200 - bus error
803
// ... etc
804
// where P represents exception prefix.
805
//
806
// Exception vectors can be customized as per
807
// the following formula:
808
// 0xPPPPPNVV - exception N
809
//
810
// P represents exception prefix
811
// N represents exception N
812
// VV represents length of the individual vector space,
813
//   usually it is 8 bits wide and starts with all bits zero
814
//
815
 
816
//
817
// PPPPP and VV parts
818
//
819
// Sum of these two defines needs to be 28
820
//
821
`define OR1200_EXCEPT_EPH0_P 20'h00000
822
`define OR1200_EXCEPT_EPH1_P 20'hF0000
823
`define OR1200_EXCEPT_V            8'h00
824
 
825
//
826
// N part width
827
//
828
`define OR1200_EXCEPT_WIDTH 4
829
 
830
//
831
// Definition of exception vectors
832
//
833
// To avoid implementation of a certain exception,
834
// simply comment out corresponding line
835
//
836
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
837
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
838
`define OR1200_EXCEPT_BREAK             `OR1200_EXCEPT_WIDTH'hd
839
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
840
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
841
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
842
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
843
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
844
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
845
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
846
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
847
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
848
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
849
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
850
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
851
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
852
 
853
 
854
/////////////////////////////////////////////////////
855
//
856
// SPR groups
857
//
858
 
859
// Bits that define the group
860
`define OR1200_SPR_GROUP_BITS   15:11
861
 
862
// Width of the group bits
863
`define OR1200_SPR_GROUP_WIDTH  5
864
 
865
// Bits that define offset inside the group
866
`define OR1200_SPR_OFS_BITS 10:0
867
 
868
// List of groups
869
`define OR1200_SPR_GROUP_SYS    5'd00
870
`define OR1200_SPR_GROUP_DMMU   5'd01
871
`define OR1200_SPR_GROUP_IMMU   5'd02
872
`define OR1200_SPR_GROUP_DC     5'd03
873
`define OR1200_SPR_GROUP_IC     5'd04
874
`define OR1200_SPR_GROUP_MAC    5'd05
875
`define OR1200_SPR_GROUP_DU     5'd06
876
`define OR1200_SPR_GROUP_PM     5'd08
877
`define OR1200_SPR_GROUP_PIC    5'd09
878
`define OR1200_SPR_GROUP_TT     5'd10
879
 
880
 
881
/////////////////////////////////////////////////////
882
//
883
// System group
884
//
885
 
886
//
887
// System registers
888
//
889
`define OR1200_SPR_CFGR         7'd0
890
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
891
`define OR1200_SPR_NPC          11'd16
892
`define OR1200_SPR_SR           11'd17
893
`define OR1200_SPR_PPC          11'd18
894
`define OR1200_SPR_EPCR         11'd32
895
`define OR1200_SPR_EEAR         11'd48
896
`define OR1200_SPR_ESR          11'd64
897
 
898
//
899
// SR bits
900
//
901
`define OR1200_SR_WIDTH 16
902
`define OR1200_SR_SM   0
903
`define OR1200_SR_TEE  1
904
`define OR1200_SR_IEE  2
905
`define OR1200_SR_DCE  3
906
`define OR1200_SR_ICE  4
907
`define OR1200_SR_DME  5
908
`define OR1200_SR_IME  6
909
`define OR1200_SR_LEE  7
910
`define OR1200_SR_CE   8
911
`define OR1200_SR_F    9
912
`define OR1200_SR_CY   10       // Unused
913
`define OR1200_SR_OV   11       // Unused
914
`define OR1200_SR_OVE  12       // Unused
915
`define OR1200_SR_DSX  13       // Unused
916
`define OR1200_SR_EPH  14
917
`define OR1200_SR_FO   15
918
`define OR1200_SR_CID  31:28    // Unimplemented
919
 
920
//
921
// Bits that define offset inside the group
922
//
923
`define OR1200_SPROFS_BITS 10:0
924
 
925
//
926
// Default Exception Prefix
927
//
928
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
929
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
930
//
931
`define OR1200_SR_EPH_DEF       1'b0
932
 
933
/////////////////////////////////////////////////////
934
//
935
// Power Management (PM)
936
//
937
 
938
// Define it if you want PM implemented
939
`define OR1200_PM_IMPLEMENTED
940
 
941
// Bit positions inside PMR (don't change)
942
`define OR1200_PM_PMR_SDF 3:0
943
`define OR1200_PM_PMR_DME 4
944
`define OR1200_PM_PMR_SME 5
945
`define OR1200_PM_PMR_DCGE 6
946
`define OR1200_PM_PMR_UNUSED 31:7
947
 
948
// PMR offset inside PM group of registers
949
`define OR1200_PM_OFS_PMR 11'b0
950
 
951
// PM group
952
`define OR1200_SPRGRP_PM 5'd8
953
 
954
// Define if PMR can be read/written at any address inside PM group
955
`define OR1200_PM_PARTIAL_DECODING
956
 
957
// Define if reading PMR is allowed
958
`define OR1200_PM_READREGS
959
 
960
// Define if unused PMR bits should be zero
961
`define OR1200_PM_UNUSED_ZERO
962
 
963
 
964
/////////////////////////////////////////////////////
965
//
966
// Debug Unit (DU)
967
//
968
 
969
// Define it if you want DU implemented
970
`define OR1200_DU_IMPLEMENTED
971
 
972
//
973
// Define if you want HW Breakpoints
974
// (if HW breakpoints are not implemented
975
// only default software trapping is
976
// possible with l.trap insn - this is
977
// however already enough for use
978
// with or32 gdb)
979
//
980
//`define OR1200_DU_HWBKPTS
981
 
982
// Number of DVR/DCR pairs if HW breakpoints enabled
983
`define OR1200_DU_DVRDCR_PAIRS 8
984
 
985
// Define if you want trace buffer
986
// (for now only available for Xilinx Virtex FPGAs)
987
`ifdef OR1200_ASIC
988
`else
989
//`define OR1200_DU_TB_IMPLEMENTED
990
`endif
991
 
992
//
993
// Address offsets of DU registers inside DU group
994
//
995
// To not implement a register, do not define its address
996
//
997
`ifdef OR1200_DU_HWBKPTS
998
`define OR1200_DU_DVR0          11'd0
999
`define OR1200_DU_DVR1          11'd1
1000
`define OR1200_DU_DVR2          11'd2
1001
`define OR1200_DU_DVR3          11'd3
1002
`define OR1200_DU_DVR4          11'd4
1003
`define OR1200_DU_DVR5          11'd5
1004
`define OR1200_DU_DVR6          11'd6
1005
`define OR1200_DU_DVR7          11'd7
1006
`define OR1200_DU_DCR0          11'd8
1007
`define OR1200_DU_DCR1          11'd9
1008
`define OR1200_DU_DCR2          11'd10
1009
`define OR1200_DU_DCR3          11'd11
1010
`define OR1200_DU_DCR4          11'd12
1011
`define OR1200_DU_DCR5          11'd13
1012
`define OR1200_DU_DCR6          11'd14
1013
`define OR1200_DU_DCR7          11'd15
1014
`endif
1015
`define OR1200_DU_DMR1          11'd16
1016
`ifdef OR1200_DU_HWBKPTS
1017
`define OR1200_DU_DMR2          11'd17
1018
`define OR1200_DU_DWCR0         11'd18
1019
`define OR1200_DU_DWCR1         11'd19
1020
`endif
1021
`define OR1200_DU_DSR           11'd20
1022
`define OR1200_DU_DRR           11'd21
1023
`ifdef OR1200_DU_TB_IMPLEMENTED
1024
`define OR1200_DU_TBADR         11'h0ff
1025
`define OR1200_DU_TBIA          11'h1xx
1026
`define OR1200_DU_TBIM          11'h2xx
1027
`define OR1200_DU_TBAR          11'h3xx
1028
`define OR1200_DU_TBTS          11'h4xx
1029
`endif
1030
 
1031
// Position of offset bits inside SPR address
1032
`define OR1200_DUOFS_BITS       10:0
1033
 
1034
// DCR bits
1035
`define OR1200_DU_DCR_DP        0
1036
`define OR1200_DU_DCR_CC        3:1
1037
`define OR1200_DU_DCR_SC        4
1038
`define OR1200_DU_DCR_CT        7:5
1039
 
1040
// DMR1 bits
1041
`define OR1200_DU_DMR1_CW0      1:0
1042
`define OR1200_DU_DMR1_CW1      3:2
1043
`define OR1200_DU_DMR1_CW2      5:4
1044
`define OR1200_DU_DMR1_CW3      7:6
1045
`define OR1200_DU_DMR1_CW4      9:8
1046
`define OR1200_DU_DMR1_CW5      11:10
1047
`define OR1200_DU_DMR1_CW6      13:12
1048
`define OR1200_DU_DMR1_CW7      15:14
1049
`define OR1200_DU_DMR1_CW8      17:16
1050
`define OR1200_DU_DMR1_CW9      19:18
1051
`define OR1200_DU_DMR1_CW10     21:20
1052
`define OR1200_DU_DMR1_ST       22
1053
`define OR1200_DU_DMR1_BT       23
1054
`define OR1200_DU_DMR1_DXFW     24
1055
`define OR1200_DU_DMR1_ETE      25
1056
 
1057
// DMR2 bits
1058
`define OR1200_DU_DMR2_WCE0     0
1059
`define OR1200_DU_DMR2_WCE1     1
1060
`define OR1200_DU_DMR2_AWTC     12:2
1061
`define OR1200_DU_DMR2_WGB      23:13
1062
 
1063
// DWCR bits
1064
`define OR1200_DU_DWCR_COUNT    15:0
1065
`define OR1200_DU_DWCR_MATCH    31:16
1066
 
1067
// DSR bits
1068
`define OR1200_DU_DSR_WIDTH     14
1069
`define OR1200_DU_DSR_RSTE      0
1070
`define OR1200_DU_DSR_BUSEE     1
1071
`define OR1200_DU_DSR_DPFE      2
1072
`define OR1200_DU_DSR_IPFE      3
1073
`define OR1200_DU_DSR_TTE       4
1074
`define OR1200_DU_DSR_AE        5
1075
`define OR1200_DU_DSR_IIE       6
1076
`define OR1200_DU_DSR_IE        7
1077
`define OR1200_DU_DSR_DME       8
1078
`define OR1200_DU_DSR_IME       9
1079
`define OR1200_DU_DSR_RE        10
1080
`define OR1200_DU_DSR_SCE       11
1081
`define OR1200_DU_DSR_BE        12
1082
`define OR1200_DU_DSR_TE        13
1083
 
1084
// DRR bits
1085
`define OR1200_DU_DRR_RSTE      0
1086
`define OR1200_DU_DRR_BUSEE     1
1087
`define OR1200_DU_DRR_DPFE      2
1088
`define OR1200_DU_DRR_IPFE      3
1089
`define OR1200_DU_DRR_TTE       4
1090
`define OR1200_DU_DRR_AE        5
1091
`define OR1200_DU_DRR_IIE       6
1092
`define OR1200_DU_DRR_IE        7
1093
`define OR1200_DU_DRR_DME       8
1094
`define OR1200_DU_DRR_IME       9
1095
`define OR1200_DU_DRR_RE        10
1096
`define OR1200_DU_DRR_SCE       11
1097
`define OR1200_DU_DRR_BE        12
1098
`define OR1200_DU_DRR_TE        13
1099
 
1100
// Define if reading DU regs is allowed
1101
`define OR1200_DU_READREGS
1102
 
1103
// Define if unused DU registers bits should be zero
1104
`define OR1200_DU_UNUSED_ZERO
1105
 
1106
// Define if IF/LSU status is not needed by devel i/f
1107
`define OR1200_DU_STATUS_UNIMPLEMENTED
1108
 
1109
/////////////////////////////////////////////////////
1110
//
1111
// Programmable Interrupt Controller (PIC)
1112
//
1113
 
1114
// Define it if you want PIC implemented
1115
`define OR1200_PIC_IMPLEMENTED
1116
 
1117
// Define number of interrupt inputs (2-31)
1118
`define OR1200_PIC_INTS 20
1119
 
1120
// Address offsets of PIC registers inside PIC group
1121
`define OR1200_PIC_OFS_PICMR 2'd0
1122
`define OR1200_PIC_OFS_PICSR 2'd2
1123
 
1124
// Position of offset bits inside SPR address
1125
`define OR1200_PICOFS_BITS 1:0
1126
 
1127
// Define if you want these PIC registers to be implemented
1128
`define OR1200_PIC_PICMR
1129
`define OR1200_PIC_PICSR
1130
 
1131
// Define if reading PIC registers is allowed
1132
`define OR1200_PIC_READREGS
1133
 
1134
// Define if unused PIC register bits should be zero
1135
`define OR1200_PIC_UNUSED_ZERO
1136
 
1137
 
1138
/////////////////////////////////////////////////////
1139
//
1140
// Tick Timer (TT)
1141
//
1142
 
1143
// Define it if you want TT implemented
1144
`define OR1200_TT_IMPLEMENTED
1145
 
1146
// Address offsets of TT registers inside TT group
1147
`define OR1200_TT_OFS_TTMR 1'd0
1148
`define OR1200_TT_OFS_TTCR 1'd1
1149
 
1150
// Position of offset bits inside SPR group
1151
`define OR1200_TTOFS_BITS 0
1152
 
1153
// Define if you want these TT registers to be implemented
1154
`define OR1200_TT_TTMR
1155
`define OR1200_TT_TTCR
1156
 
1157
// TTMR bits
1158
`define OR1200_TT_TTMR_TP 27:0
1159
`define OR1200_TT_TTMR_IP 28
1160
`define OR1200_TT_TTMR_IE 29
1161
`define OR1200_TT_TTMR_M 31:30
1162
 
1163
// Define if reading TT registers is allowed
1164
`define OR1200_TT_READREGS
1165
 
1166
 
1167
//////////////////////////////////////////////
1168
//
1169
// MAC
1170
//
1171
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1172
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1173
 
1174
 
1175
//////////////////////////////////////////////
1176
//
1177
// Data MMU (DMMU)
1178
//
1179
 
1180
//
1181
// Address that selects between TLB TR and MR
1182
//
1183
`define OR1200_DTLB_TM_ADDR     7
1184
 
1185
//
1186
// DTLBMR fields
1187
//
1188
`define OR1200_DTLBMR_V_BITS    0
1189
`define OR1200_DTLBMR_CID_BITS  4:1
1190
`define OR1200_DTLBMR_RES_BITS  11:5
1191
`define OR1200_DTLBMR_VPN_BITS  31:13
1192
 
1193
//
1194
// DTLBTR fields
1195
//
1196
`define OR1200_DTLBTR_CC_BITS   0
1197
`define OR1200_DTLBTR_CI_BITS   1
1198
`define OR1200_DTLBTR_WBC_BITS  2
1199
`define OR1200_DTLBTR_WOM_BITS  3
1200
`define OR1200_DTLBTR_A_BITS    4
1201
`define OR1200_DTLBTR_D_BITS    5
1202
`define OR1200_DTLBTR_URE_BITS  6
1203
`define OR1200_DTLBTR_UWE_BITS  7
1204
`define OR1200_DTLBTR_SRE_BITS  8
1205
`define OR1200_DTLBTR_SWE_BITS  9
1206
`define OR1200_DTLBTR_RES_BITS  11:10
1207
`define OR1200_DTLBTR_PPN_BITS  31:13
1208
 
1209
//
1210
// DTLB configuration
1211
//
1212
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1213
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1214
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1215
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1216
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1217
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1218
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1219
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1220
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1221
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1222
 
1223
//
1224
// Cache inhibit while DMMU is not enabled/implemented
1225
//
1226
// cache inhibited 0GB-4GB              1'b1
1227
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1228
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1229
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1230
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1231
// cached 0GB-4GB                       1'b0
1232
//
1233
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1234
 
1235
 
1236
//////////////////////////////////////////////
1237
//
1238
// Insn MMU (IMMU)
1239
//
1240
 
1241
//
1242
// Address that selects between TLB TR and MR
1243
//
1244
`define OR1200_ITLB_TM_ADDR     7
1245
 
1246
//
1247
// ITLBMR fields
1248
//
1249
`define OR1200_ITLBMR_V_BITS    0
1250
`define OR1200_ITLBMR_CID_BITS  4:1
1251
`define OR1200_ITLBMR_RES_BITS  11:5
1252
`define OR1200_ITLBMR_VPN_BITS  31:13
1253
 
1254
//
1255
// ITLBTR fields
1256
//
1257
`define OR1200_ITLBTR_CC_BITS   0
1258
`define OR1200_ITLBTR_CI_BITS   1
1259
`define OR1200_ITLBTR_WBC_BITS  2
1260
`define OR1200_ITLBTR_WOM_BITS  3
1261
`define OR1200_ITLBTR_A_BITS    4
1262
`define OR1200_ITLBTR_D_BITS    5
1263
`define OR1200_ITLBTR_SXE_BITS  6
1264
`define OR1200_ITLBTR_UXE_BITS  7
1265
`define OR1200_ITLBTR_RES_BITS  11:8
1266
`define OR1200_ITLBTR_PPN_BITS  31:13
1267
 
1268
//
1269
// ITLB configuration
1270
//
1271
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1272
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1273
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1274
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1275
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1276
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1277
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1278
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1279
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1280
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1281
 
1282
//
1283
// Cache inhibit while IMMU is not enabled/implemented
1284
// Note: all combinations that use icpu_adr_i cause async loop
1285
//
1286
// cache inhibited 0GB-4GB              1'b1
1287
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1288
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1289
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1290
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1291
// cached 0GB-4GB                       1'b0
1292
//
1293
`define OR1200_IMMU_CI                  1'b0
1294
 
1295
 
1296
/////////////////////////////////////////////////
1297
//
1298
// Insn cache (IC)
1299
//
1300
 
1301
// 3 for 8 bytes, 4 for 16 bytes etc
1302
`define OR1200_ICLS             4
1303
 
1304
//
1305
// IC configurations
1306
//
1307
`ifdef OR1200_IC_1W_512B
1308
`define OR1200_ICSIZE   9     // 512
1309
`define OR1200_ICINDX   `OR1200_ICSIZE-2 // 7
1310
`define OR1200_ICINDXH  `OR1200_ICSIZE-1 // 8
1311
`define OR1200_ICTAGL   `OR1200_ICINDXH+1 // 9
1312
`define OR1200_ICTAG    `OR1200_ICSIZE-`OR1200_ICLS // 5
1313
`define OR1200_ICTAG_W  24
1314
`endif
1315
`ifdef OR1200_IC_1W_4KB
1316
`define OR1200_ICSIZE                   12                      // 4096
1317
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1318
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1319
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1320
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1321
`define OR1200_ICTAG_W                  21
1322
`endif
1323
`ifdef OR1200_IC_1W_8KB
1324
`define OR1200_ICSIZE                   13                      // 8192
1325
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1326
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1327
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1328
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1329
`define OR1200_ICTAG_W                  20
1330
`endif
1331
 
1332
 
1333
/////////////////////////////////////////////////
1334
//
1335
// Data cache (DC)
1336
//
1337
 
1338
// 3 for 8 bytes, 4 for 16 bytes etc
1339
`define OR1200_DCLS             4
1340
 
1341
// Define to perform store refill (potential performance penalty)
1342
// `define OR1200_DC_STORE_REFILL
1343
 
1344
//
1345
// DC configurations
1346
//
1347
`ifdef OR1200_DC_1W_4KB
1348
`define OR1200_DCSIZE                   12                      // 4096
1349
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1350
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1351
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1352
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1353
`define OR1200_DCTAG_W                  21
1354
`endif
1355
`ifdef OR1200_DC_1W_8KB
1356
`define OR1200_DCSIZE                   13                      // 8192
1357
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1358
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1359
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1360
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1361
`define OR1200_DCTAG_W                  20
1362
`endif
1363
 
1364
/////////////////////////////////////////////////
1365
//
1366
// Store buffer (SB)
1367
//
1368
 
1369
//
1370
// Store buffer
1371
//
1372
// It will improve performance by "caching" CPU stores
1373
// using store buffer. This is most important for function
1374
// prologues because DC can only work in write though mode
1375
// and all stores would have to complete external WB writes
1376
// to memory.
1377
// Store buffer is between DC and data BIU.
1378
// All stores will be stored into store buffer and immediately
1379
// completed by the CPU, even though actual external writes
1380
// will be performed later. As a consequence store buffer masks
1381
// all data bus errors related to stores (data bus errors
1382
// related to loads are delivered normally).
1383
// All pending CPU loads will wait until store buffer is empty to
1384
// ensure strict memory model. Right now this is necessary because
1385
// we don't make destinction between cached and cache inhibited
1386
// address space, so we simply empty store buffer until loads
1387
// can begin.
1388
//
1389
// It makes design a bit bigger, depending what is the number of
1390
// entries in SB FIFO. Number of entries can be changed further
1391
// down.
1392
//
1393
//`define OR1200_SB_IMPLEMENTED
1394
 
1395
//
1396
// Number of store buffer entries
1397
//
1398
// Verified number of entries are 4 and 8 entries
1399
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1400
// always match 2**OR1200_SB_LOG.
1401
// To disable store buffer, undefine
1402
// OR1200_SB_IMPLEMENTED.
1403
//
1404
`define OR1200_SB_LOG           2       // 2 or 3
1405
`define OR1200_SB_ENTRIES       4       // 4 or 8
1406
 
1407
 
1408
/////////////////////////////////////////////////
1409
//
1410
// Quick Embedded Memory (QMEM)
1411
//
1412
 
1413
//
1414
// Quick Embedded Memory
1415
//
1416
// Instantiation of dedicated insn/data memory (RAM or ROM).
1417
// Insn fetch has effective throughput 1insn / clock cycle.
1418
// Data load takes two clock cycles / access, data store
1419
// takes 1 clock cycle / access (if there is no insn fetch)).
1420
// Memory instantiation is shared between insn and data,
1421
// meaning if insn fetch are performed, data load/store
1422
// performance will be lower.
1423
//
1424
// Main reason for QMEM is to put some time critical functions
1425
// into this memory and to have predictable and fast access
1426
// to these functions. (soft fpu, context switch, exception
1427
// handlers, stack, etc)
1428
//
1429
// It makes design a bit bigger and slower. QMEM sits behind
1430
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1431
// used with QMEM and QMEM is seen by the CPU just like any other
1432
// memory in the system). IC/DC are sitting behind QMEM so the
1433
// whole design timing might be worse with QMEM implemented.
1434
//
1435
`define OR1200_QMEM_IMPLEMENTED
1436
 
1437
//
1438
// Base address and mask of QMEM
1439
//
1440
// Base address defines first address of QMEM. Mask defines
1441
// QMEM range in address space. Actual size of QMEM is however
1442
// determined with instantiated RAM/ROM. However bigger
1443
// mask will reserve more address space for QMEM, but also
1444
// make design faster, while more tight mask will take
1445
// less address space but also make design slower. If
1446
// instantiated RAM/ROM is smaller than space reserved with
1447
// the mask, instatiated RAM/ROM will also be shadowed
1448
// at higher addresses in reserved space.
1449
//
1450
`define OR1200_QMEM_IADDR       32'h0080_0000
1451
`define OR1200_QMEM_IMASK       32'hfff0_0000   // Max QMEM size 1MB
1452
`define OR1200_QMEM_DADDR  32'h0080_0000
1453
`define OR1200_QMEM_DMASK  32'hfff0_0000 // Max QMEM size 1MB
1454
 
1455
//
1456
// QMEM interface byte-select capability
1457
//
1458
// To enable qmem_sel* ports, define this macro.
1459
//
1460
//`define OR1200_QMEM_BSEL
1461
 
1462
//
1463
// QMEM interface acknowledge
1464
//
1465
// To enable qmem_ack port, define this macro.
1466
//
1467
//`define OR1200_QMEM_ACK
1468
 
1469
/////////////////////////////////////////////////////
1470
//
1471
// VR, UPR and Configuration Registers
1472
//
1473
//
1474
// VR, UPR and configuration registers are optional. If 
1475
// implemented, operating system can automatically figure
1476
// out how to use the processor because it knows 
1477
// what units are available in the processor and how they
1478
// are configured.
1479
//
1480
// This section must be last in or1200_defines.v file so
1481
// that all units are already configured and thus
1482
// configuration registers are properly set.
1483
// 
1484
 
1485
// Define if you want configuration registers implemented
1486
`define OR1200_CFGR_IMPLEMENTED
1487
 
1488
// Define if you want full address decode inside SYS group
1489
`define OR1200_SYS_FULL_DECODE
1490
 
1491
// Offsets of VR, UPR and CFGR registers
1492
`define OR1200_SPRGRP_SYS_VR            4'h0
1493
`define OR1200_SPRGRP_SYS_UPR           4'h1
1494
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1495
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1496
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1497
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1498
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1499
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1500
 
1501
// VR fields
1502
`define OR1200_VR_REV_BITS              5:0
1503
`define OR1200_VR_RES1_BITS             15:6
1504
`define OR1200_VR_CFG_BITS              23:16
1505
`define OR1200_VR_VER_BITS              31:24
1506
 
1507
// VR values
1508
`define OR1200_VR_REV                   6'h01
1509
`define OR1200_VR_RES1                  10'h000
1510
`define OR1200_VR_CFG                   8'h00
1511
`define OR1200_VR_VER                   8'h12
1512
 
1513
// UPR fields
1514
`define OR1200_UPR_UP_BITS              0
1515
`define OR1200_UPR_DCP_BITS             1
1516
`define OR1200_UPR_ICP_BITS             2
1517
`define OR1200_UPR_DMP_BITS             3
1518
`define OR1200_UPR_IMP_BITS             4
1519
`define OR1200_UPR_MP_BITS              5
1520
`define OR1200_UPR_DUP_BITS             6
1521
`define OR1200_UPR_PCUP_BITS            7
1522
`define OR1200_UPR_PMP_BITS             8
1523
`define OR1200_UPR_PICP_BITS            9
1524
`define OR1200_UPR_TTP_BITS             10
1525
`define OR1200_UPR_RES1_BITS            23:11
1526
`define OR1200_UPR_CUP_BITS             31:24
1527
 
1528
// UPR values
1529
`define OR1200_UPR_UP                   1'b1
1530
`ifdef OR1200_NO_DC
1531
`define OR1200_UPR_DCP                  1'b0
1532
`else
1533
`define OR1200_UPR_DCP                  1'b1
1534
`endif
1535
`ifdef OR1200_NO_IC
1536
`define OR1200_UPR_ICP                  1'b0
1537
`else
1538
`define OR1200_UPR_ICP                  1'b1
1539
`endif
1540
`ifdef OR1200_NO_DMMU
1541
`define OR1200_UPR_DMP                  1'b0
1542
`else
1543
`define OR1200_UPR_DMP                  1'b1
1544
`endif
1545
`ifdef OR1200_NO_IMMU
1546
`define OR1200_UPR_IMP                  1'b0
1547
`else
1548
`define OR1200_UPR_IMP                  1'b1
1549
`endif
1550
`define OR1200_UPR_MP                   1'b1    // MAC always present
1551
`ifdef OR1200_DU_IMPLEMENTED
1552
`define OR1200_UPR_DUP                  1'b1
1553
`else
1554
`define OR1200_UPR_DUP                  1'b0
1555
`endif
1556
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1557
`ifdef OR1200_DU_IMPLEMENTED
1558
`define OR1200_UPR_PMP                  1'b1
1559
`else
1560
`define OR1200_UPR_PMP                  1'b0
1561
`endif
1562
`ifdef OR1200_DU_IMPLEMENTED
1563
`define OR1200_UPR_PICP                 1'b1
1564
`else
1565
`define OR1200_UPR_PICP                 1'b0
1566
`endif
1567
`ifdef OR1200_DU_IMPLEMENTED
1568
`define OR1200_UPR_TTP                  1'b1
1569
`else
1570
`define OR1200_UPR_TTP                  1'b0
1571
`endif
1572
`define OR1200_UPR_RES1                 13'h0000
1573
`define OR1200_UPR_CUP                  8'h00
1574
 
1575
// CPUCFGR fields
1576
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1577
`define OR1200_CPUCFGR_HGF_BITS 4
1578
`define OR1200_CPUCFGR_OB32S_BITS       5
1579
`define OR1200_CPUCFGR_OB64S_BITS       6
1580
`define OR1200_CPUCFGR_OF32S_BITS       7
1581
`define OR1200_CPUCFGR_OF64S_BITS       8
1582
`define OR1200_CPUCFGR_OV64S_BITS       9
1583
`define OR1200_CPUCFGR_RES1_BITS        31:10
1584
 
1585
// CPUCFGR values
1586
`define OR1200_CPUCFGR_NSGF             4'h0
1587
`define OR1200_CPUCFGR_HGF              1'b0
1588
`define OR1200_CPUCFGR_OB32S            1'b1
1589
`define OR1200_CPUCFGR_OB64S            1'b0
1590
`define OR1200_CPUCFGR_OF32S            1'b0
1591
`define OR1200_CPUCFGR_OF64S            1'b0
1592
`define OR1200_CPUCFGR_OV64S            1'b0
1593
`define OR1200_CPUCFGR_RES1             22'h000000
1594
 
1595
// DMMUCFGR fields
1596
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1597
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1598
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1599
`define OR1200_DMMUCFGR_CRI_BITS        8
1600
`define OR1200_DMMUCFGR_PRI_BITS        9
1601
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1602
`define OR1200_DMMUCFGR_HTR_BITS        11
1603
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1604
 
1605
// DMMUCFGR values
1606
`ifdef OR1200_NO_DMMU
1607
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1608
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1609
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1610
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1611
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1612
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1613
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1614
`define OR1200_DMMUCFGR_RES1            20'h00000
1615
`else
1616
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1617
// bviyer: below is changed because we are unable to synthesize the damn thing
1618
// with the way opeNRISC wrote it
1619
// the 6 should be replaced with what ever OR1200_DTLB_INDXW
1620
`define OR1200_DMMUCFGR_NTS             3'd6    // Num TLB sets
1621
`define OR1200_DMMUCFGR_NAE             3'b0    // No ATB entries
1622
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1623
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1624
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1625
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1626
`define OR1200_DMMUCFGR_RES1            20'h00000
1627
`endif
1628
 
1629
// IMMUCFGR fields
1630
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1631
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1632
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1633
`define OR1200_IMMUCFGR_CRI_BITS        8
1634
`define OR1200_IMMUCFGR_PRI_BITS        9
1635
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1636
`define OR1200_IMMUCFGR_HTR_BITS        11
1637
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1638
 
1639
// IMMUCFGR values
1640
`ifdef OR1200_NO_IMMU
1641
`define OR1200_IMMUCFGR_NTW             2'b0    // Irrelevant
1642
`define OR1200_IMMUCFGR_NTS             3'b0    // Irrelevant
1643
`define OR1200_IMMUCFGR_NAE             3'b0    // Irrelevant
1644
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1645
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1646
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1647
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1648
`define OR1200_IMMUCFGR_RES1            20'h00000
1649
`else
1650
`define OR1200_IMMUCFGR_NTW             2'b0    // 1 TLB way
1651
// same problem as the Data TLB
1652
`define OR1200_IMMUCFGR_NTS             3'd6    // Num TLB sets
1653
`define OR1200_IMMUCFGR_NAE             3'b0    // No ATB entry
1654
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1655
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1656
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1657
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1658
`define OR1200_IMMUCFGR_RES1            20'h00000
1659
`endif
1660
 
1661
// DCCFGR fields
1662
`define OR1200_DCCFGR_NCW_BITS          2:0
1663
`define OR1200_DCCFGR_NCS_BITS          6:3
1664
`define OR1200_DCCFGR_CBS_BITS          7
1665
`define OR1200_DCCFGR_CWS_BITS          8
1666
`define OR1200_DCCFGR_CCRI_BITS         9
1667
`define OR1200_DCCFGR_CBIRI_BITS        10
1668
`define OR1200_DCCFGR_CBPRI_BITS        11
1669
`define OR1200_DCCFGR_CBLRI_BITS        12
1670
`define OR1200_DCCFGR_CBFRI_BITS        13
1671
`define OR1200_DCCFGR_CBWBRI_BITS       14
1672
`define OR1200_DCCFGR_RES1_BITS 31:15
1673
 
1674
// DCCFGR values
1675
`ifdef OR1200_NO_DC
1676
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1677
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1678
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1679
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1680
`define OR1200_DCCFGR_CCRI              1'b1    // Irrelevant
1681
`define OR1200_DCCFGR_CBIRI             1'b1    // Irrelevant
1682
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1683
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1684
`define OR1200_DCCFGR_CBFRI             1'b1    // Irrelevant
1685
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1686
`define OR1200_DCCFGR_RES1              17'h00000
1687
`else
1688
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1689
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1690
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4)      // 16 byte cache block
1691
`define OR1200_DCCFGR_CWS               1'b0    // Write-through strategy
1692
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1693
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1694
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1695
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1696
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1697
`define OR1200_DCCFGR_CBWBRI            1'b0    // Cache block WB reg not impl.
1698
`define OR1200_DCCFGR_RES1              17'h00000
1699
`endif
1700
 
1701
// ICCFGR fields
1702
`define OR1200_ICCFGR_NCW_BITS          2:0
1703
`define OR1200_ICCFGR_NCS_BITS          6:3
1704
`define OR1200_ICCFGR_CBS_BITS          7
1705
`define OR1200_ICCFGR_CWS_BITS          8
1706
`define OR1200_ICCFGR_CCRI_BITS         9
1707
`define OR1200_ICCFGR_CBIRI_BITS        10
1708
`define OR1200_ICCFGR_CBPRI_BITS        11
1709
`define OR1200_ICCFGR_CBLRI_BITS        12
1710
`define OR1200_ICCFGR_CBFRI_BITS        13
1711
`define OR1200_ICCFGR_CBWBRI_BITS       14
1712
`define OR1200_ICCFGR_RES1_BITS 31:15
1713
 
1714
// ICCFGR values
1715
`ifdef OR1200_NO_IC
1716
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1717
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1718
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1719
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1720
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1721
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1722
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1723
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1724
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1725
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1726
`define OR1200_ICCFGR_RES1              17'h00000
1727
`else
1728
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1729
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1730
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4)      // 16 byte cache block
1731
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1732
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1733
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1734
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1735
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1736
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1737
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1738
`define OR1200_ICCFGR_RES1              17'h00000
1739
`endif
1740
 
1741
// DCFGR fields
1742
`define OR1200_DCFGR_NDP_BITS           2:0
1743
`define OR1200_DCFGR_WPCI_BITS          3
1744
`define OR1200_DCFGR_RES1_BITS          31:4
1745
 
1746
// DCFGR values
1747
`ifdef OR1200_DU_HWBKPTS
1748
`define OR1200_DCFGR_NDP        3'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1749
`ifdef OR1200_DU_DWCR0
1750
`define OR1200_DCFGR_WPCI               1'b1
1751
`else
1752
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1753
`endif
1754
`else
1755
`define OR1200_DCFGR_NDP                3'h0    // Zero DVR/DCR pairs
1756
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1757
`endif
1758
`define OR1200_DCFGR_RES1               28'h0000000
1759
 
1760
`endif

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