OpenCores
URL https://opencores.org/ocsvn/claw/claw/trunk

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [or1200_dmmu_tlb.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 conte
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Data TLB                                           ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of DTLB.                                      ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.6  2004/04/05 08:29:57  lampret
48
// Merged branch_qmem into main tree.
49
//
50
// Revision 1.4.4.1  2003/12/09 11:46:48  simons
51
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
52
//
53
// Revision 1.4  2002/10/17 20:04:40  lampret
54
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
55
//
56
// Revision 1.3  2002/02/11 04:33:17  lampret
57
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
58
//
59
// Revision 1.2  2002/01/28 01:16:00  lampret
60
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
61
//
62
// Revision 1.1  2002/01/03 08:16:15  lampret
63
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
64
//
65
// Revision 1.8  2001/10/21 17:57:16  lampret
66
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
67
//
68
// Revision 1.7  2001/10/14 13:12:09  lampret
69
// MP3 version.
70
//
71
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
72
// no message
73
//
74
//
75
 
76
// synopsys translate_off
77
`include "timescale.v"
78
// synopsys translate_on
79
`include "or1200_defines.v"
80
 
81
//
82
// Data TLB
83
//
84
 
85
module or1200_dmmu_tlb(
86
        // Rst and clk
87
        clk, rst,
88
 
89
        // I/F for translation
90
        tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
91
 
92
`ifdef OR1200_BIST
93
        // RAM BIST
94
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
95
`endif
96
 
97
        // SPR access
98
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
99
);
100
 
101
parameter dw =32; // `OR1200_OPERAND_WIDTH;
102
parameter aw =32; // `OR1200_OPERAND_WIDTH;
103
 
104
//
105
// I/O
106
//
107
 
108
//
109
// Clock and reset
110
//
111
input                           clk;
112
input                           rst;
113
 
114
//
115
// I/F for translation
116
//
117
input                           tlb_en;
118
input   [aw-1:0]         vaddr;
119
output                          hit;
120
output  [31:`OR1200_DMMU_PS]    ppn;
121
output                          uwe;
122
output                          ure;
123
output                          swe;
124
output                          sre;
125
output                          ci;
126
 
127
`ifdef OR1200_BIST
128
//
129
// RAM BIST
130
//
131
input mbist_si_i;
132
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
133
output mbist_so_o;
134
`endif
135
 
136
//
137
// SPR access
138
//
139
input                           spr_cs;
140
input                           spr_write;
141
input   [31:0]                   spr_addr;
142
input   [31:0]                   spr_dat_i;
143
output  [31:0]                   spr_dat_o;
144
 
145
//
146
// Internal wires and regs
147
//
148
wire    [`OR1200_DTLB_TAG]      vpn;
149
wire                            v;
150
wire    [`OR1200_DTLB_INDXW-1:0] tlb_index;
151
wire                            tlb_mr_en;
152
wire                            tlb_mr_we;
153
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_in;
154
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_out;
155
wire                            tlb_tr_en;
156
wire                            tlb_tr_we;
157
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_in;
158
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_out;
159
`ifdef OR1200_BIST
160
//
161
// RAM BIST
162
//
163
wire                            mbist_mr_so;
164
wire                            mbist_tr_so;
165
wire                            mbist_mr_si = mbist_si_i;
166
wire                            mbist_tr_si = mbist_mr_so;
167
assign                          mbist_so_o = mbist_tr_so;
168
`endif
169
 
170
//
171
// Implemented bits inside match and translate registers
172
//
173
// dtlbwYmrX: vpn 31-19  v 0
174
// dtlbwYtrX: ppn 31-13  swe 9  sre 8  uwe 7  ure 6
175
//
176
// dtlb memory width:
177
// 19 bits for ppn
178
// 13 bits for vpn
179
// 1 bit for valid
180
// 4 bits for protection
181
// 1 bit for cache inhibit
182
 
183
//
184
// Enable for Match registers
185
//
186
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
187
 
188
//
189
// Write enable for Match registers
190
//
191
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
192
 
193
//
194
// Enable for Translate registers
195
//
196
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
197
 
198
//
199
// Write enable for Translate registers
200
//
201
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
202
 
203
//
204
// Output to SPRS unit
205
//
206
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
207
                        {vpn, tlb_index & {`OR1200_DTLB_INDXW{v}}, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
208
                (spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
209
                        {ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
210
                        32'h00000000;
211
 
212
//
213
// Assign outputs from Match registers
214
//
215
assign {vpn, v} = tlb_mr_ram_out;
216
 
217
//
218
// Assign to Match registers inputs
219
//
220
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
221
 
222
//
223
// Assign outputs from Translate registers
224
//
225
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
226
 
227
//
228
// Assign to Translate registers inputs
229
//
230
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
231
                        spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
232
                        spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
233
                        spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
234
                        spr_dat_i[`OR1200_DTLBTR_URE_BITS],
235
                        spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
236
 
237
//
238
// Generate hit
239
//
240
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
241
 
242
//
243
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
244
// spr_addr[5:0].
245
//
246
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
247
 
248
//
249
// Instantiation of DTLB Match Registers
250
//
251
or1200_spram_64x14 dtlb_mr_ram(
252
        .clk(clk),
253
        .rst(rst),
254
`ifdef OR1200_BIST
255
        // RAM BIST
256
        .mbist_si_i(mbist_mr_si),
257
        .mbist_so_o(mbist_mr_so),
258
        .mbist_ctrl_i(mbist_ctrl_i),
259
`endif
260
        .ce(tlb_mr_en),
261
        .we(tlb_mr_we),
262
        .oe(1'b1),
263
        .addr(tlb_index),
264
        .di(tlb_mr_ram_in),
265
        .do(tlb_mr_ram_out)
266
);
267
 
268
//
269
// Instantiation of DTLB Translate Registers
270
//
271
or1200_spram_64x24 dtlb_tr_ram(
272
        .clk(clk),
273
        .rst(rst),
274
`ifdef OR1200_BIST
275
        // RAM BIST
276
        .mbist_si_i(mbist_tr_si),
277
        .mbist_so_o(mbist_tr_so),
278
        .mbist_ctrl_i(mbist_ctrl_i),
279
`endif
280
        .ce(tlb_tr_en),
281
        .we(tlb_tr_we),
282
        .oe(1'b1),
283
        .addr(tlb_index),
284
        .di(tlb_tr_ram_in),
285
        .do(tlb_tr_ram_out)
286
);
287
 
288
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.