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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_dmmu_top.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Data MMU top level                                 ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all DMMU blocks.                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.9  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.7.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.7  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.6  2002/03/29 15:16:55  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5  2002/02/14 15:34:02  simons
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// Lapsus fixed.
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//
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// Revision 1.4  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.3  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.6  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.5  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/17 08:03:35  lampret
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// *** empty log message ***
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//
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// Revision 1.2  2001/07/22 03:31:53  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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102
//
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// Data MMU
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//
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module or1200_dmmu_top(
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        // Rst and clk
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        clk, rst,
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        // CPU i/f
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        dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
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        dcpu_tag_o, dcpu_err_o,
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        // SPR access
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // DC i/f
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        qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
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);
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126
parameter dw = 32;//`OR1200_OPERAND_WIDTH;
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parameter aw = 32; //`OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// CPU I/F
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//
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input                           dc_en;
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input                           dmmu_en;
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input                           supv;
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input   [aw-1:0]         dcpu_adr_i;
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input                           dcpu_cycstb_i;
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input                           dcpu_we_i;
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output  [3:0]                    dcpu_tag_o;
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output                          dcpu_err_o;
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151
//
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// SPR access
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//
154
input                           spr_cs;
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input                           spr_write;
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input   [aw-1:0]         spr_addr;
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input   [31:0]                   spr_dat_i;
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output  [31:0]                   spr_dat_o;
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160
`ifdef OR1200_BIST
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//
162
// RAM BIST
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//
164
input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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169
//
170
// DC I/F
171
//
172
input                           qmemdmmu_err_i;
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input   [3:0]                    qmemdmmu_tag_i;
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output  [aw-1:0]         qmemdmmu_adr_o;
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output                          qmemdmmu_cycstb_o;
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output                          qmemdmmu_ci_o;
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178
//
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// Internal wires and regs
180
//
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wire                            dtlb_spr_access;
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wire    [31:`OR1200_DMMU_PS]    dtlb_ppn;
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wire                            dtlb_hit;
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wire                            dtlb_uwe;
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wire                            dtlb_ure;
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wire                            dtlb_swe;
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wire                            dtlb_sre;
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wire    [31:0]                   dtlb_dat_o;
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wire                            dtlb_en;
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wire                            dtlb_ci;
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wire                            fault;
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wire                            miss;
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`ifdef OR1200_NO_DMMU
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`else
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reg                             dtlb_done;
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reg     [31:`OR1200_DMMU_PS]    dcpu_vpn_r;
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`endif
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199
//
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// Implemented bits inside match and translate registers
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//
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// dtlbwYmrX: vpn 31-10  v 0
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// dtlbwYtrX: ppn 31-10  swe 9  sre 8  uwe 7  ure 6
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//
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// dtlb memory width:
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// 19 bits for ppn
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// 13 bits for vpn
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// 1 bit for valid
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// 4 bits for protection
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// 1 bit for cache inhibit
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212
`ifdef OR1200_NO_DMMU
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214
//
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// Put all outputs in inactive state
216
//
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assign spr_dat_o = 32'h00000000;
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assign qmemdmmu_adr_o = dcpu_adr_i;
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assign dcpu_tag_o = qmemdmmu_tag_i;
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assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
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assign dcpu_err_o = qmemdmmu_err_i;
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assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
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`ifdef OR1200_BIST
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assign mbist_so_o = mbist_si_i;
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`endif
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`else
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//
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// DTLB SPR access
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//
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// 0A00 - 0AFF  dtlbmr w0
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// 0A00 - 0A3F  dtlbmr w0 [63:0]
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//
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// 0B00 - 0BFF  dtlbtr w0
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// 0B00 - 0B3F  dtlbtr w0 [63:0]
237
//
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assign dtlb_spr_access = spr_cs;
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240
//
241
// Tags:
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//
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// OR1200_DTAG_TE - TLB miss Exception
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// OR1200_DTAG_PE - Page fault Exception
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//
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assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
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248
//
249
// dcpu_err_o
250
//
251
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
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253
//
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// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
255
//
256
always @(posedge clk or posedge rst)
257
        if (rst)
258
                dtlb_done <=  1'b0;
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        else if (dtlb_en)
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                dtlb_done <=  dcpu_cycstb_i;
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        else
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                dtlb_done <=  1'b0;
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//
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// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
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//
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assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
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//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
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//
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// Cache Inhibit
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//
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assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
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//
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// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
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// one clock cycle after offset part.
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//
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always @(posedge clk or posedge rst)
280
        if (rst)
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                dcpu_vpn_r <=  {31-`OR1200_DMMU_PS{1'b0}};
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        else
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                dcpu_vpn_r <=  dcpu_adr_i[31:`OR1200_DMMU_PS];
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//
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// Physical address is either translated virtual address or
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// simply equal when DMMU is disabled
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//
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// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
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assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
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//
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// Output to SPRS unit
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//
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assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
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//
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// Page fault exception logic
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//
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assign fault = dtlb_done &
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                        (  (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
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                        || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
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                        || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
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                        || (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
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//
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// TLB Miss exception logic
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//
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assign miss = dtlb_done & !dtlb_hit;
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//
312
// DTLB Enable
313
//
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assign dtlb_en = dmmu_en & dcpu_cycstb_i;
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//
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// Instantiation of DTLB
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//
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or1200_dmmu_tlb or1200_dmmu_tlb(
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        // Rst and clk
321
        .clk(clk),
322
        .rst(rst),
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        // I/F for translation
325
        .tlb_en(dtlb_en),
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        .vaddr(dcpu_adr_i),
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        .hit(dtlb_hit),
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        .ppn(dtlb_ppn),
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        .uwe(dtlb_uwe),
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        .ure(dtlb_ure),
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        .swe(dtlb_swe),
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        .sre(dtlb_sre),
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        .ci(dtlb_ci),
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`ifdef OR1200_BIST
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        // RAM BIST
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        .mbist_si_i(mbist_si_i),
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        .mbist_so_o(mbist_so_o),
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        .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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        // SPR access
343
        .spr_cs(dtlb_spr_access),
344
        .spr_write(spr_write),
345
        .spr_addr(spr_addr),
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        .spr_dat_i(spr_dat_i),
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        .spr_dat_o(dtlb_dat_o)
348
);
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350
`endif
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endmodule

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