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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_gmultp2_32x32.v] - Blame information for rev 4

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1 2 conte
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic 32x32 multiplier                                    ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Generic 32x32 multiplier with pipeline stages.              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////  Modified by:                                                ////
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////      - Balaji V. Iyer, bviyer@ncsu.edu                       ////
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////  Advisor:                                                    ////
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////      - Dr. Tom Conte                                         ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2  2002/07/31 02:04:35  lampret
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// MAC now follows software convention (signed multiply instead of unsigned).
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.4  2001/12/04 05:02:35  lampret
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// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
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//
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// Revision 1.3  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.2  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.2  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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// 32x32 multiplier, no input/output registers
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// Registers inside Wallace trees every 8 full adder levels,
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// with first pipeline after level 4
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`ifdef OR1200_GENERIC_MULTP2_32X32
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`define OR1200_W 3:
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`define OR1200_WW 64
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module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
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//input   [`OR1200_W-1:0]  X;
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input [31:0] X;          // bviyer
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// input   [`OR1200_W-1:0]  Y;
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input [31:0] Y;          //bviyer
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input           CLK;
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input           RST;
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// output  [`OR1200_WW-1:0]  P;
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output[63:0] P;          // bviyer
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// reg     [`OR1200_WW-1:0]  p0;
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reg     [63:0]  p0;      // bviyer
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// reg     [`OR1200_WW-1:0]  p1;
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reg     [63:0]  p1;      // bviyer
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integer                   xi;
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integer                   yi;
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//
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// Conversion unsigned to signed
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//
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always @(X)
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        xi <= X;
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//
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// Conversion unsigned to signed
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//
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always @(Y)
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        yi <= Y;
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//
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// First multiply stage
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//
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always @(posedge CLK or posedge RST)
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        if (RST)
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                p0 <= `OR1200_WW'b0;
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        else
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                p0 <=  xi * yi;
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//
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// Second multiply stage
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//
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always @(posedge CLK or posedge RST)
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        if (RST)
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                p1 <= `OR1200_WW'b0;
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        else
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                p1 <=  p0;
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assign P = p1;
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endmodule
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`endif

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