OpenCores
URL https://opencores.org/ocsvn/claw/claw/trunk

Subversion Repositories claw

[/] [claw/] [trunk/] [or1200_cpu/] [or1200_ic_tag.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 conte
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's IC TAGs                                            ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instatiation of instruction cache tag rams                  ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.6  2004/04/08 11:00:46  simont
48
// Add support for 512B instruction cache.
49
//
50
// Revision 1.5  2004/04/05 08:29:57  lampret
51
// Merged branch_qmem into main tree.
52
//
53
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
54
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
55
//
56
// Revision 1.3  2002/10/24 22:19:04  mohor
57
// Signal scanb_eni renamed to scanb_en
58
//
59
// Revision 1.2  2002/10/17 20:04:40  lampret
60
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
61
//
62
// Revision 1.1  2002/01/03 08:16:15  lampret
63
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
64
//
65
// Revision 1.8  2001/10/21 17:57:16  lampret
66
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
67
//
68
// Revision 1.7  2001/10/14 13:12:09  lampret
69
// MP3 version.
70
//
71
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
72
// no message
73
//
74
// Revision 1.2  2001/08/09 13:39:33  lampret
75
// Major clean-up.
76
//
77
// Revision 1.1  2001/07/20 00:46:03  lampret
78
// Development version of RTL. Libraries are missing.
79
//
80
//
81
 
82
// synopsys translate_off
83
`include "timescale.v"
84
// synopsys translate_on
85
`include "or1200_defines.v"
86
 
87
module or1200_ic_tag(
88
        // Clock and reset
89
        clk, rst,
90
 
91
`ifdef OR1200_BIST
92
        // RAM BIST
93
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
94
`endif
95
 
96
        // Internal i/f
97
        addr, en, we, datain, tag_v, tag
98
);
99
 
100
parameter dw = `OR1200_ICTAG_W;
101
parameter aw = `OR1200_ICTAG;
102
 
103
//
104
// I/O
105
//
106
 
107
//
108
// Clock and reset
109
//
110
input                           clk;
111
input                           rst;
112
 
113
`ifdef OR1200_BIST
114
//
115
// RAM BIST
116
//
117
input mbist_si_i;
118
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
119
output mbist_so_o;
120
`endif
121
 
122
//
123
// Internal i/f
124
//
125
input   [aw-1:0]         addr;
126
input                           en;
127
input                           we;
128
input   [dw-1:0]         datain;
129
output                          tag_v;
130
output  [dw-2:0]         tag;
131
 
132
`ifdef OR1200_NO_IC
133
 
134
//
135
// Insn cache not implemented
136
//
137
assign tag = {dw-1{1'b0}};
138
assign tag_v = 1'b0;
139
`ifdef OR1200_BIST
140
assign mbist_so_o = mbist_si_i;
141
`endif
142
 
143
`else
144
 
145
//
146
// Instantiation of TAG RAM block
147
//
148
`ifdef OR1200_IC_1W_512B
149
or1200_spram_32x24 ic_tag0(
150
`endif
151
`ifdef OR1200_IC_1W_4KB
152
or1200_spram_256x21 ic_tag0(
153
`endif
154
`ifdef OR1200_IC_1W_8KB
155
or1200_spram_512x20 ic_tag0(
156
`endif
157
`ifdef OR1200_BIST
158
        // RAM BIST
159
        .mbist_si_i(mbist_si_i),
160
        .mbist_so_o(mbist_so_o),
161
        .mbist_ctrl_i(mbist_ctrl_i),
162
`endif
163
        .clk(clk),
164
        .rst(rst),
165
        .ce(en),
166
        .we(we),
167
        .oe(1'b1),
168
        .addr(addr),
169
        .di(datain),
170
        .do({tag, tag_v})
171
);
172
 
173
`endif
174
 
175
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.