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[/] [claw/] [trunk/] [or1200_cpu/] [or1200_immu_top.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Instruction MMU top level                          ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IMMU blocks.                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - cache inhibit                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.14  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
49
//
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// Revision 1.12.4.2  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.12.4.1  2003/07/08 15:36:37  lampret
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// Added embedded memory QMEM.
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//
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// Revision 1.12  2003/06/06 02:54:47  lampret
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// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
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//
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// Revision 1.11  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.10  2002/09/16 03:08:56  lampret
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// Disabled cache inhibit atttribute.
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//
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// Revision 1.9  2002/08/18 19:54:17  lampret
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// Added store buffer.
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//
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// Revision 1.8  2002/08/14 06:23:50  lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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//
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// Revision 1.7  2002/08/12 05:31:30  lampret
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// Delayed external access at page crossing.
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//
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// Revision 1.6  2002/03/29 15:16:56  lampret
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// Some of the warnings fixed.
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//
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// Revision 1.5  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4  2002/02/01 19:56:54  lampret
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// Fixed combinational loops.
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//
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// Revision 1.3  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.2  2002/01/14 06:18:22  lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.6  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.5  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/17 08:03:35  lampret
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// *** empty log message ***
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//
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// Revision 1.2  2001/07/22 03:31:53  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1  2001/07/20 00:46:03  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
111
 
112
// synopsys translate_off
113
`include "timescale.v"
114
// synopsys translate_on
115
`include "or1200_defines.v"
116
 
117
//
118
// Insn MMU
119
//
120
 
121
module or1200_immu_top(
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        // Rst and clk
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        clk, rst,
124
 
125
        // CPU i/f
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        ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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        icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
128
 
129
        // SPR access
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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132
`ifdef OR1200_BIST
133
        // RAM BIST
134
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
135
`endif
136
 
137
        // QMEM i/f
138
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
139
);
140
 
141
parameter dw = 32; // `OR1200_OPERAND_WIDTH;    // bviyer
142
parameter aw = 32; // `OR1200_OPERAND_WIDTH;    // bviyer
143
 
144
//
145
// I/O
146
//
147
 
148
//
149
// Clock and reset
150
//
151
input                           clk;
152
input                           rst;
153
 
154
//
155
// CPU I/F
156
//
157
input                           ic_en;
158
input                           immu_en;
159
input                           supv;
160
input   [aw-1:0]         icpu_adr_i;
161
input                           icpu_cycstb_i;
162
output  [aw-1:0]         icpu_adr_o;
163
output  [3:0]                    icpu_tag_o;
164
output                          icpu_rty_o;
165
output                          icpu_err_o;
166
 
167
//
168
// SPR access
169
//
170
input                           spr_cs;
171
input                           spr_write;
172
input   [aw-1:0]         spr_addr;
173
input   [31:0]                   spr_dat_i;
174
output  [31:0]                   spr_dat_o;
175
 
176
`ifdef OR1200_BIST
177
//
178
// RAM BIST
179
//
180
input mbist_si_i;
181
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
182
output mbist_so_o;
183
`endif
184
 
185
//
186
// IC I/F
187
//
188
input                           qmemimmu_rty_i;
189
input                           qmemimmu_err_i;
190
input   [3:0]                    qmemimmu_tag_i;
191
output  [aw-1:0]         qmemimmu_adr_o;
192
output                          qmemimmu_cycstb_o;
193
output                          qmemimmu_ci_o;
194
 
195
//
196
// Internal wires and regs
197
//
198
wire                            itlb_spr_access;
199
wire    [31:`OR1200_IMMU_PS]    itlb_ppn;
200
wire                            itlb_hit;
201
wire                            itlb_uxe;
202
wire                            itlb_sxe;
203
wire    [31:0]                   itlb_dat_o;
204
wire                            itlb_en;
205
wire                            itlb_ci;
206
wire                            itlb_done;
207
wire                            fault;
208
wire                            miss;
209
wire                            page_cross;
210
reg     [31:0]                   icpu_adr_o;
211
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
212
`ifdef OR1200_NO_IMMU
213
`else
214
reg                             itlb_en_r;
215
reg                             dis_spr_access;
216
`endif
217
 
218
//
219
// Implemented bits inside match and translate registers
220
//
221
// itlbwYmrX: vpn 31-10  v 0
222
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
223
//
224
// itlb memory width:
225
// 19 bits for ppn
226
// 13 bits for vpn
227
// 1 bit for valid
228
// 2 bits for protection
229
// 1 bit for cache inhibit
230
 
231
//
232
// icpu_adr_o
233
//
234
`ifdef OR1200_REGISTERED_OUTPUTS
235
always @(posedge rst or posedge clk)
236
        if (rst)
237
                icpu_adr_o <=  32'h0000_0100;
238
        else
239
                icpu_adr_o <=  icpu_adr_i;
240
`else
241
Unsupported !!!
242
`endif
243
 
244
//
245
// Page cross
246
//
247
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
248
//
249
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
250
 
251
//
252
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
253
// one clock cycle after offset part.
254
//
255
always @(posedge clk or posedge rst)
256
        if (rst)
257
                icpu_vpn_r <=  {31-`OR1200_IMMU_PS{1'b0}};
258
        else
259
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
260
 
261
`ifdef OR1200_NO_IMMU
262
 
263
//
264
// Put all outputs in inactive state
265
//
266
assign spr_dat_o = 32'h00000000;
267
assign qmemimmu_adr_o = icpu_adr_i;
268
assign icpu_tag_o = qmemimmu_tag_i;
269
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
270
assign icpu_rty_o = qmemimmu_rty_i;
271
assign icpu_err_o = qmemimmu_err_i;
272
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
273
`ifdef OR1200_BIST
274
assign mbist_so_o = mbist_si_i;
275
`endif
276
`else
277
 
278
//
279
// ITLB SPR access
280
//
281
// 1200 - 12FF  itlbmr w0
282
// 1200 - 123F  itlbmr w0 [63:0]
283
//
284
// 1300 - 13FF  itlbtr w0
285
// 1300 - 133F  itlbtr w0 [63:0]
286
//
287
assign itlb_spr_access = spr_cs & ~dis_spr_access;
288
 
289
//
290
// Disable ITLB SPR access
291
//
292
// This flop is used to mask ITLB miss/fault exception
293
// during first clock cycle of accessing ITLB SPR. In
294
// subsequent clock cycles it is assumed that ITLB SPR
295
// access was accomplished and that normal instruction fetching
296
// can proceed.
297
//
298
// spr_cs sets dis_spr_access and icpu_rty_o clears it.
299
//
300
always @(posedge clk or posedge rst)
301
        if (rst)
302
                dis_spr_access <=  1'b0;
303
        else if (!icpu_rty_o)
304
                dis_spr_access <=  1'b0;
305
        else if (spr_cs)
306
                dis_spr_access <=  1'b1;
307
 
308
//
309
// Tags:
310
//
311
// OR1200_DTAG_TE - TLB miss Exception
312
// OR1200_DTAG_PE - Page fault Exception
313
//
314
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
315
 
316
//
317
// icpu_rty_o
318
//
319
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
320
assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
321
 
322
//
323
// icpu_err_o
324
//
325
assign icpu_err_o = miss | fault | qmemimmu_err_i;
326
 
327
//
328
// Assert itlb_en_r after one clock cycle and when there is no
329
// ITLB SPR access
330
//
331
always @(posedge clk or posedge rst)
332
        if (rst)
333
                itlb_en_r <=  1'b0;
334
        else
335
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
336
 
337
//
338
// ITLB lookup successful
339
//
340
assign itlb_done = itlb_en_r & ~page_cross;
341
 
342
//
343
// Cut transfer if something goes wrong with translation. If IC is disabled,
344
// use delayed signals.
345
//
346
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
347
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
348
 
349
//
350
// Cache Inhibit
351
//
352
// Cache inhibit is not really needed for instruction memory subsystem.
353
// If we would do it, we would do it like this.
354
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
355
// However this causes a async combinational loop so we stick to
356
// no cache inhibit.
357
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
358
 
359
 
360
//
361
// Physical address is either translated virtual address or
362
// simply equal when IMMU is disabled
363
//
364
assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
365
 
366
//
367
// Output to SPRS unit
368
//
369
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
370
 
371
//
372
// Page fault exception logic
373
//
374
assign fault = itlb_done &
375
                        (  (!supv & !itlb_uxe)          // Execute in user mode not enabled
376
                        || (supv & !itlb_sxe));         // Execute in supv mode not enabled
377
 
378
//
379
// TLB Miss exception logic
380
//
381
assign miss = itlb_done & !itlb_hit;
382
 
383
//
384
// ITLB Enable
385
//
386
assign itlb_en = immu_en & icpu_cycstb_i;
387
 
388
//
389
// Instantiation of ITLB
390
//
391
or1200_immu_tlb or1200_immu_tlb(
392
        // Rst and clk
393
        .clk(clk),
394
        .rst(rst),
395
 
396
        // I/F for translation
397
        .tlb_en(itlb_en),
398
        .vaddr(icpu_adr_i),
399
        .hit(itlb_hit),
400
        .ppn(itlb_ppn),
401
        .uxe(itlb_uxe),
402
        .sxe(itlb_sxe),
403
        .ci(itlb_ci),
404
 
405
`ifdef OR1200_BIST
406
        // RAM BIST
407
        .mbist_si_i(mbist_si_i),
408
        .mbist_so_o(mbist_so_o),
409
        .mbist_ctrl_i(mbist_ctrl_i),
410
`endif
411
 
412
        // SPR access
413
        .spr_cs(itlb_spr_access),
414
        .spr_write(spr_write),
415
        .spr_addr(spr_addr),
416
        .spr_dat_i(spr_dat_i),
417
        .spr_dat_o(itlb_dat_o)
418
);
419
 
420
`endif
421
 
422
endmodule

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